SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 D D D D D D D OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54LVTH540 . . . FK PACKAGE (TOP VIEW) A3 A4 A5 A6 A7 OE2 D SN54LVTH540 . . . J OR W PACKAGE SN74LVTH540 . . . DB, DGV, DW, OR PW PACKAGE (TOP VIEW) A2 A1 OE1 VCC D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation High-Impedance State During Power Up and Power Down Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25C Power Off Disables Inputs/Outputs, Permitting Live Insertion ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (J) DIPs 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 Y3 Y4 Y5 A8 GND Y8 Y7 Y6 D description These octal buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVTH540 are ideal for driving bus lines or buffer memory address registers. These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LVTH540 is characterized for operation over the full military temperature range of -55C to 125C. The SN74LVTH540 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 FUNCTION TABLE INPUTS A OUTPUT Y L L H L H L H X X Z X H X Z OE1 OE2 L L logic symbol OE1 1 & 19 EN OE2 A1 A2 A3 A4 A5 A6 A7 A8 2 18 1 3 17 4 16 5 15 6 14 7 13 8 12 9 11 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) OE1 OE2 A1 1 19 2 18 To Seven Other Channels 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 Y1 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Current into any output in the low state, IO: SN54LVTH540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH540 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH540 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH540 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH540 SN74LVTH540 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current -24 -32 mA Low-level output current 48 64 mA t/v Input transition rise or fall rate t/VCC TA Power-up ramp rate 200 Operating free-air temperature -55 High-level input voltage 2 2 10 V 10 -40 ns/V s/V 200 125 V 85 C NOTE 4: Unused inputs must be held high or low to prevent them from floating. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = -18 mA IOH = -100 A VCC = 2.7 V, IOH = -8 mA IOH = -24 mA VCC = 3 V VOL VCC = 3 V Control inputs Data inputs Ioff VCC = 0 or 3.6 V, VCC = 3.6 V, VCC-0.2 2.4 -1.2 VCC-0.2 2.4 0.2 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 0.55 IOL = 64 mA VI = 5.5 V 10 10 1 1 1 1 -5 -5 VO = 3 V VO = 0.5 V IOZPU 100 75 75 -75 -75 A A A A 5 5 A -5 -5 A VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = Don't care 100 100 A IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = Don't care 100 100 A 0.19 0.19 ICC VCC = 3.6 3 6 V, V IO = 0, 0 VI = VCC or GND Outputs high ICC Ci Outputs low Outputs disabled VCC = 3 V to 3.6 V, One input at VCC - 0.6 V, Other inputs at VCC or GND VI = 3 V or 0 VO = 3 V or 0 5 5 0.19 0.19 0.2 0.2 3 Co 7 All typical values are at VCC = 3.3 V, TA = 25C. Unused pins at VCC or GND This parameter is warranted but not production tested. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 V 0.55 VI = 0 VCC = 0, VI or VO = 0 to 4.5 V VCC = 3.6 V, VCC = 3.6 V, V 2 0.5 IOZH IOZL UNIT V 2 IOL = 24 mA IOL = 16 mA VCC = 3 V Data inputs -1.2 VI = VCC or GND VI = VCC VCC = 3 3.6 6V SN74LVTH540 TYP MAX MIN 0.2 VI = 0.8 V VI = 2 V II(hold) MIN IOH = -32 mA IOL = 100 A 7V VCC = 2 2.7 II SN54LVTH540 TYP MAX TEST CONDITIONS POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 mA A mA 3 pF 7 pF SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH540 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y VCC = 3.3 V 0.3 V SN74LVTH540 VCC = 2.7 V VCC = 3.3 V 0.3 V VCC = 2.7 V MAX MIN TYP MAX 3.9 4.7 1.1 2.4 3.8 4.6 1 3.9 4.7 1.1 2.7 3.8 4.6 1.4 5.3 6.3 1.5 3.4 5.2 6.2 1.4 5.5 6.1 1.5 3.7 5.3 5.9 1.4 5.9 6.2 1.5 3.9 5.6 5.9 1.4 5.5 5.8 1.5 3.5 5 5.3 MIN MAX 1 MIN MIN UNIT MAX ns ns ns All typical values are at VCC = 3.3 V, TA = 25C. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LVTH540, SN74LVTH540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS681 - MARCH 1997 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) 1.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH tPLH VOH Output 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH - 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPZL and tPZH are the same as ten. F. tPLZ and tPHZ are the same as tdis. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("Critical Applications"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1996, Texas Instruments Incorporated