74ACT08SCX_NL - Fairchild Semiconductor

November 1988

Revised February 2005

74AC08 • 74ACT08 Quad 2-Input AND Gate

74AC08 • 74ACT08

Quad 2-Input AND Gate

General Descript ion

The AC/ACT08 contains four, 2-input AND gates. Features

■ICC reduced by 50% on 74AC only

■Outputs source/sink 24 mA

Ordering Code:

Device a ls o av ailable in Tape and Reel. Specify by append ing suffix lette r “X” to the ord ering co de. (PC no t available in Tape and Reel.)

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Use th is numbe r to order devic e.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT

is a trademark of Fairchild Semiconductor Corporation.

Order Number Package Packag e Descript ion

Number

74AC08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74AC08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC08MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74AC08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74AC08PC_NL

(Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT08SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT08SCX_NL

(Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74ACT08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT08MTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74ACT08PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74ACT08PC_NL

(Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pin Names Description

An, BnInputs

OnOutputs

www.fairchildsemi.com 2

74AC08 • 74ACT08

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions

Note 2: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exc eption, to e nsure that the system des ign is reliabl e over its power

supply, temperatu re, and output /input lo ading variable s. Fairch ild do es not

recomm end operation of FACT

circuits outside databo ok s pecificat ions.

DC Electrical Characteristics for AC

Note 3: All outputs loaded; thresholds on input associated with output under test.

Note 4: Maximum test du ration 2.0 m s, one output loaded at a time.

Note 5: IIN and ICC @ 3. 0V are gu aranteed t o be less th an or equa l to th e respectiv e limit @ 5. 5V VCC.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Diode Current (IIK)



0.5V



20 mA

VCC



0.5V



20 mA

DC Input Voltage (VI)



0.5V to VCC



0.5V

DC Output Diode Current (IOK)



0.5V



20 mA

VCC



0.5V



20 mA

DC O utput Voltage (VO)



0.5V to VCC



0.5V

DC Output Source

or Sink Current (IO)

50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)

50 mA

Storage Temperature (TSTG)



C to



150

Junction Temperature (TJ)

PDIP 140

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Operating Temperature (TA)



C to



Minimum Input Edge Rate (

AC Devices

VIN from 30% to 70% of VCC

VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate (

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC TA





C to



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT

0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC



0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT

0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC



0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9

Output Voltage 4.5 4.49 4.4 4.4 V IOUT



5.5 5.49 5.4 5.4 VIN

VIL or VIH

3.0 2.56 2.46 IOH



12 mA

4.5 3.86 3.76 V IOH



24 mA

5.5 4.86 4.76 IOH



24 mA (Note 3)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1

Output Voltage 4.5 0.001 0.1 0.1 V IOUT

5.5 0.001 0.1 0.1 VIN

VIL or VIH

3.0 0.36 0.44 IOL

12 mA

4.5 0.36 0.44 V IOL

24 mA

5.5 0.36 0.44 IOL

24 mA (Note 3)

IIN Maximum Input 5.5

0.1

1.0

VCC, GND

(Note 5) Leakage Current

IOLD Minimum Dynamic 5.5 75 mA VOLD

1.65V Max

IOHD Output Current (Note 4) 5.5



75 mA VOHD

3.85V Min

ICC Maximum Quiescent 5.5 2.0 20.0

VCC

(Note 5) Supply Current or GND

3 www.fairchildsemi.com

74AC08 • 74ACT08

DC Electrical Characteristics for ACT

Note 6: All outputs loaded; thresholds on input associated with output under test.

Note 7: Maximum test duration 2.0 ms, one output loaded at a time.

AC Electrical Characteristics for AC

Note 8: Voltage Range 3. 3 is 3. 3V

0.3V

Voltage Range 5.0 is 5.0V

0.5V

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5. 0 is 5.0V

0.5V

Capacitance

Symbol Parameter VCC TA





C to



CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT

0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC



0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT

0.1V

Input Voltage 5.5 1.5 0.8 0.8 or VCC



0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI

OUT



Output Voltage 5.5 5.49 5.4 5.4 VIN

VIL or VIH

4.5 3.86 3.76 VIOH



24 mA

5.5 4.86 4.76 IOH



24 mA (Note 6)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI

OUT

Output Voltage 5.5 0.001 0.1 0.1 VIN

VIL or VIH

4.5 0.36 0.44 VIOL

24 mA

5.5 0.36 0.44 IOL

24 mA (Note 6)

IIN Maximum Input Leakage Current 5.5

0.1

1.0

VCC, GND

ICCT Maximum ICC/Input 5.5 0.6 1.5 mA VI

VCC



2.1V

IOLD Minimum Dynamic Output Current 5.5 75 mA VOLD

1.65V Max

IOHD (Note 7) 5.5



75 mA VOHD

3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0

AVIN

VCC

Supply Current or GND

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 8) Min Typ Max Min Max

tPLH Propagation Delay 3.3 1.5 7.5 9.5 1.0 10.0 ns

5.0 1.5 5.5 7.5 1.0 8.5

tPHL Propagation Delay 3.3 1.5 7.0 8.5 1.0 9.0 ns

5.0 1.5 5.5 7.0 1.0 7.5

VCC TA





C to



Symbol Parameter (V) CL

50 pF CL

50 pF Units

(Note 9) Min Typ Max Min Max

tPLH Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns

tPHL Propagation Delay 5.0 1.0 6.5 9.0 1.0 10.0 ns

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC

OPEN

CPD Power Dissipation Capacitance 20.0 pF VCC

5.0V

www.fairchildsemi.com 4

74AC08 • 74ACT08

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

5 www.fairchildsemi.com

74AC08 • 74ACT08

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

www.fairchildsemi.com 6

74AC08 • 74ACT08

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

7 www.fairchildsemi.com

74AC08 • 74ACT08 Quad 2-Input AND Gate

Physical Dim ensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does not assum e any responsibility for use of any circuitry described, no cir cuit patent licenses are im plied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use provided in the l abe li ng, can be re a-

sonably expected to result in a significant injury to the

user.

2. A crit ical com ponen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife suppor t

device or system, or to affect its safety or effectiveness.