DS1388
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
General Description
The DS1388 I2C real-time clock (RTC), supervisor, and
EEPROM is a multifunction device that provides a
clock/calendar, programmable watchdog timer, power-
supply monitor with reset, and 512 bytes of EEPROM.
The clock provides hundredths of seconds, seconds,
minutes, and hours, and operates in 24-hour or 12-hour
format with an AM/PM indicator. The calendar provides
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. A watchdog timer provides a reset for an unre-
sponsive microprocessor. It is programmable in 10ms
intervals from 0.01 to 99.99 seconds. A temperature-
compensated voltage reference and comparator circuit
monitors the status of VCC. If a primary power failure is
detected, the device automatically switches to the
backup supply and drives the reset output to the active
state. The backup supply maintains time and date
operation in the absence of VCC. When VCC returns to
nominal levels, the reset is held low for a period to allow
the power supply and processor to stabilize. The
device also has a pushbutton reset controller, which
debounces a reset input signal. The device is
accessed through an I2C serial interface.
Applications
Portable Instruments
Point-of-Sale Equipment
Network Interface Cards
Wireless Equipment
Features
oFast (400kHz) I2C Interface
oRTC Counts Hundredths of Seconds, Seconds,
Minutes, Hours, Day, Date, Month, and Year with
Leap Year Compensation Valid Up to 2100
oProgrammable Watchdog Timer
oAutomatic Power-Fail Detect and Switch Circuitry
oReset Output with Pushbutton Reset Input
Capability
o512 x 8 Bits of EEPROM
oIntegrated Trickle-Charge Capability for Backup
Supply
oThree Operating Voltages: 5.0V, 3.3V, and 3.0V
oLow Timekeeping Voltage Down to 1.3V
o-40°C to +85°C Temperature Range
oUL Recognized
SO
TOP VIEW
+
DS1388
SCL
SDAGND
1
2
8
7
VCC
RSTX2
VBACKUP
X1
3
4
6
5
Pin Configuration
RST
VCC
X1
SCL
X2
CPU
VCC
SDA
GND
VCC
RPU
RPU = tR/CB
RPU
VCC CRYSTAL
VBACKUP
DS1388
Typical Operating Circuit
19-4984; Rev 4 4/13
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information
PART TEMP RANGE PIN-PACKAGE TOP
MARK
DS1388Z-5+ -40°C to +85°C 8 SO (150 mils) DS1388-5
DS1388Z-33+ -40°C to +85°C 8 SO (150 mils) DS138833
DS1388Z-3+ -40°C to +85°C 8 SO (150 mils) DS1388-3
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
2 Maxim Integrated
DS1388
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCC or VBACKUP Pins
Relative to Ground.............................................-0.3V to +6.0V
Voltage Range on Inputs Relative
to Ground ...............................................-0.3V to (VCC + 0.3V)
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)..170°C/W
Junction-to-Case Thermal Resistance (θJC) (Note 1) ......40°C/W
Operating Temperature Range
(noncondensing) .............................................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DS1388Z-5 4.5 5 5.5
DS1388Z-33 2.97 3.3 3.63
Supply Voltage VCC (Note 3)
DS1388Z-3 2.7 3 3.3
V
Logic 1 VIH (Note 3) 0.7 x
VCC
VCC +
0.3 V
Logic 0 VIL (Note 3) -0.3 +0.3 x
VCC V
Pullup Voltage (SCL, SDA),
VCC = 0V VPU 5.5 V
VBACKUP Voltage VBACKUP (Note 3) 1.3 3.0 5.5 V
DS1388Z-5 4.15 4.33 4.50
DS1388Z-33 2.70 2.88 2.97
Power-Fail Voltage VPF (Note 3)
DS1388Z-3 2.45 2.60 2.70
V
DC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
R1 (Notes 4, 5) 250
R2 (Note 6) 2000
Trickle-Charger Current-Limiting
Resistors
R3 (Note 7) 4000
Input Leakage (SCL) ILI -1 +1 μA
I/O Leakage (SDA) ILO -1 +1 μA
I/O Leakage (RST) ILORST (Note 8) -200 +10 μA
SDA Logic 0 Output
(VOL = 0.15 x VCC)IOLDOUT 3 mA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 3
DS1388
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = VCC(MIN) to VCC(MAX), TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC > 2V; VOL = 0.4V 3.0
1.8V < VCC < 2V; VOL = 0.2 x VCC 3.0
mA
RST Logic 0 Output IOLSIR
1.3V < VCC < 1.8V; VOL = 0.2 x VCC 250 μA
DS1388Z-5 600
DS1388Z-33 250
VCC Active Current, EEPROM
Read, I2C Read/Write Access ICCER (Note 9)
DS1388Z-3 225
μA
DS1388Z-5 1.0
DS1388Z-33 0.70
VCC Active Current, EEPROM
Write Cycle ICCEW (Note 9)
DS1388Z-3 0.65
mA
DS1388Z-5 270
DS1388Z-33 100 150
VCC Standby Current ICCS (Note 10)
DS1388Z-3 140
μA
VBACKUP Leakage Current
(VBACKUP = 3.7V,
VCC = VCC(MAX))
IBACKUPLKG 15 100 nA
TA = +25°C (guaranteed by design) 200k
EEPROM Write/Erase Cycles tWR TA = -40°C to +85°C (guaranteed by
design) 50k
Cycles
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, VBACKUP = 3.7V, TA= +25°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VBACKUP Current, OSC On
(EOSC = 0), SDA = SCL = 0V IBACKUP (Note 11) 410 550 nA
VBACKUP Current, OSC Off
(EOSC = 1), SDA = SCL = 0V
(Data Retention)
IBACKUPDR (Note 11) 10 100 nA
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
4 Maxim Integrated
DS1388
AC ELECTRICAL CHARACTERISTICS
(VCC = VCC(MIN) to VCC(MAX), TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Fast mode 100 400
SCL Clock Frequency fSCL Standard mode 0 100 kHz
Fast mode 1.3
Bus Free Time Between a STOP
and START Condition tBUF Standard mode 4.7 μs
Fast mode 0.6
Hold Time (Repeated) START
Condition (Note 12) tHD:STA Standard mode 4.0 μs
Fast mode 1.3
LOW Period of SCL Clock tLOW Standard mode 4.7 μs
Fast mode 0.6
HIGH Period of SCL Clock tHIGH Standard mode 4.0 μs
Fast mode 0.6
Setup Time for a Repeated
START Condition tSU:STA Standard mode 4.7 μs
Fast mode 0 0.9
Data Hold Time (Notes 13, 14) tHD:DAT Standard mode 0 μs
Fast mode 100
Data Setup Time (Note 15) tSU:DAT Standard mode 250 ns
Fast mode 300
Rise Time of Both SDA and SCL
Signals (Note 16) tRStandard mode
20 +
0.1CB 1000
ns
Fast mode 300
Fall Time of Both SDA and SCL
Signals (Note 16) tFStandard mode
20 +
0.1CB 300
ns
Fast mode 0.6
Setup Time for STOP Condition tSU:STO Standard mode 4.0 μs
Capacitive Load for Each Bus
Line CB (Note 16) 400 pF
I/O Capacitance (SDA, SCL, RST) CI/O +25°C 10 pF
Pushbutton Debounce PBDB 160 180 ms
Reset Active Time tRST 160 180 ms
EEPROM Write Cycle Time tWEE 8 10 ms
Oscillator Stop Flag (OSF) Delay tOSF (Note 17) 20 ms
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 5
DS1388
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA= -40°C to +85°C) (Note 2) (Figures 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC Detect to Recognize Inputs
(VCC Rising) tRST (Note 18) 160 180 ms
VCC Fall Time; VPF(MAX) to VPF(MIN) t
F 300 μs
VCC Rise Time; VPF(MIN) to VPF(MAX) t
R 0 μs
OUTPUTS
VCC
VPF(MAX)
INPUTS
HIGH IMPEDANCE
RST
DON'T CARE
VALID
RECOGNIZED RECOGNIZED
VALID
VPF(MIN)
tRST
tRPU
tR
tF
VPF VPF
Figure 1. Power-Up/Down Timing
tRST
PBDB
RST
Figure 2. Pushbutton Reset Timing
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
6 Maxim Integrated
DS1388
WARNING: Under no circumstances are negative undershoots, of any
amplitude, allowed when device is in write protection.
Note 2: Limits at -40°C are guaranteed by design and are not production tested.
Note 3: All voltages are referenced to ground.
Note 4: Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A5h.
Note 5: The use of the 250Ωtrickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.
Note 6: Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A6h.
Note 7: Measured at VCC = typ, VBACKUP = 0V, register 0Ah, block 0h = A7h.
Note 8: The RST pin has an internal 50kΩpullup resistor to VCC.
Note 9: ICCA—SCL clocking at max frequency = 400kHz.
Note 10: Specified with I2C bus inactive.
Note 11: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 12: After this period, the first clock pulse is generated.
Note 13: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal)
to bridge the undefined region of the falling edge of SCL.
Note 14: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 15: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT 250ns must then be met. This
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns
before the SCL line is released.
Note 16: CB—total capacitance of one bus line in pF.
Note 17: The parameter tOSF is the period of time that the oscillator must be stopped for the OSF flag to be set over the voltage
range of 0V VCC VCC(MAX) and 1.3V VBACKUP 3.7V.
Note 18: If the oscillator is disabled or stopped, RST goes inactive after tRST plus the startup time of the oscillator.
VCC FALLING vs. RST DELAY
DS1388 toc04
VCC FALLING (V/ms)
RESET DELAY (μs)
1010.1
100
1000
10,000
10
0.01 100
VCC = VPF + 0.1V TO 0V
IBACKUP SUPPLY CURRENT VOLTAGE
vs. TEMPERATURE
DS1388 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
65
503520
5
10-25
300
350
400
450
500
550
600
250
-40 80
VBACKUP = 3V
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
DS1388 toc03
SUPPLY (V)
FREQUENCY (Hz)
5.34.8
3.8 4.3
2.3 2.8 3.3
1.8
32768.05
32768.10
32768.15
32768.20
32768.25
32768.30
32768.35
32768.40
32768.45
32768.00
1.3
IBACKUP SUPPLY CURRENT VOLTAGE
vs. VBACKUP
DS1388 toc01
VBACKUP (V)
SUPPLY CURRENT (nA)
5.3
4.9
4.5
4.1
3.73.32.92.52.11.7
300
350
400
450
500
250
1.3
VCC = 0V
Typical Operating Characteristics
(VCC = +3.3V, TA = +25°C, unless otherwise noted.)
Maxim Integrated 7
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
DS1388
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
8 Maxim Integrated
DS1388
Pin Description
Block Diagram
PIN NAME FUNCTION
1 X1
2 X2
Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for
operation with a crystal having a specified load capacitance (CL) of 6.0pF. Pin X1 is the input to the
oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal
oscillator, pin X2, is left unconnected if an external oscillator is connected to pin X1.
3 VBACKUP
Connection for a Secondary Power Supply. Supply voltage must be held between 1.3V and 5.5V for proper
operation. This pin can be connected to a primary cell, such as a lithium button cell. Additionally, this pin
can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. If not
used, this pin must be connected to ground. UL recognized to ensure against reverse charging current
when used with a lithium battery (www.maximintegrated.com/qa/info/ul/).
4 GND Ground
5 SDA
Serial Data Output. SDA is the input/output for the I2C serial interface. This pin is open drain and requires
an external pullup resistor.
6 SCL
Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement
on the serial interface.
7 RST
Active-Low, Open-Drain Reset Output. This pin indicates the status of VCC relative to the VPF
specification. As VCC falls below VPF, the RST pin is driven low. When VCC exceeds VPF, for tRST, the RST
pin is driven high impedance. The active-low, open-drain output is combined with a debounced
pushbutton input function. This pin can be activated by a pushbutton reset request. It has an internal
50k nominal value pullup resistor to VCC. No external pullup resistors should be connected. If the
crystal oscillator is disabled, the startup time of the oscillator is added to the tRST delay.
8 VCC DC Power Pin for Primary Power Supply
BLOCK 2BLOCK 1BLOCK 0
CLOCK AND CALENDAR
REGISTERS
POWER CONTROL
AND
TRICKLE CHARGER
I2C
INTERFACE EEPROM
INTERFACE
EEPROM EEPROM
WATCHDOG
TIMER
STATUS CONTROL/
TRICKLE
X2
X1
VCC
GND
VBACKUP
RST
SDA
SCL
CL
CL
DS1388
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 9
DS1388
Detailed Description
The DS1388 I2C RTC, supervisor, and EEPROM is a
multifunction device that provides a clock/calendar,
programmable watchdog timer, power-supply monitor
with reset, and 512 bytes of EEPROM. The clock pro-
vides hundredths of seconds, seconds, minutes, and
hours, and operates in 24-hour or 12-hour format with
an AM/PM indicator. The calendar provides day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year. A
watchdog timer provides a reset for an unresponsive
microprocessor. It is programmable in 10ms intervals
from 0.01 to 99.99 seconds. A temperature-compensat-
ed voltage reference and comparator circuit monitors
the status of VCC. If a primary power failure is detected,
the device automatically switches to the backup supply
and drives the reset output to the active state. When
VCC returns to nominal levels, the reset is held low for a
period to allow the power supply and processor to sta-
bilize. The device also has a pushbutton reset con-
troller, which debounces a reset input signal. The
device is accessed through an I2C serial interface.
Operation
The DS1388 operates as a slave device on the I2C bus.
Access is obtained by implementing a START condition
and providing a device identification code followed by
data. Subsequent registers can be accessed sequen-
tially until a STOP condition is executed. See the
Block
Diagram
, which shows the main elements of the serial
real-time clock.
Power Control
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the VCC level. The
device is fully accessible and data can be written and
read when VCC is greater than VPF. However, when
VCC falls below VPF, the internal clock registers are
blocked from any access. If VPF is less than VBACKUP,
the device power is switched from VCC to VBACKUP
when VCC drops below VPF. If VPF is greater than
VBACKUP, the device power is switched from VCC to
VBACKUP when VCC drops below VBACKUP. The regis-
ters are maintained from the VBACKUP source until VCC
is returned to nominal levels (Table 1). After VCC
returns above VPF, read and write access is allowed
after RST goes high (Figure 1).
On first application of power to the device, the time and
date registers are set to 00/00/00 00 00:00:00
(DD/MM/YY DOW HH:MM:SS). The user should initial-
ize all RTC registers to valid date and time settings.
Oscillator Circuit
The DS1388 uses an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several
crystal parameters for the external crystal. Using a
crystal with the specified characteristics, the startup
time is usually less than one second.
SUPPLY CONDITION READ/WRITE
ACCESS
POWERED
BY
No VBACKUP
No VCC
Yes VCC
Yes VCC
PARAMETER
SYMBOL MIN TYP MAX
UNITS
Nominal
Frequency fO
32.768
kHz
Series
Resistance ESR 50
kΩ
Load
Capacitance CL6pF
*
The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Dallas Real-Time Clocks for addi-
tional specifications.
Table 1. Power Control
Table 2. Crystal Specifications*
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
10 Maxim Integrated
DS1388
Clock Accuracy
The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise
coupled into the oscillator circuit can result in the clock
running fast. Figure 3 shows a typical PC board layout
for isolation of the crystal and oscillator from noise.
Refer to Application Note 58:
Crystal Considerations
with Dallas Real-Time Clock
s for detailed information.
Address Map
Figure 4 shows the address map for the DS1388. The
memory map is divided into three blocks. The memory
block accessed is determined by the value of the block
address bits in the slave address byte. The timekeep-
ing registers reside in block 0h. During a multibyte
access of the timekeeping registers, when the internal
address pointer reaches 0Ch, it wraps around to loca-
tion 00h. On an I2C START or address pointer incre-
menting to location 00h, the current time is transferred
to a second set of registers. The time information is
read from these secondary registers, while the clock
may continue to run. This eliminates the need to reread
the registers in case the main registers update during a
read. The EEPROM is divided into two 256-byte blocks
located in blocks 1h and 2h. During a multibyte read of
the EEPROM registers, when the internal address point-
er reaches FFh, it wraps around to location 00h of the
block of EEPROM specified in the block address.
During a multibyte write of the EEPROM registers, when
the internal address pointer reaches the end of the cur-
rent 8-byte EEPROM page, it wraps around to the
beginning of the EEPROM page. See the
Write
Operation
section for details.
To avoid rollover issues when writing to the time and
date registers, all registers should be written before the
hundredths-of-seconds register reaches 99 (BCD).
Hundredths-of-Seconds
Generator
The hundredths-of-seconds generator circuit shown in
the
Block Diagram
is a state machine that divides the
incoming frequency (4096Hz) by 41 for 24 cycles and
40 for 1 cycle. This produces a 100Hz output that is
slightly off during the short term, and is exactly correct
every 250ms. The divide ratio is given by:
Ratio = [41 x 24 + 40 x 1] / 25 = 40.96
Thus, the long-term average frequency output is
exactly 100Hz.
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
GND
X2
X1
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Figure 3. Layout Example
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 11
DS1388
ADDRESS
BLK WORD BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE
0h 00h Tenth Seconds Hundredths of Seconds Hundredths of
Seconds 0099
0h 01h 0 10 Seconds Seconds Seconds 0059
0h 02h 0 10 Minutes Minutes Minutes 0059
AM/
PM 10 Hour
0h 03h 0 12/24
10 Hour
Hours Hours
1–12+
AM/PM
0023
0h 04h 0 0 0 0 X Day Day 0107
0h 05h 0 0 10 Date Date Date 0131
0h 06h 0 0 X 10
Month Month Month 0112
0h 07h 10 Year Year Year 0099
0h 08h Watchdog Tenths of Seconds Watchdog Hundredths of Seconds
Watchdog
Hundredth
Seconds
0099
0h 09h Watchdog Ten Seconds Watchdog Seconds Watchdog
Seconds 0099
0h 0Ah TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Trickle Charger
0h 0Bh OSF WF 0 0 0 0 0 0 Flag
0h 0Ch EOSC 0 0 0 0 0 WDE WD/RST Control
1h 00FFh 256 x 8 EEPROM EEPROM 00–FFh
2h 00FFh 256 x 8 EEPROM EEPROM 00–FFh
Figure 4. Address Map
Note: Unless otherwise specified, the state of the registers is not defined when power (VCC and VBACKUP) is first applied.
X = General-purpose read/write bit.
0 = Always reads as a zero.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Figure 4 illustrates
the RTC registers. The time and calendar are set or ini-
tialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The end of the
month date is automatically adjusted for months with
fewer than 31 days, including corrections for leap years
through 2099. The day-of-week register increments at
midnight. Values that correspond to the day-of-week
are user-defined but must be sequential (i.e., if 1
equals Sunday, then 2 equals Monday, and so on).
Illogical time and date entries result in undefined oper-
ation. The DS1388 can be run in either 12-hour or 24-
hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the
AM/PM bit with logic-high being PM. In the 24-hour
mode, bit 5 is the 20-hour bit (20–23 hours). Changing
the 12/24 bit requires that the hours data be re-entered
in the proper format.
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
12 Maxim Integrated
DS1388
Watchdog Alarm Counter
The contents of the watchdog alarm counter, which is a
separate two-byte BCD down counter, are accessed in
the address range 08h–09h in block 0h. It is programma-
ble in 10ms intervals from 0.01 to 99.99 seconds. When
this counter is written, both the counter and a seed regis-
ter are loaded with the desired value. When the counter is
to be reloaded, it uses the value in the seed register.
When the counter is read, the current counter value is
latched into a register, which is output on the serial data
line and the watchdog counter reloads the seed value.
If the counter is not needed, it can be disabled and
used as a 16-bit cache of battery-backed RAM by set-
ting the WDE bit in the control register to logic 0. If all
16 bits of the watchdog alarm counter are written to a
zero when WDE = 1, the counter is disabled and the
WF bit is not set.
When the WDE bit in the control register is set to a logic
1 and a non-zero value is written into the watchdog reg-
isters, the watchdog alarm counter decrements every
1/100 second, until it reaches zero. At this point, the WF
bit in the flag register is set. If WD/RST = 1, the RST pin
is pulsed low for tRST and access to the DS1388 is
inhibited. At the end of tRST, the RST pin becomes high
impedance, and read/write access to the DS1388 is
enabled. The WF flag remains set until cleared by writ-
ing WF to logic 0. The watchdog alarm counter can be
reloaded and restarted before the counter reaches zero
by reading or writing any of the watchdog alarm
counter registers.
The WF flag and WDE bit must be set to zero before writing
the watchdog registers. After writing the watchdog regis-
ters, WDE must be set to one to enable the watchdog.
Power-Up/Down, Reset, and
Pushbutton Reset Functions
A precision temperature-compensated reference and
comparator circuit monitors the status of VCC. When an
out-of-tolerance condition occurs, an internal power-fail
signal is generated that blocks read/write access to the
device and forces the RST pin low. When VCC returns
to an in-tolerance condition, the internal power-fail sig-
nal is held active for tRST to allow the power supply to
stabilize, and the RST pin is held low. If the EOSC bit is
set to a logic 1 (to disable the oscillator in battery-back-
up mode), the internal power-fail signal and the RST pin
are kept active for tRST plus the oscillator startup time.
Access is inhibited whenever RST is low.
The DS1388 provides for a pushbutton switch to be
connected to the RST output pin. When the DS1388 is
not in a reset cycle, it continuously monitors the RST
signal for a low-going edge. If an edge is detected, the
part debounces the switch by pulling the RST pin low
and inhibits read/write access. After the internal timer
has expired, the part continues to monitor the RST line.
If the line is still low, it continues to monitor the line look-
ing for a rising edge. Upon detecting release, the part
forces the RST pin low and holds it low for tRST.
Special-Purpose Registers
The DS1388 has three additional registers (control,
flag, and trickle charger) that control the real-time
clock, watchdog, and trickle charger.
Flag Register (00Bh)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some period of time and may be used to
judge the validity of the clock and calendar data. This
bit is edge triggered and is set to logic 1 when the
internal circuitry senses the oscillator has transitioned
from a normal run state to a STOP condition. The follow-
ing are examples of conditions that can cause the OSF
bit to be set:
1) The first time power is applied.
2) The voltage present on both VCC and VBACKUP are
insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (i.e., noise, leak-
age, etc.).
This bit remains at logic 1 until written to logic 0. This
bit can only be written to logic 0. Attempting to write
OSF to logic 1 leaves the value unchanged.
Bit 6: Watchdog Alarm Flag (WF). A logic 1 in this bit
indicates that the watchdog counter reached zero. If
WDE and WD/RST are set to 1, the RST pin pulses low
for tRST when the watchdog counter reaches zero and
sets WF = 1. At the completion of the pulse, the WF bit
remains set to logic 1. Writing this bit to logic 0 clears
the WF flag. This bit can only be written to logic 0.
Attempting to write logic 1 leaves the value unchanged.
Bits 5 to 0: These bits read as zero and cannot be
modified.
Flag Register (00Bh)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
OSFWF000000
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 13
DS1388
Control Register (00Ch)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscillator
is stopped when the DS1388 switches to battery power.
This setting can be used to conserve battery power
when timekeeping operation is not required. This bit is
cleared (logic 0) when power is first applied. When the
DS1388 is powered by VCC, the oscillator is always on
regardless of the status of the EOSC bit. The clock can
be halted whenever the timekeeping functions are not
required, which minimizes VBAT current (IBACKUPDR).
Bits 6 to 2: These bits read as zero and cannot be
modified.
Bit 1: Watchdog Enable (WDE). When set to logic
one, the watchdog counter is enabled. When set to
logic 0, the watchdog counter is disabled, and the two
registers can be used as NV RAM. This bit is cleared
(logic 0) when power is first applied.
Bit 0: Watchdog Reset (WD/RST). This bit enables the
watchdog alarm output to drive the RST pin. When the
WD/RST bit is set to logic 1, RST pulses low for tRST if
WDE = 1 and the watchdog counter reaches zero.
When the WD/RST bit is set to logic 0, the RST pin is
not driven by the watchdog alarm; only the watchdog
flag bit (WF) in the flag register is set to logic 1. This bit
is logic 0 when power is first applied.
Trickle-Charge Register (00Ah)
The simplified schematic of Figure 5 shows the basic
components of the trickle charger. The trickle-charge
select (TCS) bits (bits 4–7) control the selection of the
trickle charger. To prevent accidental enabling, only a
pattern on 1010 enables the trickle charger. All other
patterns disable it. The trickle charger is disabled when
power is first applied. The diode-select (DS) bits (bits 2
and 3) select whether or not a diode is connected
between VCC and VBACKUP. If DS is 01, no diode is
selected, yet if DS is 10, a diode is selected. The ROUT
bits (bits 0 and 1) select the value of the resistor con-
nected between VCC and VBACKUP. Table 3 shows the
resistor selected by the resistor select (ROUT) bits and
the diode selected by the diode-select (DS) bits.
Warning: The ROUT value of 250Ωmust not be select-
ed whenever VCC is greater than 3.63V.
The user determines the diode and resistor selection
according to the maximum current desired for battery
or super cap charging. The maximum charging current
can be calculated as illustrated in the following exam-
ple. Assume that a system power supply of 3.3V is
applied to VCC and a super cap is connected to
VBACKUP. Also, assume that the trickle charger has
been enabled with a diode and resistor R2 between
VCC and VBACKUP. The maximum current IMAX would
be calculated as follows:
IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2kΩ
1.3mA
As the super cap charges, the voltage drop between
VCC and VBACKUP decreases and therefore the charge
current decreases.
Control Register (00Ch)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
EOSC 00000WDEWD/RST
Table 3. Trickle-Charge Register
TCS3
TCS2 TCS1 TCS0
DS1 DS0
ROUT1 ROUT0
FUNCTION
X X X X 0 0 X X Disabled
X X X X 1 1 X X Disabled
X X X X X X 0 0 Disabled
10100101No diode, 250Ω resistor
10101001One diode, 250Ω resistor
10100110No diode, 2kΩ resistor
10101010One diode, 2kΩ resistor
10100111No diode, 4kΩ resistor
10101011One diode, 4kΩ resistor
00000000Initial default value—disabled
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
14 Maxim Integrated
DS1388
EEPROM
The DS1388 provides 512 bytes of EEPROM organized
into two blocks of 256 bytes. Each 256-byte block is
divided into 32 pages consisting of 8 bytes per page.
The EEPROM can be written one page at a time. Page
write operations are limited to writing bytes within a sin-
gle physical page, regardless of the number of bytes
actually being written. Physical page boundaries start at
addresses that are integer multiples of the page size (8
bytes) and end at addresses that are integer multiples
of [page size -1]. For example, page 0 contains word
addresses 00h to 07h. Similarly, page 1 contains word
addresses 08h to 0Fh. If a page write command
attempts to write across a physical page boundary, the
result is that the data wraps around to the beginning of
the current page (overwriting data previously stored
there), instead of being written to the next page as
might be expected. Therefore, it is necessary for the
application software to prevent page write operations
that would attempt to cross a page boundary.
I2C Serial Data Bus
The DS1388 supports a bidirectional I2C bus and data
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data is defined as a receiver. The device that con-
trols the message is called a master. The devices that
are controlled by the master are slaves. The bus must
be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions. The DS1388
operates as a slave on the I2C bus. Connections to the
bus are made through the open-drain I/O lines SDA
and SCL. Within the bus specifications, a standard
mode (100kHz maximum clock rate) and a fast mode
(400kHz maximum clock rate) are defined. The DS1388
works in both modes.
The following bus protocol has been defined (Figure 6):
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain stable
whenever the clock line is high. Changes in the data
line while the clock line is high will be interpreted as
control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the data
line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the clock
signal. The data on the line must be changed during
the low period of the clock signal. There is one clock
pulse per bit of data.
R1
250Ω
R2
2kΩ
R3
4kΩ
VCC VBACKUP
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0
TRICKLE-CHARGE REGISTER (00Ah)
1 0F 16 SELECT
NOTE: ONLY 1010b ENABLES CHARGER
1 OF 2
SELECT
1 OF 3
SELECT
TCS0-3 = TRICKLE-CHARGE SELECT
DS0-1 = DIODE SELECT
ROUT0-1 = RESISTOR SELECT
Figure 5. Programmable Trickle Charger
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 15
DS1388
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and the
STOP conditions is not limited, and is determined by
the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) after the reception of each byte. The master
device must generate an extra clock pulse, which is
associated with this acknowledge bit. The DS1388
does not generate any acknowledge bits if access to
the EEPROM is attempted during an internal pro-
gramming cycle.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by generating a not-acknowledge (NACK) bit on
the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 7 and 8 detail how data transfer is accom-
plished on the I2C bus. Depending upon the state of
the R/Wbit, two types of data transfer are possible:
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte. Data are transferred with the
most significant bit (MSB) first.
Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last
received byte, a NACK is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a repeat-
ed START condition. Since a repeated START
condition is also the beginning of the next serial
transfer, the bus is not released. Data are transferred
with the most significant bit (MSB) first.
SDA
SCL
IDLE
1–7 8 9 1–7 8 9 1–7 8 9
START
CONDITION STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/W ACK ACKDATA ACK/
NACK
DATA
MSB FIRST MSB LSB MSB LSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 6. I2C Data Transfer Overview
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
16 Maxim Integrated
DS1388
Device Addressing
The slave address byte is the first byte received follow-
ing the START condition from the master device. The
slave address byte consists of a 4-bit control code. For
the DS1388, this is set as 1101 binary for read and
write operations. The next three bits of the slave
address byte are the block select bits (B2, B1, B0). B2
is always logic 0 for the DS1388. These bits are used
by the master device to select which of the three blocks
in the memory map are to be accessed. These bits are
the three most significant bits of the word address. The
last bit of the slave address byte defines the operation
to be performed. When set to 1, a read operation is
selected; when set to 0, a write operation is selected.
Write Operation
Slave Receiver Mode (Write Mode)
Following the START condition from the master, the
device code (4 bits); the block address (3 bits); and the
R/Wbit, which is logic-low, is placed onto the bus by
the master transmitter. This indicates to the DS1388
that a byte with a word address follows after the
DS1388 has generated an acknowledge bit during the
ninth clock cycle. The next byte transmitted by the
master is the word address and will set the internal
address pointer of the DS1388, with the DS1388
acknowledging the transfer on the ninth clock cycle.
The master device can then transmit zero or more
bytes of data, with the DS1388 acknowledging the
transfer on the ninth clock cycle. The master generates
a STOP condition to terminate the data write.
Byte Write
The write-slave address byte and word address are
transmitted to the DS1388 as described in the
Slave
Receiver Mode
section. The master transmits one data
byte, with the DS1388 acknowledging the transfer on
the ninth clock cycle. The master then generates a
STOP condition to terminate the data write. This initiates
the internal write cycle, and, if the write was to the
EEPROM, the DS1388 does not generate acknowledge
signals during the internal EEPROM write cycle.
EEPROM Page Write
The write-slave address byte, word address, and the
first data byte are transmitted to the DS1388 in the
same way as in a byte write. But instead of generating
a STOP condition, the master transmits up to 8 data
bytes to the DS1388, which are temporarily stored in
the on-chip page buffer and are written into the memo-
ry after the master has transmitted a STOP condition.
Data bytes within the page that are not written remain
unchanged. The internal address pointer automatically
increments after each byte is written.
If the master should transmit more than 8 data bytes prior
to generating the STOP condition, the address pointer
rolls over and the previously received data is overwritten.
As with the byte write operation, once the STOP condi-
tion is received an internal write cycle begins.
RTC Multibyte Write
Writing multiple bytes to the RTC works much the same
way as the EEPROM page write, except that the entire
contents of block 0h can be written at once. The 8-byte
page size limitation does not apply to the block 0. If the
master should transmit more bytes than exists in block
0 prior to generating the STOP condition, the internal
address pointer rolls over and the previously received
data is overwritten. As with the byte write operation,
once the STOP condition is received an internal write
cycle begins.
Slave Address Byte
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
1 1 0 1 B2B1B0R/W
OPERATION CONTROL CODE BLOCK SELECT R/W
Read Clock 1101 000 1
Write Clock 1101 000 0
Read Lower Block of EEPROM 1101 001 1
Write Lower Block of EEPROM 1101 001 0
Read Upper Block of EEPROM 1101 010 1
Write Upper Block of EEPROM 1101 010 0
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
Maxim Integrated 17
DS1388
Acknowledge Polling
Since the DS1388 does not acknowledge during an
EEPROM write cycle, acknowledge polling can be used
to determine when the cycle is complete (this feature
can be used to maximize bus throughput). Once the
master issues the STOP condition for a write command,
the DS1388 initiates the internally timed write cycle.
ACK polling can be initiated immediately. This involves
the master sending a START condition, followed by the
slave address byte for a write command (R/W= 0) to
the EEPROM. If the device is still busy with the write
cycle, then a NACK is returned. If the cycle is com-
plete, then the device returns the ACK and the master
can then proceed with the next read or write command.
The RTC registers in block 0 are accessible during an
EEPROM write cycle.
Read Operation
Read operations are initiated in the same way as write
operations with the exception that the R/Wbit of the
slave address is set to 1. There are three basic types of
read operations: current address read, random read,
and sequential read.
Current Address Read
The DS1388 contains an address pointer that main-
tains the last address accessed, internally increment-
ed by 1. Therefore, if the previous access (either a
read or write operation) was to address n, the next cur-
rent address read operation would access data from
address n + 1. Upon receipt of the slave address with
the R/Wbit set to 1, the DS1388 issues an acknowl-
edge and transmits the 8-bit data byte. The master
issues a NACK followed by a STOP condition, and the
DS1388 discontinues transmission.
Random Read
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be
set. This is done by sending the word address to the
DS1388 as part of a write operation. After the word
address is sent, the master generates a START condi-
tion following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the slave address byte
again but with the R/Wbit set to 1. The DS1388 then
issues an acknowledge and transmits the 8-bit data
byte. The master issues a NACK followed by a STOP
condition, and the DS1388 discontinues transmission.
Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the DS1388 transmits the
first data byte, the master issues an acknowledge as
opposed to a STOP condition in a random read. This
directs the DS1388 to transmit the next sequentially
addressed 8-bit byte. To provide sequential reads, the
DS1388 contains an internal address pointer, which is
incremented by one at the completion of each opera-
tion. This allows the entire memory contents of the
block specified in the slave address to be serially read
during one operation. The master terminates the read
by generating a NACK followed by a STOP condition.
No page boundaries exist for read operations. When
the address pointer reaches the end of an EEPROM
block (FFh), the address pointer wraps to the beginning
(00h) of the same block.
The DS1388 can operate in the two modes illustrated in
Figures 7 and 8.
...
AXXXXXXXXA1101000S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
<R/W> <WORD ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
MASTER TO SLAVESLAVE TO MASTER
<SLAVE
ADDRESS>
Figure 7. Data Write—Slave Receiver Mode
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
18 Maxim Integrated
DS1388
...
AXXXXXXXXA1101BBBS 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P
B - BLOCK SELECT
S - START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
MASTER TO SLAVE SLAVE TO MASTER
<R/W> <DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
<SLAVE
ADDRESS>
Figure 8. Data Read—Slave Transmitter Mode
B - BLOCK SELECT
S - START
Sr - REPEATED START
A - ACKNOWLEDGE (ACK)
P - STOP
A - NOT ACKNOWLEDGE (NACK)
R/W - READ/WRITE OR DIRECTION BIT ADDRESS
<R/W> <WORD ADDRESS (n)> <SLAVE ADDRESS (n)>
<SLAVE
ADDRESS> <R/W>
AXXXXXXXXA1101BBB 1101BBBSSr0 A1
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK.
MASTER TO SLAVE SLAVE TO MASTER
AXXXXXXXX XXXXXXXX A XXXXXXXX A XXXXXXXX A P
<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
...
Figure 9. Data Write/Read (Write Pointer, Then Read)—Slave Receive and Transmit
Chip Information
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Package Information
For the latest package outline information and land patterns, go
to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 SO S8+4 21-0041 90-0096
I2C RTC/Supervisor with Trickle Charger
and 512 Bytes EEPROM
DS1388
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
19
© 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 4/05 Initial release.
Removed the leaded parts from the Ordering Information. 1
Indicated the pullup voltage for SDA and SCL in the Pin Description table. 8
Added the oscillator bias circuit to the Block Diagram and removed the original Figure 8, 10
Added time and date POR values in the Power Control section. 9
Changed the last sentence of the Watchdog Alarm Counter section (first paragraph) to
When the counter is read, the current counter value is latched into a register, which is
output on the serial data line and the watchdog counter reloads the seed value.”
12
Added “Access is inhibited whenever RST is low.” To the end of the Power-Up/Down,
Reset, and Pushbutton Reset Functions section (first paragraph). 12
In the Control Register (00Ch) section, bit 7 description, added a statement that EOSC is
used to reduce VBAT current when timekeeping is not required. 13
1 9/08
Replaced the I2C read and write figures. 17, 18
Corrected the RTC power-on default values in the Power Control section. 9
Corrected the date register range in Figure 4. 11
2 10/09
Added WF flag clear to the Watchdog Alarm Counter section. 12
In the Absolute Maximum Ratings section, added the thermal information, lead
information, and new Note 1, and updated the soldering information. 2–6
In the Pin Description, corrected X2 pin name and bias limit on SDA, SCL. 8
3 8/10
Added the package code and land pattern no. to the Package Information table. 18
44/13 Updated Absolute Maximum Ratings,Power Control and Clock and Calendar sections 2, 9, 11
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