LM2575T-5.0LF03/NOPB - TEXAS INSTRUMENTS

 2007-2015 Microchip Technology Inc. DS40001341F-page 1

PIC16(L)F722/3/4/6/7

Devices Included In This Data Sheet:

PIC16F722/3/4/6/7 Devices:

PIC16LF722/3/4/6/7 Devices:

High-Performance RISC CPU:

• Only 35 Instru ctions to Lear n:

- All single-cycle instructions except branches

• Ope rati ng Sp eed :

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Up to 8K x 14 Words of Flash Program Memory

• Up to 368 Bytes of Data Memory (RAM)

• Interrupt Capability

• 8-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinou t Compatibl e to other 28/40-pin PI C16CXXX

and PIC16FXXX Microcontrollers

S pecial Microcontroller Features:

• Precision Internal Oscillator:

- 16 MHz or 500 kHz operation

- Factory calibrated to ±1%, typical

- Softwa re tu nable

- Software selectable ÷1, ÷2, ÷4 or ÷8 divider

• 1.8V-5.5V Operation – PIC16F722/3/4/6/7

• 1.8V-3.6V Operation – PIC16LF722/3/4/6/7

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Brown-out Reset (BOR):

- Selectable between two trip points

- Disable in Sleep option

• Programmable Code Protection

• In-C ircuit Serial Programm ingTM (ICSPTM) via Two

Pins

• Multiplexed Master Clear with Pull-up/Input Pin

• Indus tri al and Extended Temperatu r e Range

• High-Endurance Flash Cell:

- 1,000 write Flash endurance (typical)

- F lash r etention: > 40 years

• Power-Saving Sleep mode

Extreme Low-Power M anagement

PIC16LF722/3/4/6/7 with XLP:

• Sleep Mode: 20 nA

• Watchdog Ti mer: 500 nA

• Timer1 Oscillator: 600 nA @ 32 kHz

Analog Features:

• A/D Converter:

- 8-bit resolution and up to 14 channels

- Conversion available during Sleep

- Select ab le 1.0 24/2 . 04 8/4 .096 V voltage

reference

• On-ch ip 3 .2V Regulator (PIC1 6F 72 2/3 /4 /6/ 7

devices only)

Peripheral Highl ights:

• Up to 35 I/O Pins and One Input-only Pin:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler

• Enhanced Timer1:

- Dedicated low-power 32 kHz oscillator

- 16-bit timer/counter with prescaler

- External Gate Input mode with Toggle and

Single Shot modes

- Interrupt-on-gate completion

• Timer2: 8-Bit Timer/Counter with 8-Bit Period

• Two Capture, Compare, PWM (CCP) Modules:

- 1 6-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Addressable Universal Synchronous

Asynchronous Receiver Transmitter (AUSART)

• Synchronous Serial Port (SSP):

- SPI (Master/Slave)

-I

2C (Slave) with Address Mask

•mTouch

® Sensing Oscill ator Module:

- Up to 16 input channels

• PIC16F722 • PIC16F726

• PIC16F723 • PIC16F727

•PIC16F724

• PIC16LF722 • PIC16LF726

• PIC16LF723 • PIC16LF727

• PIC16LF724

28/40/44-Pin Flash Microcontrollers with XLP Technology

PIC16(L)F722/3/4/6/7

DS40001341F-page 2  2007-2015 Mic rochip Tec hnology Inc.

PIC16(L)F72X Family Types

Device

Data Sheet Index

Program Memory

Flash (words)

Data SRAM

(bytes)

High-Endurance Flash

Memory (bytes)

I/O’s(2)

8-bit ADC (ch)

CapSense (ch)

Timers

(8/16-bit)

AUSART

SSP (I2C/SPI)

CCP

Debug(1)

XLP

PIC16(L)F707 (1) 8192 363 036 14 32 4/2 1 1 2 I Y

PIC16(L)F720 (2) 2048 128 128 18 12 —2/1 1 1 1 I Y

PIC16(L)F721 (2) 4096 256 128 18 12 —2/1 1 1 1 I Y

PIC16(L)F722 (4) 2048 128 0 25 11 8 2/1 1 1 2 I Y

PIC16(L)F722A (3) 2048 128 025 11 82/1 1 1 2 I Y

PIC16(L)F723 (4) 4096 192 0 25 11 8 2/1 1 1 2 I Y

PIC16(L)F723A (3) 4096 192 025 11 82/1 1 1 2 I Y

PIC16(L)F724 (4) 4096 192 0 36 14 16 2/1 1 1 2 I Y

PIC16(L)F726 (4) 8192 368 0 25 11 8 2/1 1 1 2 I Y

PIC16(L)F727 (4) 8192 368 0 36 14 16 2/1 1 1 2 I Y

Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.

2: One pin is input-only.

Dat a Shee t Index: (Unshaded devices are described in this document.)

1: DS41418 PIC16(L)F707 Data Sheet, 40/44-Pin Flash, 8-bit Microcontrollers

2: DS41430 PIC16(L)F720/721 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers

3: DS41417 PIC16(L)F722A/723A Data Sheet, 28-Pin Flash, 8-bit Microcontrollers

4: DS41341 PIC16(L)F72X Data Sheet, 28/40/44-Pin Flash, 8-bit Microcontrollers

 2007-2015 Microchip Technology Inc. DS40001341F-page 3

PIC16(L)F722/3/4/6/7

Pin Diagrams – 28-PIN PDIP/SOIC/SSOP/QFN/UQFN (PIC16F722/723/726/PIC16LF722/723/726)

PIC16F722/723/726/

PIC16LF722/723/726

VPP/MCLR/RE3

VCAP(3)/SS(2)/AN0/RA0

AN1/RA1

AN2/RA2

VREF/AN3/RA3

T0CKI/CPS6/RA4

VCAP(3)/SS(2)/CPS7/AN4/RA5

RB6/ICSPCLK

RB5/AN13/CPS5/T1G

RB4/AN11/CPS4

RB3/AN9/CPS3/CCP2(1)

RB2/AN8/CPS2

RB1/AN10/CPS1

RB0/AN12/CPS0/INT

VDD

VSS

14 15

VSS

CLKIN/OSC1/RA7

VCAP(3)/CLKOUT/OSC2/RA6

T1CKI/T1OSO/RC0

CCP2(1)/T1OSI/RC1

CCP1/RC2

SCL/SCK/RC3

RC5/SDO

RC4/SDI/SDA

RC7/RX/DT

RC6/TX/CK

RB7/ICSPDAT

716

T1CKI/T1OSO/RC0

RB7/ICSPDAT

RB6/ICSPCLK

RB5/AN13/CPS5/T1G

RB4/AN11/CPS4

RB3/AN9/CPS3/CCP2(1)

RB2/AN8/CPS2

RB1/AN10/CPS1

RB0/AN12/CPS0/INT

VDD

VSS

RC7/RX/DT

CK/TX/RC6

SDO/RC5

SDA/SDI/RC4

RE3/MCLR/VPP

RA0/AN0/SS(2)/VCAP(3)

RA1/AN1

AN2/RA2

VREF/AN3/RA3

T0CKI/CPS6/RA4

VCAP(3)/SS(2)/CPS7/AN4/RA5

VSS

CLKIN/OSC1/RA7

VCAP(3)/CLKOUT/OSC2/RA6

CCP2(1)/T1OSI/RC1

CCP1/RC2

SCL/SCK/RC3

PIC16F722/723/726/

PIC16LF722/723/726

Note 1:CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F722/723/726 devices only.

PDIP, SOIC, SSOP

QFN, UQFN

PIC16(L)F722/3/4/6/7

DS40001341F-page 4  2007-2015 Mic rochip Tec hnology Inc.

TABLE 1: 28-PIN PDIP/SOIC/SSOP/QFN/UQFN SUMMARY (PIC16F722/723/726/PIC16LF722/723/

726)

I/O

28-Pin

PDIP,

SOIC,

SSOP

28-Pin

QFN,

UQFN A/D Cap Sensor Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 227 AN0 — — — — SS(3) — — VCAP(4)

RA1 3 28 AN1 — — — — — — — —

RA2 4 1 AN2 — — — — — — — —

RA3 5 2 AN3/VREF ——————— —

RA4 6 3 — CPS6 T0CKI — — — — — —

RA5 7 4 AN4 CPS7 — — — SS(3) —— VCAP(4)

RA6 10 7 — — — — — — — — OSC2/CLKOUT/VCAP(4)

RA7 9 6 — — — — — — — — OSC1/CLKIN

RB0 21 18 AN12 CPS0 — — — — IOC/INT Y —

RB1 22 19 AN10 CPS1 — — — — IOC Y —

RB2 23 20 AN8 CPS2 — — — — IOC Y —

RB3 24 21 AN9 CPS3 — CCP2(2) — — IOC Y —

RB4 25 22 AN11 CPS4 — — — — IOC Y —

RB5 26 23 AN13 CPS5 T1G — — — IOC Y —

RB6 27 24 — — — — — — IOC YICSPCLK/ICDCLK

RB7 28 25 — — — — — — IOC Y ICSPDAT/ICDDAT

RC0 11 8 — — T1OSO/T1CKI — — — — — —

RC1 12 9 — — T1OSI CCP2(2) ———— —

RC2 13 10 — — — CCP1 — — — — —

RC3 14 11 — — — — — SCK/SCL — — —

RC4 15 12 — — — — SDI/SDA — — —

RC5 16 13 — — — — — SDO — — —

RC6 17 14 — — — — TX/CK — — — —

RC7 18 15 — — — — RX/DT — — — —

RE3 126 — — — — — — — Y(1) MCLR/VPP

—2017 — — — — — — — — VDD

—8,19 5,16 — — — — — — — — VSS

Note 1: Pull-up enabled only with external MCLR Configuration.

2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.

3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.

4: PIC16F724/727/PIC16LF724/727 devices only.

Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st

be connected to one of the available VCAP pins to stabilize the regulator. For more information, see

Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he

voltage regulator and therefore no external capacitor is required.

 2007-2015 Microchip Technology Inc. DS40001341F-page 5

PIC16(L)F722/3/4/6/7

Pin Diagrams – 40-PIN PDIP (PIC16F724/727/PIC16LF724/727)

PIC16F724/727/

PIC16LF724/727

VPP/MCLR/RE3

VCAP(3)/SS(2)/AN0/RA0

AN1/RA1

AN2/RA2

VREF/AN3/RA3

T0CKI/CPS6/RA4

VCAP(3)/SS(2)/CPS7/AN4/RA5

AN5/RE0

AN6/RE1

AN7/RE2

RB6/ICSPCLK

RB5/AN13/CPS5/T1G

RB4/AN11/CPS4

RB3/AN9/CPS3/CCP2(1)

RB2/AN8/CPS2

RB1/AN10/CPS1

RB0/AN12/CPS0/INT

VDD

VSS

RD2/CPS10

VDD

VSS

CLKIN/OSC1/RA7

VCAP(3)/CLKOUT/OSC2/RA6

T1CKI/T1OSO/RC0

CCP2(1)/T1OSI/RC1

CCP1/RC2

SCL/SCK/RC3

CPS8/RD0

CPS9/RD1

RC5/SDO

RC4/SDI/SDA

RD3/CPS11

RD4/CPS12

RC7/RX/DT

RC6/TX/CK

RD7/CPS15

RD6/CPS14

RD5/CPS13

RB7/ICSPDAT

Note 1:CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F724/727 devices only.

PIC16(L)F722/3/4/6/7

DS40001341F-page 6  2007-2015 Mic rochip Tec hnology Inc.

Pin Diagrams – 44-PIN TQFP (PIC16F724/727/PIC16LF724/727)

VREF/AN3/RA3

AN2/RA2

AN1/RA1

VCAP(3)/SS(2)/AN0/RA0

VPP/MCLR/RE3

ICSPDAT/RB7

ICSPCLK/RB6

T1G/CPS5/AN13/RB5

CPS4/AN11/RB4

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/CPS11

RD2/CPS10

RD1/CPS9

RD0/CPS8

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2(1)

RC0/T1OSO/T1CKI

RA6/OSC2/CLKOUT/VCAP(3)

RA7/OSC1/CLKIN

VSS

VDD

RE2/AN7

RE1/AN6

RE0/AN5

RA5/AN4/CPS7/SS(2)/VCAP(3)

RA4/CPS6/T0CKI

DT/RX/RC7

CPS12/RD4

CPS13/RD5

CPS14/RD6

VSS

VDD

INT/CPS0/AN12/RB0

CPS1/AN10/RB1

CPS2/AN8/RB2

CCP2(1)/CPS3/AN9/RB3

CPS15/RD7 5

4PIC16F724/727/

PIC16LF724/727

Note 1:CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F724/727 devices only.

 2007-2015 Microchip Technology Inc. DS40001341F-page 7

PIC16(L)F722/3/4/6/7

Pin Diagrams – 44-PIN QFN (PIC16F724/727/PIC16LF724/727)

VREF/AN3/RA3

AN2/RA2

AN1/RA1

VCAP(3)/SS(2)/AN0/RA0

VPP/MCLR/RE3

CCP2(1)/CPS3/AN9/RB3

ICSPDAT/RB7

ICSPCLK/RB6

T1G/CPS5/AN13/RB5

CPS4/AN11/RB4

NC RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/CPS11

RD2/CPS10

RD1/CPS9

RD0/CPS8

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2(1)

RC0/T1OSO/T1CKI

RA6/OSC2/CLKOUT/VCAP(3)

RA7/OSC1/CLKIN

VSS

VDD

RE2/AN7

RE1/AN6

RE0/AN5

RA5/AN4/CPS7/SS(2)/VCAP(3)

RA4/CPS6/T0CKI

DT/RX/RC7

CPS12/RD4

CPS13/RD5

CPS14/RD6

CPS15/RD7

VSS

VDD

INT/CPS0/AN12/RB0

CPS1/AN10/RB1

CPS2/AN8/RB2

PIC16F724/727/

PIC16LF724/727

Note 1:CCP2 pin location may be selected as RB3 or RC1.

2: SS pin location may be selected as RA5 or RA0.

3: PIC16F724/727 devices only.

PIC16(L)F722/3/4/6/7

DS40001341F-page 8  2007-2015 Mic rochip Tec hnology Inc.

TABLE 2: 40/44-PIN PDIP/TQFP/QFN SUMMARY (PIC16F724/727/PIC16LF724/727)

I/O 40-Pin

PDIP 44-Pin

TQFP 44-Pin

QFN A/D Cap

Sensor Timers CCP AUSART SSP Interrupt Pull-Up Basic

RA0 219 19 AN0 — — — — SS(3) — — VCAP(4)

RA1 3 20 20 AN1 — — — — — — — —

RA2 421 21 AN2 — — — — — — — —

RA3 5 22 22 AN3/VREF ——— — — —— —

RA4 623 23 —CPS6 T0CKI — — — — — —

RA5 7 24 24 AN4 CPS7 — — — SS(3) —— VCAP(4)

RA6 14 31 33 — — — — — — — — OSC2/CLKOUT/VCAP(4)

RA7133032 — — — — — — — — OSC1/CLKIN

RB0 33 8 9 AN12 CPS0 — — — — IOC/INT Y —

RB1 34 9 10 AN10 CPS1 — — — — IOC Y —

RB2 35 10 11 AN8 CPS2 — — — — IOC Y —

RB3 36 11 12 AN9 CPS3 — CCP2(2) — — IOC Y —

RB4 37 14 14 AN11 CPS4 — — — — IOC Y —

RB5381515AN13CPS5T1G— — — IOC Y —

RB6 39 16 16 — — — — — — IOC YICSPCLK/ICDCLK

RB7 40 17 17 — — — — — — IOC Y ICSPDAT/ICDDAT

RC0 15 32 34 — — T1OSO/

T1CKI — — — — — —

RC1 16 35 35 — — T1OSI CCP2(2) ———— —

RC2 17 36 36 — — — CCP1 — — — — —

RC3 18 37 37 — — — — — SCK/SCL — — —

RC4 23 42 42 — — — — SDI/SDA — — —

RC5 24 43 43 — — — — SDO — — —

RC6 25 44 44 — — — — TX/CK — — — —

RC7 26 1 1 — — — — RX/DT — — — —

RD0 19 38 38 —CPS8 — — — — — — —

RD1 20 39 39 — CPS9 — — — — — — —

RD2 21 40 40 —CPS10 — — — — — — —

RD3 22 41 41 — CPS11 — — — — — — —

RD4 27 2 2 — CPS12 — — — — — — —

RD5 28 3 3 — CPS13 — — — — — — —

RD6 29 4 4 — CPS14 — — — — — — —

RD7 30 5 5 — CPS15 — — — — — — —

RE0 825 25 AN5 — — — — — — — —

RE1 9 26 26 AN6 — — — — — — — —

RE2 10 27 27 AN7 — — — — — — — —

RE3 1 18 18 — — — — — — — Y(1) MCLR/VPP

—11,32 7,28 7,8,28 — — — — — — — — VDD

— 12,13 6,29 6,30,31 — — — — — — — — VSS

Note 1: Pull-up enabled only with external MCLR configur ati o n.

2: RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.

3: RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.

4: PIC16F 72 2/3 /4/6 / 7 devices onl y.

Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st

be connected to one of the available VCAP pins to stabilize the regulator. For more information, see

Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he

voltage regulator and therefore no external capacitor is required.

 2007-2015 Microchip Technology Inc. DS40001341F-page 9

PIC16(L)F722/3/4/6/7

Table of Contents

Device Overview ................................................................................................................................................................................. 11

Memory Organization ...................................................................................... .................................................................................... 17

Resets ................................................................................................................................................................................................. 30

Interrupts ............................................................................................................................................................................................. 40

Low Dropout (LDO) Voltage Regulator ................................................................................ ............................................................... 49

I/O Ports ............ ........ ................. ......... ................ ......... ................. ........ ................. ............................................................................. 50

Oscillator Module ................................................................................................................................................................................ 85

Device Configuration ........................................................................................................................................................................... 91

Analog-to-Digital Converter (ADC) Module .................................................... ..................................................................................... 94

Fixed Voltage Reference ......... .. .... ....... .. .. .... .. .... ....... .. .. .... .. .. ....... .... .. .. .... .. ....... .... .. .. .... .. .. .... ........................................................... 104

Timer0 Module ................................. ................................................................................................................................................. 105

Timer1 Module with Gate Control ..................................................................................................................................................... 108

Timer2 Module ................................. ................................................................................................................................................. 120

Capacitive Sensing Module .................... .. .... .. .... ....... .... .. .... .. ......... .. .... .. .... .. ......... .. .... .. .... ............................................................... 122

Capture/Compare/PWM (CCP) Module ............................................................................. ............................................................... 128

Addressable Universal Synchronous Async h ronous Receiv er Transmitter (AUS ART ) .................................................................... 138

SSP Module Overview ...................................................................................................................................................................... 159

Program Memo ry Read . ................... .......................................... ..................... .................................................................................. 181

Power-Down Mode (Sleep) ............................................................................................................................................................... 184

In-Circuit Serial Programming™ (ICSP™) ........................................................................................................................................ 186

Instruction Set Summary ................................................................................................................................................................... 187

Development Support ...................... .................................................................................... ............................................................. 196

Electrical Specifications .................................................................................................................................................................... 200

DC and AC Characteristics Graphs and Charts ................................................................................................................................ 228

Packagi n g Information . ........ ................. ................. ................ ................. ................. ........ ................................................................. 263

Appendix A: Data Sheet Revision History .................................................................. .... ........... ........................................................ 277

Appendix B: Migrating From Other PIC® Devices .............................................................................. ... ........................................... 277

The Micro chip Website .................. ................. ................. ................. ................. ................ ............................................................... 278

Customer Change Notification Service ............. ................. ................. ...... ................. ........ ............ ................................................... 278

Customer Support ............................................................................................................................................................................. 278

Product Identification System ........................................................................................................................................................... 279

PIC16(L)F722/3/4/6/7

DS40001341F-page 10  2007-2015 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

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You can determ ine the version of a data s heet by examining its literature number found on the botto m outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Customer No tific atio n Syst em

 2007-2015 Microchip Technology Inc. DS40001341F-page 11

PIC16(L)F722/3/4/6/7

1.0 DEVICE OVERVIEW

The PIC16(L)F722/3/4/6/7 devices are covered by this

data sheet. They are available in 28/40/44-pin pack-

ages. Figure 1-1 shows a block diagram of the

PIC16F722/723/726/PIC16LF722/723/726 devices

and Figure 1-2 shows a block diagram of the

PIC16F724/727/PIC16LF724/727 devices. Table 1-1

shows the pinout descriptions.

PIC16(L)F722/3/4/6/7

DS40001341F-page 12  2007-2015 Microchip Technology Inc.

FIGURE 1-1: PIC16F722/723/726/PIC16LF722/723/726 BLOCK DIAGRAM

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start- up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD

PORTA

RA4

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

Brown-out

Reset

AUSART

Timer0 Timer1 Timer2

RA3

RA1

RA0

Analog-To-Dig ital Conve rte r

RA6

RA7

RB6

RB7

VSS

T0CKI T1G T1CKI

VREF Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

TX/CK RX/DT

Internal

Oscillator

Block

Configuration 13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start- up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

MCLR VDD

RC1

Brown-out

Reset

AUSART

Timer0 Timer1 Timer2

VSS

T0CKI T1CKI

Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

Internal

Oscillator

Block

Configuration 13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

W Reg

Power-up

Timer

Oscillator

Start- up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode and

Control

Timing

Generation

MCLR VDD

PORTB

PORTC

RA5

Brown-out

Reset

Timer0 Timer1 Timer2

RA2

RB0

RB1

RB2

RB3

RB4

RB5

VSS

T0CKI T1CKI

Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

Internal

Oscillator

Block

Configuration

CCP2

Timer1

32 kHz

Oscillator

PORTE RE3

CCP1

T1OSI

T1OSO

AN9

AN0 AN1 AN2 AN3 AN4 AN8 AN10 AN11 AN12 AN13

LDO(1)

Regulator

Flash

Program

Memory

Note 1: PIC16F722/723/726 only.

RAM

Capacitive Sensi n g Modul e

CPS6

CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS7

 2007-2015 Microchip Technology Inc. DS40001341F-page 13

PIC16(L)F722/3/4/6/7

FIGURE 1-2: PIC16F724/727/PIC16LF724/727 BLOCK DIAGRAM

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

PORTA

PORTB

PORTC

PORTD

PORTE

RA4

RA5

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

RE0

RE1

RE2

AUSART

Timer0 Timer1 Timer2

RA3

RA1

RA0

RA6

RA7

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RB0

RB1

RB2

RB3

RB4

RB5

RB7

AN6

AN0 AN1 AN2 AN3 AN4 AN5 AN7

Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

TX/CK RX/DT

Internal

Oscillator

Block

Configuration 13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W Reg

Instruction

Decode &

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

AUSART

Timer0 Timer1 Timer2

Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

Internal

Oscillator

Block

Configuration 13 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

PORTB

PORTC

PORTD

PORTE

RC1

AUSART

Timer0 Timer1 Timer2

Analog-To-Digital Converter

RB6

Synchronous

SDA SCL SSSDO

Serial Port

SDI/ SCK/

Internal

Oscillator

Block

Configuration

RE3

CCP2

CCP1

VREF

RA2

AN9AN8 AN10 AN11 AN12 AN13

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VDD

Brown-out

Reset

VSS

T0CKI T1G T1CKI

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VDD

Brown-out

Reset

VSS

T0CKI T1CKI

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

MCLR VDD

Brown-out

Reset

VSS

T0CKI T1CKI

Timer1

32 kHz

Oscillator

T1OSI

T1OSO

LDO(1)

Regulator

Note 1: PIC16F724/727 only.

Capacitive Sensing Module

CPS6CPS0 CPS1 CPS2 CPS3 CPS4 CPS7 CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15CPS5

Flash

Program

Memory RAM

PIC16(L)F722/3/4/6/7

DS40001341F-page 14  2007-2015 Microchip Technology Inc.

TABLE 1-1: PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/SS/VCAP RA0 TTL CMO S General purpose I/O.

AN0 AN — A /D Channel 0 input.

SS ST — S lave Select input.

VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).

RA1/AN1 RA1 TTL CMOS General purpose I/O.

AN1 AN — A /D Channel 1 input.

RA2/AN2 RA2 TTL CMOS General purpose I/O.

AN2 AN — A /D Channel 2 input.

RA3/AN3/VREF RA3 TTL CMOS Gener al purpose I/O.

AN3 AN — A /D Channel 3 input.

VREF AN — A/D Voltage Reference input.

RA4/CPS6/T0CKI RA4 TTL CMO S Gener al purpose I/O.

CPS6 AN — Capacitive sensing input 6.

T0CKI ST — Timer0 clock input.

RA5/AN4/CPS7/SS/VCAP RA5 T TL CMOS General purpose I/O.

AN4 AN — A /D Channel 4 input.

CPS7 AN — Capacitive sensing input 7.

SS ST — Slave Select input.

VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).

RA6/OSC2/CLKOUT/VCAP RA6 TTL CMO S Gener al purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

VCAP Power Power Filter capacitor for V oltage Regulator (PIC16F72X only).

RA7/OSC1/CLKIN RA7 TTL CMO S Gener al purpose I/O.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN CMOS — External clock input (EC mode).

CLKIN ST — RC oscillator connection (RC mode).

RB0/AN12/CPS0/INT RB0 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN12 AN — A/D Channel 12 input.

CPS0 AN — Capacitive sensing input 0.

INT ST — External interrupt.

RB1/AN10/CPS1 RB1 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN10 AN — A/D Channel 10 input.

CPS1 AN — Capacitive sensing input 1.

RB2/AN8/CPS2 RB2 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN8 AN — A /D Channel 8 input.

CPS2 AN — Capacitive sensing input 2.

RB3/AN9/CPS3/CCP2 RB3 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN9 AN — A /D Channel 9 input.

CPS3 AN — Capacitive sensing input 3.

CCP2 ST CMOS Capture/Compare/PWM2.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTA L = Crystal levels

 2007-2015 Microchip Technology Inc. DS40001341F-page 15

PIC16(L)F722/3/4/6/7

RB4/AN11/CPS4 RB4 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN11 AN — A/D Channel 11 input.

CPS4 AN — Capacitive sensing input 4.

RB5/AN13/CPS5/T1G RB5 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

AN13 AN — A/D Channel 13 input.

CPS5 AN — Capacitive sensing input 5.

T1G ST — Timer1 Gate input.

RB6/ICSPCLK/ICDCLK RB6 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

ICSPCLK S T — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

RB7/ICSPDAT/ICDDAT RB7 TTL CMOS General purpose I/O. Individually controlled inter-

rupt-on-change. Individually enabled pull-up.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST — In-Circuit Data I/O.

RC0/T1OSO/T1CKI RC0 ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator co nnection.

T1CKI ST — Timer1 clock input.

RC1/T1OSI/CCP2 RC1 ST CMOS General purpose I/O.

T1OSI X TAL XTAL Timer1 oscillator co nnection.

CCP2 ST CMOS Capture/Compare/PWM2.

RC2/CCP1 RC2 ST CMOS General purpose I/O.

CCP1 ST CMOS Capture/Compare/PWM1.

RC3/SCK/SCL RC3 ST CMOS General purpose I/O.

SCK ST CM O S SPI clock.

SCL I2CODI

2C clock.

RC4/SDI/SDA RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA I2CODI

2C data input/output.

RC5/SDO RC5 ST CMOS General purpose I/O .

SDO — CMOS SPI data output.

RC6/TX/CK RC6 ST CMOS General purpose I/O .

TX — CMOS USART async hronous tr ansmit.

CK ST CMOS USART synchronous clock.

RC7/RX/DT RC7 ST CMOS Gener al purpose I/O.

RX ST — USART async hronous input.

DT ST CMO S U SART synch ronous data.

RD0/CPS8 RD0 ST CMOS Gener al purpose I/O.

CPS8 AN — Capacitive sensing input 8.

RD1/CPS9 RD1 ST CMOS Gener al purpose I/O.

CPS9 AN — Capacitive sensing input 9.

RD2/CPS10 RD2 ST CMOS Gener al purpose I/O.

CPS10 AN — Capacitive sensing input 10.

TABLE 1-1: PIC16(L)F722/3/4/6/7 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTA L = Crys tal levels

PIC16(L)F722/3/4/6/7

DS40001341F-page 16  2007-2015 Microchip Technology Inc.

RD3/CPS11 RD3 ST CMOS Gener al purpose I/O.

CPS11 AN — Capacitive sensing input 11.

RD4/CPS12 RD4 ST CMOS General purpose I/O.

CPS12 AN — Capacitive sensing input 12.

RD5/CPS13 RD5 ST CMOS General purpose I/O.

CPS13 AN — Capacitive sensing input 13.

RD6/CPS14 RD6 ST CMOS General purpose I/O.

CPS14 AN — Capacitive sensing input 14.

RD7/CPS15 RD7 ST CMOS General purpose I/O.

CPS15 AN — Capacitive sensing input 15.

RE0/AN5 RE0 ST CMOS General purpose I/O.

AN5 AN — A /D Channel 5 input.

RE1/AN6 RE1 ST CMOS General purpose I/O.

AN6 AN — A /D Channel 6 input.

RE2/AN7 RE2 ST CMOS General purpose I/O.

AN7 AN — A /D Channel 7 input.

RE3/MCLR/VPP RE3 TTL — General purpose input.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Program ming voltage.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

Note: The PIC 16F722/3 /4/6/7 devi ces have an internal low dropou t volta ge regulato r . An exte rnal cap acitor mu st

be connected to one of the available VCAP pins to stabilize the regulator. For more information, see

Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16L F722/3 /4/6/7 dev ices d o not h ave t he

voltage regulator and therefore no external capacitor is required.

TA BL E 1-1: PI C16( L) F722/ 3/4/6/7 PINOUT DESCRIPTION (C ONTI NUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C

HV = High Voltage XTA L = Crystal levels

 2007-2015 Microchip Technology Inc. DS40001341F-page 17

PIC16(L)F722/3/4/6/7

2.0 MEMORY ORGANIZATION

2.1 Program Memory Organization

The PIC16(L)F722/3/4/6/7 has a 13-bit program

counter capable of addressing a 2K x 14 program

memory space for the PIC16F722/LF722

(0000h-07FFh), a 4K x 14 program memory space for

the PIC16F723/LF723 and PIC16F724/LF724

(0000h-0FFFh) and an 8K x 14 program memory space

for the PIC16F726/LF726 and PIC16F727/LF727

(0000h-1FFFh). Accessing a location above the

memory boundaries for the PIC16F722/LF722 will

cause a wrap-around within the first 2K x 14 program

memory space. Accessing a location above the

memory boundaries for the PIC16F723/LF723 and

PIC16F 724 / LF 724 w i ll cause a wra p- aro und w ith in t he

first 4K x 14 program memory space. The Reset vector

is at 0000h and the interrupt vector is at 000 4h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F722/LF722

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F723/LF723 AND

PIC16F724/LF724

PC<12:0>

0000h

0004h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

0005h

On-chip

Program

Memory Page 0 07FFh

Wraps to Page 0

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

PC<12:0>

0000h

0004h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

0005h

On-chip

Program

Memory

Page 0

Page 1

07FFh

0800h

0FFFh

Wraps to Page 0

Wraps to Page 1

1000h

17FFh

1800h

1FFFh

PIC16(L)F722/3/4/6/7

DS40001341F-page 18  2007-2015 Microchip Technology Inc.

FIGURE 2-3: PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F726/LF726 AND

PIC16F727/LF727

2.2 Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

RP1 RP0

00Bank 0 is selected

01Bank 1 is selected

10Bank 2 is selected

11Bank 3 is selected

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers are the General Purpose Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

2.2.1 GENERAL PUR POSE REGISTER

FILE

The register file is organized as 128 x 8 bits in the

PIC16F722/LF722, 192 x 8 bits in the PIC16F723/LF723

and PIC16F724/LF724, and 368 x 8 bits in the

PIC16F726/LF726 and PIC16F727/LF727. Each

the File Select Register (FSR), (Refer to Section 2.5

“Indirect Addressing, INDF a nd FSR Reg isters ” ).

2.2.2 SPECIAL FUNCTION REGISTERS

The Sp eci al Fu nct ion Reg ist ers a re re gi ster s use d b y

the CPU and peripheral functions for controlling the

desired operation of the device (refer to Table 2-1).

These reg ister s ar e static R AM.

The Special Function Registers can be classified into

two sets: core and peripheral. The Special Function

Registers associated with the “core” are described in

this section. Those related to the operation of the

peripheral features are described in the section of that

peripheral feature.

PC<12:0>

0000h

0004h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

CALL, RETURN

RETFIE, RETLW

Stack Level 2

0005h

On-chip

1FFFh

Program

Memory

Page 0

Page 1

07FFh

0800h

0FFFh

1000h

Page 2

Page 3

17FFh

1800h

 2007-2015 Microchip Technology Inc. DS40001341F-page 19

PIC16(L)F722/3/4/6/7

FIGURE 2-4: PIC16F722/LF72 2 SPECIAL FUNCTION REGISTERS

File Address

Indirect addr.(*) 00h Ind irect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h

TMR0 01h OPTION 81h TMR0 101h OPTION 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h 105h ANSELA 185h

PORTB 06h TRISB 86h 106h ANSELB 186h

PORTC 07h TRISC 87h 107h 187h

08h 88h CPSCON0 108h 188h

PORTE 09h TRISE 89h CPSCON1 109h 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch

PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh

TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh

TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh

T1CON 10h OSCCON 90h 110h 190h

TMR2 11h OSCTUNE 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah 9Ah 11Ah 19Ah

CCPR2L 1Bh 9Bh 11Bh 19Bh

CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch

CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh

ADRES 1Eh 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

96 Bytes

20h

General

Purpose

32 Bytes

A0h

BFh

120h 1A0h

C0h

EFh 16Fh 1EFh

Accesses

70h-7Fh

F0h

Accesses

70h-7Fh

170h

Accesses

70h-7Fh

1F0h

7Fh FFh 17Fh 1FFh

Bank 0 Bank 1 Bank 2 Bank 3

Legend: = Unimplemented data memory locations, read as ‘0’.

* = Not a physical register .

PIC16(L)F722/3/4/6/7

DS40001341F-page 20  2007-2015 Microchip Technology Inc.

FIGURE 2-5: PIC16F723/LF723 AND PIC16F724/LF724 SPECIAL FUNCTION REGISTERS

Legend: = U nimplemented data memory locations, read as ‘0’.

* = Not a physical register.

Note 1: PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F723/LF723, read as ‘0’

File Address

Indirect addr.(*) 00h Ind irect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.(*) 180h

TMR0 01h OPTION 81h TMR0 101h OPTION 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h 105h ANSELA 185h

PORTB 06h TRISB 86h 106h ANSELB 186h

PORTC 07h TRISC 87h 107h 187h

PORTD(1) 08h TRISD(1) 88h CPSCON0 108h ANSELD(1) 188h

PORTE 09h TRISE 89h CPSCON1 109h ANSELE(1) 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch

PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh

TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh

TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh

T1CON 10h OSCCON 90h 110h 190h

TMR2 11h OSCTUNE 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah 9Ah 11Ah 19Ah

CCPR2L 1Bh 9Bh 11Bh 19Bh

CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch

CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh

ADRES 1Eh 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

96 Bytes

20h

7Fh

General

Purpose

80 Bytes

A0h

EFh

General Purpose

16 Bytes

120h

12Fh

130h

16Fh

1A0h

1EFh

Accesses

70h-7Fh F0h

FFh

Accesses

70h-7Fh 170h

17Fh

Accesses

70h-7Fh 1F0h

1FFh

Bank 0 Bank 1 Bank 2 Bank 3

 2007-2015 Microchip Technology Inc. DS40001341F-page 21

PIC16(L)F722/3/4/6/7

FIGURE 2-6: PIC16F726/LF726 AND PIC16F727/LF727 SPECIAL FUNCTION REGISTERS

Legend: = Unimplemented data memory locations, read as ‘0’,

* = Not a phys ical re g i s ter

Note 1: PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F726/LF726, read as ‘0’

File Address

Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr. (*) 180h

TMR0 01h OPTION 81h TMR0 101h OPTION 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h

PORTA 05h TRISA 85h 105h ANSELA 185h

PORTB 06h TRISB 86h 106h ANSELB 186h

PORTC 07h TRISC 87h 107h 187h

PORTD(1) 08h TRISD(1) 88h CPSCON0 108h ANSELD(1) 188h

PORTE 09h TRISE 89h CPSCON1 109h ANSELE(1) 189h

PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah

INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

PIR1 0Ch PIE1 8Ch PMDATL 10Ch PMCON1 18Ch

PIR2 0Dh PIE2 8Dh PMADRL 10Dh Reserved 18Dh

TMR1L 0Eh PCON 8Eh PMDATH 10Eh Reserved 18Eh

TMR1H 0Fh T1GCON 8Fh PMADRH 10Fh Reserved 18Fh

T1CON 10h OSCCON 90h

General

Purpose

16 Bytes

110h

General

Purpose

16 Bytes

190h

TMR2 11h OSCTUNE 91h 111h 191h

T2CON 12h PR2 92h 112h 192h

SSPBUF 13h SSPADD/SSPMSK 93h 113h 193h

SSPCON 14h SSPSTAT 94h 114h 194h

CCPR1L 15h WPUB 95h 115h 195h

CCPR1H 16h IOCB 96h 116h 196h

CCP1CON 17h 97h 117h 197h

RCSTA 18h TXSTA 98h 118h 198h

TXREG 19h SPBRG 99h 119h 199h

RCREG 1Ah 9Ah 11Ah 19Ah

CCPR2L 1Bh 9Bh 11Bh 19Bh

CCPR2H 1Ch APFCON 9Ch 11Ch 19Ch

CCP2CON 1Dh FVRCON 9Dh 11Dh 19Dh

ADRES 1Eh 9Eh 11Eh 19Eh

ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh

General

Purpose

96 Bytes

20h

7Fh

General

Purpose

80 Bytes

A0h

EFh

General

Purpose

80 Bytes

120h

16Fh

General

Purpose

80 Bytes

1A0h

1EFh

Accesses

70h-7Fh F0h

FFh

Accesses

70h-7Fh 170h

17Fh

Accesses

70h-7Fh 1F0h

1FFh

Bank 0 Bank 1 Bank 2 Bank 3

PIC16(L)F722/3/4/6/7

DS40001341F-page 22  2007-2015 Microchip Technology Inc.

TABLE 2-1: PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Page

Bank 0

00h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 29,37

01h TMR0 Timer0 Module Register xxxx xxxx 105,37

02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 28,37

03h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 25,37

04h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 29,37

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 51,37

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 60,37

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 70,37

08h(3) PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 77,37

09h PORTE — — — —RE3RE2

(3) RE1(3) RE0(3) ---- xxxx 81,37

0Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28,37

0Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 44,37

0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 47,37

0Dh PIR2 — — — — — — —CCP2IF---- ---0 48,37

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 113,37

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 113,37

10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON0000 00-0 117,37

11h T M R2 Timer2 Modul e Register 0000 0000 120,37

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 121,37

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Regis ter xxxx xxxx 161,37

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 178,37

15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 130,37

16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 130,37

17h CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 129,37

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 148,37

19h TXREG USART Transmit Data Register 0000 0000 147,37

1Ah RCREG USART Receive Data Register 0000 0000 145,37

1Bh CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 130,37

1Ch CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 130,37

1Dh CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 129,37

1Eh ADRES A/D Resu lt Register xxxx xxxx 100,37

1Fh ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 99,37

Legend: x = un known , u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.

3: These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.

4: Accessible only when SSPM<3:0> = 1001.

5: Accessible only when SSPM<3:0>  1001.

6: This bit is always ‘1’ as RE3 is input-only.

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PIC16(L)F722/3/4/6/7

Bank 1

80h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 29,37

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 26,37

82h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 28,37

83h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 25,37

84h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 29,37

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 51,37

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 60,37

87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 70,37

88h(3) TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 78,37

89h TRISE — — — — TRISE3(6) TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111 81,37

8Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28,37

8Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 44,37

8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 45,37

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 46,37

8Eh PCON — — — — — —PORBOR ---- --qq 27,38

8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 118,38

90h OSCCON —— IRCF1 IRCF0 ICSL ICSS — — --10 qq-- 87,38

91h OSCTUNE —— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 88,38

92h PR2 Timer2 Period Registe r 1111 1111 120,38

93h SSPADD(5) S yn chr ono us Se rial Port (I2C mode) Address Register 0000 0000 169,38

93h SSPMSK(4) Synchronous Se rial Port (I2C mode) Address Mask Register 1111 1111 180,38

94h SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 179,38

95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 61,38

96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 61,38

97h —Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 147,38

99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 149,38

9Ah —Unimplemented — —

9Bh —Unimplemented — —

9Ch APFCON — — — — — — SSSEL CCP2SEL ---- --00 50,38

9Dh FVRCON FVRRDY FVREN ———— ADFVR1 ADFVR0 q0-- --00 104,38

9Eh —Unimplemented — —

9Fh ADCON1 — ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 0000 --00 100,38

TABLE 2-1: PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Page

Legend: x = un known , u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.

3: These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.

4: Accessible only when SSPM<3:0> = 1001.

5: Accessible only when SSPM<3:0>  1001.

6: This bit is always ‘1’ as RE3 is input-only.

PIC16(L)F722/3/4/6/7

DS40001341F-page 24  2007-2015 Microchip Technology Inc.

Bank 2

100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 29,37

101h TMR0 Timer0 Module Register xxxx xxxx 105,37

102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 28,37

103h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 25,37

104h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 29,37

105h —Unimplemented — —

106h —Unimplemented — —

107h —Unimplemented — —

108h CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 126,38

109h CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 127,38

10Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28,37

10Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 44,37

10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx 181,38

10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx 181,38

10Eh PMDATH —— Program Memory Read Data Register High Byte --xx xxxx 181,38

10Fh PMADRH — — — Program Memory Read Address Register High Byte ---x xxxx 181,38

Bank 3

180h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 29,37

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 26,37

182h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 28,37

183h(2) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 25,37

184h(2) FSR Indirect Data Memory Address Pointer xxxx xxxx 29,37

185h ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 52,38

186h ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 61,38

187h —Unimplemented — —

188h ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 78,38

189h(3) ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 82,38

18Ah(1, 2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 28,37

18Bh(2) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 44,37

18Ch PMCON1 Reserved ——————RD1--- ---0 182,38

18Dh —Unimplemented — —

18Eh —Unimplemented — —

18Fh —Unimplemented — —

TABLE 2-1: PIC16(L)F722/3/4/6/7 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR Page

Legend: x = un known , u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are

transferred to the upper byte of the program counter.

2: These registers can be addressed from any bank.

3: These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.

4: Accessible only when SSPM<3:0> = 1001.

5: Accessible only when SSPM<3:0>  1001.

6: This bit is always ‘1’ as RE3 is input-only.

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PIC16(L)F722/3/4/6/7

2.2.2.1 STATUS Register

The S TATUS register, shown i n Register 2-1, co nt a ins :

• the arit hmetic status of the A LU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. Th ese bit s are set or cleared ac cording to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 21.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Se lect bit (used for in dire ct addressing)

1 = Bank 2, 3 (100h-1FFh)

0 = Bank 0, 1 (00h-FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h-7Fh)

01 = Bank 1 (80h-FFh)

10 = Bank 2 (100h-17Fh)

11 = Bank 3 (180h-1FFh)

bit 4 TO: Ti me-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time out occurred

bit 3 PD: Power-down bit

1 = After po wer-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry out from the Most Significant bit of the result occurred

0 = No carry out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rot ate (RRF, RLF) instructi ons, this bit is loa ded with either the high-orde r or low-o rder

bit of the source register.

PIC16(L)F722/3/4/6/7

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2.2.2.2 OPTION register

The OPTION register, shown in Register 2-2, is a

readable and writable register, which contains various

control bits to configure:

• Timer0/WDT prescaler

• Extern al R B0/INT interrup t

•Timer0

• Weak pu ll-ups on PORTB

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT

by setting the PSA bit of the

OPTION_REG register to ‘1’. Refer to

Section 11.1.3 “Software

Programmable Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual bits in the WPUB register

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transit ion on RA4/ T0CKI pin

0 = Internal instr uction cycle clock (FOSC/4)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/ T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assig nm ent bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

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PIC16(L)F722/3/4/6/7

2.2.2.3 PCON Regi st er

The Power Control (PCON) register contains flag bits

(refer to Table 3-2) to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON reg ister also co ntrols the software en able of

the BOR.

The PCON register bits are shown in Register 2-3.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-q R/W-q

— — — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-2 Unimplemented: Read as ‘0’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Re set occurred (mus t be set in softw are a f ter a Pow er- on R eset or Brown-out Re se t

occurs)

Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.

PIC16(L)F722/3/4/6/7

DS40001341F-page 28  2007-2015 Microchip Technology Inc.

2.3 PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register , which is a readable

and writable r egister. The high byte (PC<12:8>) is not

directly readable or writable and comes from

PCLA TH. On any Reset, the PC is cleared. Figure 2-7

shows the two situations for the loading of the PC. The

upper example in Figure 2-7 shows how the PC is

loaded on a write to PCL (PCLATH<4:0>  PCH).

The lower example in Figure 2-7 shows how the PC is

loaded during a CALL or GOTO instruction

(PCLATH<4:3>  PCH).

FIGURE 2-7: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by adding a n offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, Implementing a Table Read

(DS00556).

2.3.2 STACK

All devices have an 8-level x 13-bit wide hardware

stac k (refer to Figures 2-1 and 2-3). The sta ck sp ac e is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stac k whe n a CALL instruction is executed or

an interrupt causes a branch. The stack is POPed in

the even t of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

The st ack operates as a circular buffe r. This means that

after the st ack h as be en PU SHed ei ght ti mes, th e nin th

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

2.4 Program Memory Paging

All devices are capable of addressing a continuous 8K

word block of program memory. The CALL and GOTO

instructions provide only 11 bits of address to allow

branchi ng with in any 2K prog ram memory pag e. When

doing a CALL or GOTO instruction, the upper tw o bits of

the address are provided by PCLATH<4:3>. When

doing a CALL or GOTO instruction, the user must ensure

that the page select bits are programmed so that the

desired program memo ry page is addressed. If a retu rn

from a CALL instruction (or interrupt) is executed, the

entire 13-bit PC is POPed off the stack. Therefore,

manipulation of the PCLATH<4:3> bits is not required

for the RETURN ins truct ions (wh ich POPs the ad dress

from the stack).

Example 2-1 shows the calling of a subroutine in

page 1 of t he program mem ory . Thi s example as sumes

that PCLATH is saved and restored by the Interrupt

Service Routi ne (if interrupts are used).

EXAMPLE 2-1: CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE<10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no S tatus bit s to in dic ate Stack

Overflow or Stack Underflow condi tion s .

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interr upt add res s.

Note: The contents of the PCLATH register are

unchanged after a RETURN or RETFIE

instruction is executed. The user must

rewrite the contents of the PCLATH

calls or GOTO instructions.

ORG 500h

PAGESEL SUB_P1 ;Select page 1

;(800h-FFFh)

CALL SUB1_P1 ;Call subroutine in

: ;page 1 (800h-FFFh)

ORG 900h ;page 1 (800h-FFFh)

SUB1_P1 : ;called subroutine

;page 1 (800h-FFFh)

RETURN ;return to

;Call subroutine

;in page 0

;(000h-7FFh)

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2.5 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physica l register. Addres sing

the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the File Select

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit of

the STATUS register, as shown in Figure 2-8.

A simple program to clear RAM location 020h-02Fh

using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: INDIRECT ADDRESS ING

FIGURE 2-8: DIRECT/INDIRECT ADDRESS ING

MOVLW 020h ;initialize pointer

MOVWF FSR ;to RAM

BANKISEL 020h

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

CONTINUE ;yes continue

Note: For memory map detail, refer to Figures 2-4 and 2-5.

Data

Memory

Indirect AddressingDirect Addressing

Bank Select Locat ion Select

RP1 RP0 6 0

From Opcode IRP File Select Register

Bank Select Location Select

00 01 10 11 180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

PIC16(L)F722/3/4/6/7

DS40001341F-page 30  2007-2015 Microchip Technology Inc.

3.0 RESETS

The PIC16(L)F722/3/4/6/7 differentiates between vari-

ous kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

d) MCLR Reset during normal operation

e) MCLR Reset duri ng Sl eep

f) Brown-out Reset (BOR)

Some regi sters a re not af fected in a ny Rese t conditio n;

their st a tus is un kn ow n o n POR a nd un ch ang ed in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset (POR)

•MCLR

Reset

•MCLR

Reset during Sleep

•WDT Reset

• Brown-out Reset (BOR)

Most registers are not affected by a WDT wake-up

since this is viewed as the resumption of normal

operation. TO a nd PD bits are s et or cleared differently

in different Reset situations, as indicated in Table 3-3.

These bi ts are used in software to determine the n ature

of the Reset.

A simplif ied block diagra m of the On-Chip Rese t Circuit

is shown i n Figure 3-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 23.0 “Electrical

Specifications” for pulse-width specifications.

FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

MCLR/VPP

VDD

OSC1/

WDT

Module

POR

OST/PWRT

WDTOSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out(1)

Reset BOREN

CLKIN

Note 1: Refer to the Configuration Word Register 1 (Register 8-1).

MCLRE

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TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 3-2: RESET CONDITION FOR SPECIAL REGISTERS(2)

POR BOR TO PD Condition

0x11Power-on Reset or LDO Reset

0x0xIllegal, TO is set on POR

0xx0Illegal, PD is set on POR

1011Brown-out Reset

1101WDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during Sleep or interrupt wake-up from Sleep

Condition Program

Counter STATUS

Power-on Reset 0000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 0000h 000u uuuu ---- --uu

MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu

WDT Reset 0000h 0000 1uuu ---- --uu

WDT Wake- up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 0000h 0001 1uuu ---- --u0

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note1: When the wak e-up is du e t o an interrupt and Glob al Enable bit (GI E) is s et, t he retu rn address is pu sh ed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

PIC16(L)F722/3/4/6/7

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3.1 MCLR

The PIC16(L)F722/3/4/6/7 has a noise filter in the

MCLR Reset path. The filter will detect and ignore

small pul ses.

It should be noted that a Reset does not drive the

MCLR pin low.

Voltages appli ed to the p in that ex ceed i t s spe cificatio n

can resu lt in both MCLR Rese t s a nd e xc es sive c urrent

bey ond t h e de v ic e sp e ci fic at i on du ri ng th e ESD ev e nt .

For this rea son, Microc hip recomme nds that the MC LR

pin no long er be tied direc tl y to VDD. The use of an RC

netw ork, as show n in Figure 3-2, is suggested.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the RE3/MCLR pin

becomes an external Reset input. In this mode, the

RE3/MCLR pin has a weak pull-up to VDD. In-Circuit

Serial Programming is not affected by selecting the

internal MCLR option.

FIGURE 3-2: RECOMMENDE D MCLR

CIRCUIT

3.2 Power-on Reset (POR)

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high enough level fo r proper operation. A

maximum rise time for VDD is required. See

Section 23.0 “Electrical Spe cification s” for det ails. If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will keep the device in

Reset until VDD reaches VBOR (see Section 3.5

“Brown-Out Reset (BOR)”).

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, P ower-up Trouble Shooting (DS00607).

3.3 Power-up Timer (PWRT)

The P owe r-u p Timer pr ov ides a fi xed 64 ms (nom inal )

time out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the WDT

oscillator. For more information, see Section 7.3

“Internal Clock Modes”. The chip is kept in Reset as

long as PWRT is active. The PWRT delay allows the

VDD to rise to an acceptable level. A Configuration bit,

PWRTE, can dis able (if set ) or enabl e (if cleare d or pro-

grammed) the Power-up Timer. The Power-up Timer

should be enabled when Brown-out Reset is enabled,

although it is not required.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

•V

DD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 23.0

“Electrical Specifications”).

3.4 Watchdog Timer (WDT)

The WD T has the following features:

• Shar es an 8-bit prescale r with Timer0

• Time-out period is from 17 ms to 2.2 seconds,

nominal

• En abl ed by a Conf ig urat ion bit

WDT is cleared under certain conditions described in

Table 3-1.

3.4.1 WDT OSCILLATOR

The WDT derives its time base from 31 kHz internal

oscillator.

VDD PIC® MCU

MCLR

10 k

0.1 F

Note: The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word.

Note: When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the O ST to p erfo r m th e os ci ll ator d ela y

count. When the OST count has expired,

the WDT will begin counting (if enabled).

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PIC16(L)F722/3/4/6/7

3.4.2 WDT CONTROL

The WDTE bit is located in the Configuration Word

The PSA and PS<2:0> bits of the OPTION register

control the WDT period. See Section 11.0 “Timer0

Module” for more information.

FIGURE 3-1: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0

Postscaler

PS<2:0>

PSA

TO TMR0

Clock Source

To T1G

Divide by

512

WDTE

TMR1GE

T1GSS = 11

WDTE

WDT Re set

Low-Power

WDT O S C

TABLE 3-1: WDT STATUS

Conditions WDT

WDTE = 0Cleared

CLRWDT Command

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST

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3.5 Brown-Out Reset (BOR)

Brown-out Reset is enabled by programming the

BOREN<1:0> bits in the Configuration register. The

brown-out trip point is selectable from two trip points

via the BORV bit in the Configuration regist er.

Between the POR and BOR, complete voltage range

coverage for execution protection can be

implemented.

Two bits are used to enable the BOR. When

BOREN = 11, the BOR is always enabled. When

BOREN = 10, the BOR is en abl ed , bu t di sabled during

Sleep. When BOREN = 0X, the BOR is disabled.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 23.0 “Electrical Specifica-

tions”), the brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not en sure d to occu r if VDD falls below VBOR for more

than TBOR.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Pow er-up T imer will be re-initial ized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

FIGURE 3-3: BROWN-OUT SITUATIONS

Note: When erasing Flash program memory , the

BOR is forced to enabled at the minimum

BOR setting to ensure that any code pro-

tection circuitry is operating properly.

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset 64 ms(1)

< 64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is program med to ‘0’.

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3.6 Time-out Sequence

On power-u p, the tim e-out sequ ence is as fo llows: first,

PWR T ti me out is invoked af ter POR has e xpired , the n

OST is activated after the PWRT time out has expired.

The total time out will vary based on oscillator

configuration and PWRTE bit status. For example, in

EC mode with PWRTE bit = 1 (PWRT disabled), there

will be no time out at all. Figure 3-4, Figure 3-5 and

Figure 3-6 depict time-out sequences.

Since th e time ou ts oc cur from th e POR puls e, if MCLR

is kept lo w long enough, the time ou ts will expire . Then,

bringing MCLR high will begin execution immediately

(see Figure 3-5). This i s usefu l for te sting purpos es or

to synchronize more than one PIC16(L)F722/3/4/6/7

device operating in parallel.

Table 3-3 shows the Reset conditions for some special

registers.

3.7 Power Control (PCON) Register

The Power Contro l (PCON) register has two S t atus bits

to indicate what type of Reset that last occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00 in the Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

For more information, see Section 3.5 “Brown-Out

Reset (BOR)”.

TABLE 3-2: TIME OUT IN VARIOUS SITUATIONS

TABLE 3-3: RESET BITS AND THEIR SIGNIFICANCE

Oscillator Configuration Power-up Brown-out Reset Wake-up from

Sleep

PWRTE = 0PWRTE = 1PWRTE = 0PWRTE = 1

XT, HS, LP(1) TPWRT + 1024 •

TOSC 1024 • TOSC TPWRT + 1 024 •

TOSC 1024 • TOSC 1024 • TOSC

RC, EC, INTOSC TPWRT —TPWRT ——

Note 1: LP mode with T1O SC disa ble d.

POR BOR TO PD Condition

0u11Power-on Reset

1011Brown-out Reset

uu0uWDT Reset

uu00WDT Wake-up

uuuuMCLR Reset during normal operation

uu10MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

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FIGURE 3-4: TIM E-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

FIGURE 3-5: TIM E-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

FIGURE 3-6: TIM E-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT T ime-out

OST Time-out

Internal Reset

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

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TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS

Brown-out Reset(1) MCLR Reset/

WDT Rese t Wake-up from Sleep through

Interrup t/ Time out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h/80h/

100h/180h xxxx xxxx xxxx xxxx uuuu uuuu

TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h/82h/

102h/182h 0000 0000 0000 0000 PC + 1 (3)

STATUS 03h/83h/

103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)

FSR 04h/84h/

104h/184h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h xxxx xxxx xxxx xxxx uuuu uuuu

PORTB 06h xxxx xxxx xxxx xxxx uuuu uuuu

PORTC 07h xxxx xxxx xxxx xxxx uuuu uuuu

PORTD(6) 08h xxxx xxxx xxxx xxxx uuuu uuuu

PORTE 09h ---- xxxx ---- xxxx ---- uuuu

PCLATH 0Ah/8Ah/

10Ah/18Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh/8Bh/

10Bh/18Bh 0000 000x 0000 000x uuuu uuuu(2)

PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(2)

PIR2 0Dh ---- ---0 ---- ---0 ---- ---u

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h 0000 00-0 uuuu uu-u uuuu uu-u

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

SSPBUF 13h xxxx xxxx xxxx xxxx uuuu uuuu

SSPCON 14h 0000 0000 0000 0000 uuuu uuuu

CCPR1L 15h xxxx xxxx xxxx xxxx uuuu uuuu

CCPR1H 16h xxxx xxxx xxxx xxxx uuuu uuuu

CCP1CON 17h --00 0000 --00 0000 --uu uuuu

RCSTA 18h 0000 000x 0000 000x uuuu uuuu

TXREG 19h 0000 0000 0000 0000 uuuu uuuu

RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu

CCPR2L 1Bh xxxx xxxx xxxx xxxx uuuu uuuu

CCPR2H 1Ch xxxx xxxx xxxx xxxx uuuu uuuu

CCP2CON 1Dh --00 0000 --00 0000 --uu uuuu

ADRES 1Eh xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 1Fh --00 0000 --00 0000 --uu uuuu

OPTION_REG 81h/181h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h 1111 1111 1111 1111 uuuu uuuu

TRISB 86h 1111 1111 1111 1111 uuuu uuuu

TRISC 87h 1111 1111 1111 1111 uuuu uuuu

TRISD(6) 88h 1111 1111 1111 1111 uuuu uuuu

TRISE 89h ---- 1111 ---- 1111 ---- uuuu

PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu

PIE2 8Dh ---- ---0 ---- ---0 ---- ---u

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 3-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: PIC16F724/727/PIC16LF724/727 only.

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PCON 8Eh ---- --qq ---- --uu(1,5) ---- --uu

T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu

OSCCON 90h --10 qq-- --10 qq-- --uu qq--

OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu

PR2 92h 1111 1111 1111 1111 uuuu uuuu

SSPADD 93h 0000 0000 0000 0000 uuuu uuuu

SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu

SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu

WPUB 95h 1111 1111 1111 1111 uuuu uuuu

IOCB 96h 0000 0000 0000 0000 uuuu uuuu

TXSTA 98h 0000 -010 0000 -010 uuuu -uuu

SPBRG 99h 0000 0000 0000 0000 uuuu uuuu

APFCON 9Ch ---- --00 ---- --00 ---- --uu

FVRCON 9Dh q000 --00 q000 --00 uuuu --uu

ADCON1 9Fh -000 --00 -000 --00 -uuu --uu

CPSCON0 108h 0--- 0000 0--- 0000 u--- uuuu

CPSCON1 109h ---- 0000 ---- 0000 ---- uuuu

PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu

PMADRL 10Dh xxxx xxxx xxxx xxxx uuuu uuuu

PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu

PMADRH 10Fh ---x xxxx ---x xxxx ---u uuuu

ANSELA 185h --11 1111 --11 1111 --uu uuuu

ANSELB 186h --11 1111 --11 1111 --uu uuuu

ANSELD(6) 188h 1111 1111 1111 1111 uuuu uuuu

ANSELE 189h ---- -111 ---- -111 ---- -uuu

PMCON1 18Ch 1--- ---0 1--- ---0 u--- ---u

TABLE 3-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Brown-out Reset(1) MCLR Reset/

WDT Rese t Wake-up from Sleep through

Interrup t/Time out

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 and PIR2 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 3-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: PIC16F724/727/PIC16LF724/727 only.

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TABLE 3-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Condition Program

Counter STATUS

Power-on Reset 0000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 0000h 000u uuuu ---- --uu

MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu

WDT Reset 0000h 0000 uuuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 0000h 0001 1xxx ---- --10

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt

vector (0004h) after execution of PC + 1.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 B it 0 V alue on POR,

BOR

Value on

all other

Resets(1)

STATUS IRP RP1 RP0 TO PD ZDC C0001 1xxx 000q quuu

PCON ——— — ——PORBOR ---- --qq ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are

not used by Resets.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watc hdog Timer Res et during normal operation.

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4.0 INTERRUPTS

The PIC16(L)F722/3/4/6/7 device family features an

interruptible core, allowing certain events to preempt

normal program flow. An Interrupt Service Routine

(ISR) is used to determine the source of the interrupt

and act ac cordingly. Some interrupt s can be confi gured

to wake the MCU from Sleep mode.

The PIC16(L)F722/3/4/6/7 device family has 12

interrupt sources, differentiated by corresponding

interrupt enable and flag bits:

• Timer0 Overflow Interrupt

• External Edge Detect on INT Pin Interrupt

• PORTB Change Interrupt

• Timer1 Gate Interrupt

• A/D Conversion Complete Interrupt

• AUSART Receive Interrupt

• AUSART Transmit Interrupt

• SSP Event Interrupt

• CCP1 Event Interru pt

• Timer2 Match with PR2 Interrupt

• Timer1 Overflow Interrupt

• CCP2 Event Interru pt

A block diagram of the interrupt logic is shown in

Figure 4-1.

FIGURE 4-1: INTERRUPT LOGIC

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)(1)

Inter rupt to CPU

TMR1GIE

TMR1GIF

ADIF

ADIE

IOC-RB0

IOCB0

IOC-RB1

IOCB1

IOC-RB2

IOCB2

IOC-RB3

IOCB3

CCP1IF

CCP1IE

IOC-RB4

IOCB4

IOC-RB5

IOCB5

IOC-RB6

IOCB6

IOC-RB7

IOCB7

RCIF

RCIE

TMR2IE

TMR2IF

SSPIE

SSPIF

TXIE

TXIF

TMR1IE

TMR1IF

Note 1: Some peripherals depend upon the

system clock for operation. Since the

system clock is suspended during

Sleep, these peripherals will not wake

the part from Sleep. See Section 19.1

“Wake-up from Sleep”.

CCP2IF

CCP2IE

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4.1 Operation

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt

event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt even t is contain ed in the

PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record

individual interrupts via Interrupt Flag bits. Interrupt

Flag bit s will be s et, regardle ss of the st atus of th e GIE,

PEIE and individual Interrupt Enable bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Cur rent Program Counter (PC) is p ushed on to the

stack

• PC is loaded with the interrupt vector 0004h

The ISR determines the source of the interrupt by

polling the Interrupt Flag bits. The Interrupt Flag bits

must be cleared before exiting the ISR to avoid

repeated interrupts. Because the GIE b it is cleared, any

interrupt that occurs while executing the ISR will be

recorded through its Interrupt Flag, but will not cause

the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack an d setting the GIE bit.

For additional information on a specific interrupt’s

operation, refer to its peripheral chapter.

4.2 Interrupt Latency

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code e xecution at the

interrupt vector begins. The latency for synchronous

interrupts is three instruction cycles. For asynchronous

interrupts, the latency is three to four instruction cycles,

depending on when the interrupt occurs. See Figure 4-2

for timing details.

FIGURE 4-2: INT PIN INTERRUPT TIMING

Note 1: Individual Interrupt Flag bits are set,

regardless of the state of any other

enable bits.

2: All inte rrupts wi ll be ignore d while the G IE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC + 1 PC + 1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC + 1)

Inst (PC – 1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes .

4: For minimum width of INT pulse, refer to AC specifications in Section 23.0 “Electrical Specifications”.

5: INTF is enabled to be set any tim e during the Q4-Q1 cycles.

(1) (2)

(3) (4)

(5)

(1)

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4.3 Interrupt s During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without t he system clock. The interr upt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

process or will bran ch to the inte rrupt vector . O therwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to the Section 19.0

“Power-Down Mode (Sleep)” for more details.

4.4 INT Pin

The external interrupt, INT pin, causes an

asynchronous, edge-triggered interrupt. The INTEDG bit

of the OPTION register determines on which edge the

interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the INTCON register will be set when a valid

edge appears on the INT pin. If the GI E and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector. This interrupt is

disabled by clearing the INTE bit of the INTCON register .

4.5 Context Savi ng

When an interrupt occurs, only the return PC value is

saved to the stack. If the ISR modifies or uses an

instruction that modifies key registers, their values

must be s aved at the begi nning of the ISR and res tored

when the ISR completes. This prevents instructions

following the ISR from using invalid data. Examples of

key registers include the W, STATUS, FSR and

PCLATH reg isters.

The code shown in Example 4-1 can be use d t o do the

following.

• Save the W regi ster

• Save the S TATUS register

• Save the PCLATH re gister

• Execute the ISR program

• Restore the P CLATH register

• Restore the STATUS register

• Restore the W register

Since most instructions modify the W register, it must

be saved immediately upon entering the ISR. The

SWAPF instruction is used when saving and restoring

the W and STATUS registers because it will not affect

any bits in the STATUS register. It is useful to place

W_TEMP in shared memory because the ISR cannot

predict which bank will be selected when the interrupt

occurs.

The processor will branch to the interrupt vector by

loading the PC with 0004h. The PCLATH register will

remain unchanged. This requires the ISR to ensure

that the PCLATH register is set properly before using

an instruction that causes PCLATH to be loaded into

the PC. See Section 2.3 “PCL and PCLATH” for

details on PC operation.

Note: The microcontroller does not normally

require saving the PCLATH register.

However, if computed GOTO’s are used,

the PCLATH register mu st be saved at the

beginning of the ISR and restored when

the ISR is complete to ensure correct

progra m flow.

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EXAMPLE 4-1: SAVING W, STATUS AND PCLATH REGISTERS IN RAM

4.5.1 INTCON REGISTER

The INTCON register is a readable and writable

for TMR0 register overflow, PORTB change and

external RB0/INT/SEG0 pin interrupts.

MOVWF W_TEMP ;Copy W to W_TEMP register

SWAPF STATUS,W ;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

BANKSEL STATUS_TEMP ;Select regardless of current bank

MOVWF STATUS_TEMP ;Copy status to bank zero STATUS_TEMP register

MOVF PCLATH,W ;Copy PCLATH to W register

MOVWF PCLATH_TEMP ;Copy W register to PCLATH_TEMP

:(ISR) ;Insert user code here

BANKSEL STATUS_TEMP ;Select regardless of current bank

MOVF PCLATH_TEMP,W ;

MOVWF PCLATH ;Restore PCLATH

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

Note: Interru pt flag bit s are set when an inter rupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

PIC16(L)F722/3/4/6/7

DS40001341F-page 44  2007-2015 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE(1) T0IF(2) INTF RBIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: T imer0 Ov erfl ow Interru pt Enab le bit

1 = Enables the Timer0 interrupt

0 = Disables the Timer0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: PORTB Change Interrupt Enable bit(1)

1 = Enables the PORTB change interrupt

0 = Disables the PORTB change interrupt

bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)

1 = TM R0 register ha s overflowed (must be cleared i n software)

0 = TM R0 register did not over flow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: PORTB Change Interrupt Flag bit

1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in

software)

0 = None of the PORTB general purpose I/O pins have changed state

Note 1: The appropriate bits in the IOCB register must also be set.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

 2007-2015 Microchip Technology Inc. DS40001341F-page 45

PIC16(L)F722/3/4/6/7

4.5.2 PIE1 REGIS T ER

The PIE1 regis te r con t ai ns th e in terrupt enable bit s, a s

shown in Register 4-2.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enable the Timer1 Gate Acquisition complete interrupt

0 = Disable the Timer1 Gate Acquisition complete interrupt

bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt

0 = Disables the ADC interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt

0 = Disables the Timer2 to PR2 match interrupt

bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt

0 = Disables the Timer1 overflow interrupt

PIC16(L)F722/3/4/6/7

DS40001341F-page 46  2007-2015 Microchip Technology Inc.

4.5.3 PIE2 REGIS TER

The PIE2 regis te r con t ai ns th e in terrupt enable bit s, a s

shown in Register 4-3.

Note: Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

 2007-2015 Microchip Technology Inc. DS40001341F-page 47

PIC16(L)F722/3/4/6/7

4.5.4 PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 4-4.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Timer1 Gate is inactive

0 = Timer1 Gate is active

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = A/D conversion complete (must be cleared in software)

0 = A/D conversion has not completed or has not been started

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART rec eive buffer is full (c leared by reading RCREG)

0 = The USART receive buffer is not full

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1 = The Transmission/Reception is complete (must be cleared in software)

0 = Waiting to Transmit/Receive

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1 register c apture occurred (must be cleared in soft ware)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit

1 = A Timer2 to PR2 match occurred (must be cleared in software)

0 = No Timer2 to PR2 match occurred

bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit

1 = The TMR1 register overflowed (must be cleared in software)

0 = The TMR1 register did not overflow

PIC16(L)F722/3/4/6/7

DS40001341F-page 48  2007-2015 Microchip Technology Inc.

4.5.5 PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 4-5.

TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 Unimplemented: Read as ‘0’

bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture Mode:

1 = A TMR1 register c apture occurred (must be cleared in soft ware)

0 = No TMR1 register capture oc curred

Compare Mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIE2 ——————— CCP2IE ---- ---0 ---- ---0

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR2 ——————— CCP2IF ---- ---0 ---- ---0

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.

 2007-2015 Microchip Technology Inc. DS40001341F-page 49

PIC16(L)F722/3/4/6/7

5.0 LOW DROPOUT (LDO)

VOLTAGE REGULATOR

The PIC16F722/3/4/6/7 devices differ from the

PIC16LF722/3/4/6/7 devices due to an internal Low

Dropout (LDO) voltage regulator. The PIC16F722/3/4/

6/7 devices contain an internal LDO, while the

PIC16LF722/3/4/6/7 ones do not.

The litho gra phy of t he die allows a maxi mum o per ating

voltage of 3.6V on the internal digital logic. In order to

continue to support 5.0V designs, a LDO voltage

regulator is integrated on the die. The LDO voltage

regulator allows for the internal digital logic to operate

at 3.2V, while I/O’s operate at 5.0V (VDD).

The LD O volt age regul ator req uires an external b ypass

capacitor for stability. One of three pins, denoted as

VCAP, can be configured for the external bypass

capacitor. It is recommended that the capacitor be a

cerami c cap bet ween 0.1 to 1.0 µF. The VCAP pin is not

intende d to suppl y power t o external loads. An ext ernal

voltage regulator should be used if this functionality is

required. In addition, external devices should not

supply power to the VCAP pin.

On power-up, the external capacitor will look like a

large load on the LDO voltage regulator. To prevent

erroneous operation, the device is held in Reset while

a constant current source charges the external

capacitor. After the cap is fully charged, the device is

released from Reset. For more information, refer to

Section 23.0 “Electrical Specifications”.

See Configuration Word 2 register (Register 8-2) for

VCAP enable bits.

PIC16(L)F722/3/4/6/7

DS40001341F-page 50  2007-2015 Microchip Technology Inc.

6.0 I/O PORTS

There are as many as 35 general purpose I/O pins

available. Depending on which peripherals are

enabled , some or all of the pins may not be a vailable as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

6.1 Alternate Pin Function

The Alternat e Pin Fun ct ion Control (APFC ON) reg is ter

is used to steer specific peripheral input and output

functions between dif ferent pins. The APFCON reg ister

is shown in Register 6-1. For this device family, the

following functions can be moved between different

pins.

•SS

(Slave Select)

• CCP2

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — SSSEL CCP2SEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’.

bit 1 SSSEL: SS Input Pin Selection bit

0 =SS function is on RA5/AN4/CPS7/SS/VCAP

1 =SS function is on RA0/AN0/SS/VCAP

bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit

0 = CCP2 function is on RC1/T1OSI/CCP2

1 = CCP2 function is on RB3/CCP2

 2007-2015 Microchip Technology Inc. DS40001341F-page 51

PIC16(L)F722/3/4/6/7

6.2 PORTA and the TRISA Registers

PORTA is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 6-3). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driv er). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 6-1 shows how to

initialize PORTA.

Reading the PORTA register (Register 6-2) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the POR T dat a latc h.

The TRISA register (Register 6-3) controls the PORTA

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISA register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 6-1: INITIALIZI NG PORTA

Note: The ANSELA register must be initialized

to config ure an analog channel as a digit al

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTA ;

CLRF PORTA ;Init PORTA

BANKSEL ANSELA ;

CLRF ANSELA ;digital I/O

BANKSEL TRISA ;

MOVLW 0Ch ;Set RA<3:2> as inputs

MOVWF TRISA ;and set RA<7:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RA<7:0>: PORTA I/ O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)

0 = PORTA pin configured as an output

PIC16(L)F722/3/4/6/7

DS40001341F-page 52  2007-2015 Microchip Technology Inc.

6.2.1 ANSELA REGISTER

The ANSELA register (Register 6-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affec ted port.

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively

0 = Digital I/O. Pin is assigned to port or Digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

 2007-2015 Microchip Technology Inc. DS40001341F-page 53

PIC16(L)F722/3/4/6/7

6.2.2 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORT A pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the A/D Converter (ADC), refer to the

appropriate section in this dat a s heet.

6.2.2.1 RA0/AN0/SS/VCAP

Figure 6-1 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a slave select input for the SSP(1)

• a Voltage Regulator Capacitor pin (PIC16F72X

only)

6.2.2.2 RA1/AN1

Figure 6-2 shows the diagram for this pin. This pin is

configurable to function as one of the fol lowing:

• a general purpose I/O

• an analog input for the ADC

6.2.2.3 RA2/AN2

Figure 6-2 shows the diagram for this pin. This pin is

confi gu rab le to functi on a s on e of the fo ll owi ng :

• a general purpose I/O

• an analog input for the ADC

6.2.2.4 RA3/AN3/VREF

Figure 6-2 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a voltage reference input for the ADC

6.2.2.5 RA4/CPS6/T0CKI

Figure 6-3 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a capacitive sensing input

• a clock input for Timer0

The Timer0 clock input function works independently

of any TRIS register setting. Effectively, if TRISA4 = 0,

the PORTA4 register bit will output to the pad and

Clock Timer0 at the same time.

6.2.2.6 RA5/AN4/CPS7/SS/VCAP

Figure 6-4 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• an analog input for the ADC

• a capacitive sensing input

• a slave select input for the SSP(1)

• a V oltage Regulator Capacitor pin (PIC16F72X

only)

6.2.2.7 RA6/OSC2/CLKOUT/VCAP

Figure 6-5 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a crystal/resona tor con nec tio n

• a clock output

• a V oltage Regulator Capacitor pin (PIC16F72X

only)

6.2.2.8 RA7/OSC1/CLKIN

Figure 6-6 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• a crystal/resona tor con nec tio n

• a cl ock inpu t

Note: SS pin location may be selected as RA5

or RA0.

Note: SS pin location may be selected as RA5

or RA0.

PIC16(L)F722/3/4/6/7

DS40001341F-page 54  2007-2015 Microchip Technology Inc.

FIGURE 6-1: BLOCK DIAGRAM OF RA0

I/O Pin

VDD

VSS

ANSA0

Data Bus

PORTA

TRISA

PORTA

To SS P SS Input

To A/D Converter

VCAP EN = 00

To Volt age Regulator

PIC16F72X only

 2007-2015 Microchip Technology Inc. DS40001341F-page 55

PIC16(L)F722/3/4/6/7

FIGURE 6-2: RA<3: 1> BLOCK DIAGRAM

FIGURE 6-3: BLOCK DIAGRAM OF RA4

I/O Pin

VDD

VSS

ANSAx

Data Bus

PORTA

TRISA

PORTA

To A/D Converter

I/O Pin

VDD

VSS

ANSA4

Data Bus

PORTA

TRISA

PORTA

To Timer0 Clock MUX

To Cap Sensor

PIC16(L)F722/3/4/6/7

DS40001341F-page 56  2007-2015 Microchip Technology Inc.

FIGURE 6-4: BLOCK DIAGRAM OF RA5

I/O Pin

VDD

VSS

ANSA5

Data Bus

PORTA

TRISA

PORTA

To SSP SS Input

To A/D Converter

VCAP EN = 01

To Voltage Regulator

PIC16F72X only

To Cap Sensor

 2007-2015 Microchip Technology Inc. DS40001341F-page 57

PIC16(L)F722/3/4/6/7

FIGURE 6-5: BLOCK DIAGRAM OF RA6

FIGURE 6-6: BLOCK DIAGRAM OF RA7

1I/O Pin

VDD

VSS

FOSC = LP or XT or HS

Data Bus

PORTA

TRISA

PORTA

FOSC/4

CLKOUT(1)

Enable

Note 1: CLKOUT Enable = 1 When FOSC = RC or INTOSC (No I/O Selected).

Oscillator

Circuit

RA7/OSC1

VCAPEN = 10

To Voltage Re gula tor

(00X OR 010)

PIC16F72X only

I/O Pin

VDD

VSS

OSC = INTOSC or

Data Bus

PORTA

TRISA

PORTA

Oscillator

Circuit

RA6/OSC2

INTOSCIO

PIC16(L)F722/3/4/6/7

DS40001341F-page 58  2007-2015 Microchip Technology Inc.

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000

ADCON1 —ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 -000 --00 -000 --00

ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000

CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000

CONFIG2(1) — — VCAPEN1 VCAPEN0 — — — — ——

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1: PIC16F72X only.

 2007-2015 Microchip Technology Inc. DS40001341F-page 59

PIC16(L)F722/3/4/6/7

6.3 PORTB and TRISB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 6-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clea ring a TRI SB bi t (= 0) will make the corresponding

PORTB pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Example 6-2 shows how to ini tia liz e PO R TB.

Reading the PORTB register (Register 6-5) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, th is value is modifi ed and the n written

to the PORT data latch.

The TRISB register (Register 6-6) controls the PORTB

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’. Example 6-2 shows how to initialize PORTB.

EXAMPLE 6-2: INITIALIZING PO RTB

6.3. 1 ANSELB REGISTER

The ANSELB register (Register 6-9) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELB bits has no affect on digital

output functions. A pin with TRIS clear and ANSELB

set will still operate as a digital output, but the Input

mode will be analog. This can cause unexpected

behavior when executing read-modify-write

inst ruct ion s on the af f ected port.

6.3.2 WEAK PULL-UPS

Each of the PORTB pi ns has an ind ividually co nfigurable

internal weak pull-up. Control bits WPUB<7:0> enable or

disable each pull-up (see Register 6-7). Each weak

pull-up is automatically turned off when the port pin is

configured as an output. All pull-ups are disabled on a

Power-on Reset by the RBPU bit of the OPTION register.

6.3.3 INTERRUPT-ON-CHANGE

All of the PORTB pins are individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:0> enable

or disable the interrupt function for each pin. Refer to

disabled on a Power-on Reset.

For enabled interrupt-on-change pins, the present value

is compared with the old va lue l atch ed on the last rea d

of PORTB to determine which bits have changed or

mismatched the old value. The ‘mismatch’ outputs of

the last read are OR’d together to set the PORTB

Change Interrupt flag bit (RBIF) in the INTCON register .

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the inte rrupt by:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading or writing PORTB will end the mismatch

condition and allow flag bit RBIF to be cleared. The latch

holding the last read value is not affected by a MCLR nor

Brown-out Reset. After these Resets, the RBIF flag will

continue to be set if a mismatch is present.

Note: The ANSELB register must be initialized

to conf igure an analo g channel as a di gital

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTB ;

CLRF PORTB ;Init PORTB

BANKSEL ANSELB

CLRF ANSELB ;Make RB<7:0> digital

BANKSEL TRISB ;

MOVLW B’11110000’;Set RB<7:4> as inputs

;and RB<3:0> as outputs

MOVWF TRISB ;

Note: When a pin change occurs at the same

time as a read operation on PORTB, the

RBIF flag will always be set. If multiple

PORTB pins are configured for the

interrupt-on-change, the user may not be

able to identify which pin changed state.

PIC16(L)F722/3/4/6/7

DS40001341F-page 60  2007-2015 Microchip Technology Inc.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RB<7:0>: PORTB I/O Pin bit

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bit

1 = PORTB pin configured as an input (tri-stated)

0 = PORTB pin configured as an output

 2007-2015 Microchip Technology Inc. DS40001341F-page 61

PIC16(L)F722/3/4/6/7

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled

0 = Pull-up disabled

Note 1: Global RBPU bit of the OPTION register must be cleared for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in configured as an output.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bits

1 = Interrupt-on-change enabled

0 = Interrupt-on-change disabled

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

—— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively

0 = Digital I/O. Pin is assigned to port or Digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

PIC16(L)F722/3/4/6/7

DS40001341F-page 62  2007-2015 Microchip Technology Inc.

6.3.4 PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the SSP, I2C or interrupts, refer to the appropriate

section in this data sheet.

6.3.4.1 RB0/AN12/CPS0/INT

Figure 6-7 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a capacitive sensing input

• an external edge triggered interrupt

6.3.4.2 RB1/AN10/CPS1

Figure 6-8 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a capacitive sensing input

6.3.4.3 RB2/AN8/CPS2

Figure 6-8 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a capacitive sensing input

6.3.4.4 RB3/AN9/CPS3/CCP2

Figure 6-9 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a capacitive sensing input

• a Capture 2 input, Compare 2 output, and PWM2

output

6.3.4.5 RB4/AN11/CPS4

Figure 6-8 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• a capacitive sensing input

6.3.4.6 RB5/AN13/CPS5/T1G

Figure 6-10 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• an analog input for the ADC

• a capacitive sensing input

• a Timer1 gate input

6.3.4.7 RB6/ICSPCLK

Figure 6-11 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• In-Circuit Serial Programming clock

6.3.4.8 RB7/ICSPDAT

Figure 6-12 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a genera l purpo se I/O

• In-Circuit Serial Prog ramming data

Note: CCP2 pin location may be selected as

RB3 or RC1.

 2007-2015 Microchip Technology Inc. DS40001341F-page 63

PIC16(L)F722/3/4/6/7

FIGURE 6-7: BLOCK DIAGRAM OF RB0

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ANSB0

To A/D Converter

To External Interrupt Logic

To Cap Sensor

PIC16(L)F722/3/4/6/7

DS40001341F-page 64  2007-2015 Microchip Technology Inc.

FIGURE 6-8: BLOCK DIAGRAM OF RB4, RB<2:1>

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ANSB<4,2,1>

To A/D Converter

To Cap Senso r

 2007-2015 Microchip Technology Inc. DS40001341F-page 65

PIC16(L)F722/3/4/6/7

FIGURE 6-9: BLOCK DIAGRAM OF RB3

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ANSB<5,3>

To CCP2(1)

Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register.

CCP2OUT

Enable

To A/D Converter

To Cap Sensor

PIC16(L)F722/3/4/6/7

DS40001341F-page 66  2007-2015 Microchip Technology Inc.

FIGURE 6-10: BLO CK DIAGRAM OF RB5

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ANSB<5,3>

To Timer1 Gate

CCP2OUT

Enable

To A/D Converter

To Cap Sensor

 2007-2015 Microchip Technology Inc. DS40001341F-page 67

PIC16(L)F722/3/4/6/7

FIGURE 6-11: BLOCK DIAGRAM OF RB6

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ICSP™ MODE

ICSPCLK

TRIS_ICDCLK

PORT_ICDCLK

DEBUG

PIC16(L)F722/3/4/6/7

DS40001341F-page 68  2007-2015 Microchip Technology Inc.

FIGURE 6-12: BLO CK DIAGRAM OF RB7

I/O Pin

VDD

VSS

Data Bus

PORTB

TRISB

PORTB

QVDD

Weak

WPUB

WPUB RBPU

RD PORTB

IOCB

Interrupt-on-

Change

ICSPDAT_IN

TRIS_ICDDAT

PORT_ICDDAT

ICSP™ MODE

DEBUG

 2007-2015 Microchip Technology Inc. DS40001341F-page 69

PIC16(L)F722/3/4/6/7

TABLE 6-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

V alue on all

other

Resets

ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CPSCON0 CPSON ———CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000

CPSCON1 ———— CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000X

IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

PIC16(L)F722/3/4/6/7

DS40001341F-page 70  2007-2015 Microchip Technology Inc.

6.4 PORTC and TRISC Registers

PORTC is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 6-11). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corr esponding o utput dr iver in a Hi gh-Impeda nce mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pi n an outp ut ( i.e. , enab le th e out put dri ver and

put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .

Example 6-3 shows how to initialize PORTC.

Reading the PORTC register (Register 6-10) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch.

The TRISC register (Register 6-11) controls the PORTC

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘0’.

EXAMPLE 6-3: INITIALIZI NG PORTC

The location of the CCP2 function is controlled by the

CCP2SEL bit in the APFCON register (refer to

BANKSEL PORTC ;

CLRF PORTC ;Init PORTC

BANKSEL TRISC ;

MOVLW B‘00001100’ ;Set RC<3:2> as inputs

MOVWF TRISC ;and set RC<7:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RC<7:0>: PORTC General Purpose I/O Pin bits

1 = Port pin is > VIH

0 = Port pin is < VIL

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)

0 = PORTC pin conf igured as an output

 2007-2015 Microchip Technology Inc. DS40001341F-page 71

PIC16(L)F722/3/4/6/7

6.4.1 RC0/T1OSO/T1CKI

Figure 6-13 shows the diagram for this pin. T his p in is

configurable to function as one of the following:

• a general purpose I/O

• a Timer1 oscillator output

• a Timer1 clock input

6.4.2 RC1/T1OSI/CCP2

Figure 6-14 shows the diagram for this pin. T his p in is

configurable to function as one of the following:

• a general purpose I/O

• a Timer1 oscillator input

• a Capture 2 input, Compare 2 output, and PWM2

output

6.4.3 RC2/CCP1

Figure 6-15 shows the diagram for this pin. T his p in is

configurable to function as one of the following:

• a general purpose I/O

• a Capture 1 input, Compare 1 output, and PWM1

output

6.4.4 RC3/SCK/SCL

Figure 6-16 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a SPI clock

•an I

2C clock

6.4.5 RC4/SDI/SDA

Figure 6-17 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• a SPI data i nput

•an I

2C data I/O

6.4.6 RC5/SDO

Figure 6-18 shows the diagram for this pin. T his p in is

configurable to function as one of the following:

• a general purpose I/O

• a SPI data output

6.4.7 RC6/TX/CK

Figure 6-19 shows the diagram for this pin. T his p in is

configurable to function as one of the following:

• a general purpose I/O

• an asynchronous serial output

• a synchronous clock I/O

6.4.8 RC7/RX/DT

Figure 6-20 shows the diagram for this pin. Thi s p in is

configurable to function as one of the following:

• a genera l purpo se I/O

• an asynchronous serial input

• a synchronous serial data I/O

Note: CCP2 pin location may be selected as

RB3 or RC1.

PIC16(L)F722/3/4/6/7

DS40001341F-page 72  2007-2015 Microchip Technology Inc.

FIGURE 6-13: BLO CK DIAGRAM OF RC0

FIGURE 6-14: BLO CK DIAGRAM OF RC1

I/O Pin

VDD

VSS

T1OSCEN

Data Bus

PORTC

TRISC

PORTC

To Timer1 CLK Input

Oscillator

Circuit

RC1/T1OSI

I/O Pin

VDD

VSS

T1OSCEN

Data Bus

PORTC

TRISC

PORTC

To CCP2(1) Input

CCP2OUT

Enable Oscillator

Circuit

RC0/T1OSO

Note 1: CCP2 input is controlled by CCP2SEL in the APFCON register .

 2007-2015 Microchip Technology Inc. DS40001341F-page 73

PIC16(L)F722/3/4/6/7

FIGURE 6-15: BLO CK DIAGRAM OF RC2

FIGURE 6-16: BLO CK DIAGRAM OF RC3

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

To CCP1 Input

CCP1OUT

Enable

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

To SSP SPI

SSPEN

SSPM = I2C MODE

SCL

SSPEN

SCK_MASTER

SSPM = SPI MODE

To SSP I2C

Clock Input

SCL Input

(2)

I2C(1)

Note 1: I2C Schmitt Trigger has special input levels.

2: I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register.

PIC16(L)F722/3/4/6/7

DS40001341F-page 74  2007-2015 Microchip Technology Inc.

FIGURE 6-17: BLOCK DIAGRAM OF RC4

FIGURE 6-18: BLOCK DIAGRAM OF RC5

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

To SSP SPI

SSPEN

SSPM = I2C MODE

SDA FROM SSP

To SSP I2C

I2C(1)

SDA Input

Data Input

(2)

Note 1: I2C Schmitt Trigger has special input levels.

2: I2C Slew Rate limiting controlled by SMP bit of SSPSTAT register.

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

SDO

SSPEN

SSPM = SPI MODE

SDO

 2007-2015 Microchip Technology Inc. DS40001341F-page 75

PIC16(L)F722/3/4/6/7

FIGURE 6-19: BLOCK DIAGRAM OF RC6

FIGURE 6-20: BLOCK DIAGRAM OF RC7

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

To USART

SPEN

USART_TX

SYNC

USART_CK

TXEN

SYNC

CSRC

Sync Clock Input

I/O Pin

VDD

VSS

Data Bus

PORTC

TRISC

PORTC

To USART Data Input

SPEN

SYNC

USART_DT

SPEN

SYNC

TXEN

SREN

CREN

PIC16(L)F722/3/4/6/7

DS40001341F-page 76  2007-2015 Microchip Technology Inc.

TABLE 6-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

V alue on all

other

Resets

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON 0000 00-0 uuuu uu-u

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Port C.

 2007-2015 Microchip Technology Inc. DS40001341F-page 77

PIC16(L)F722/3/4/6/7

6.5 PORTD and TRISD Registers

PORTD is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISD

(Register 6-13). Setting a TRISD bit (= 1) will make the

corresponding PORTD pin an input (i.e., put the

corr esponding o utput dr iver in a Hi gh-Impeda nce mode).

Clearing a TRISD bit (= 0) will make the corresponding

PORTD pi n an outp ut ( i.e. , enab le th e out put dri ver and

put th e co nte nts of t he ou tp ut l atc h on t h e se le cted pi n) .

Example 6-4 shows how to initialize PORTD.

Reading the PORTD register (Register 6-12) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pin s are read, thi s value is modi fied and the n written

to the PORT data latch.

The TRISD register (Register 6-13) controls the

PORTD pin output drivers, even when they are being

used as analo g inpu ts. The us er shou ld ens ure the bit s

in the TRISD register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

EXAMPLE 6-4: INITIALIZI NG PORTD

6.5.1 ANSELD REGISTER

The ANSELD register (Register 6-9) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELD bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELD bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

Note: PO RTD i s a v ai lable on PIC16F724/LF724

and PIC 16 F72 7/L F72 7 on ly.

Note: The ANSELD register must be initialized

to config ure an analog channel as a digit al

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTD ;

CLRF PORTD ;Init PORTD

BANKSEL ANSELD

CLRF ANSELD ;Make PORTD digital

BANKSEL TRISD ;

MOVLW B‘00001100’ ;Set RD<3:2> as inputs

MOVWF TRISD ;and set RD<7:4,1:0>

;as outputs

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RD<7:0>: PORTD General Purpose I/O Pin bits

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: PORTD is not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.

PIC16(L)F722/3/4/6/7

DS40001341F-page 78  2007-2015 Microchip Technology Inc.

6.5.2 RD0/CPS8

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a general purpose I/O

• a capacitive sensing input

6.5.3 RD1/CPS9

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a general purpose I/O

• a capacitive sensing input

6.5.4 RD2/CPS10

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a genera l purpo se I/O

• a capacitive sensing input

6.5.5 RD3/CPS11

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a genera l purpo se I/O

• a capacitive sensing input

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits

1 = PORTD pin configured as an input (tri-stated)

0 = PORTD pin conf igured as an output

Note 1: TRISD is not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively

0 = Digital I/O. Pin is assigned to port or Digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: ANSELD register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.

Note: POR TD is available on PIC 16F724/LF724

and PIC16F727/LF727 only.

 2007-2015 Microchip Technology Inc. DS40001341F-page 79

PIC16(L)F722/3/4/6/7

6.5.6 RD4/CPS12

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a general purpose I/O

• a capacitive sensing input

6.5.7 RD5/CPS13

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a general purpose I/O

• a capacitive sensing input

6.5.8 RD6/CPS14

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a genera l purpo se I/O

• a capacitive sensing input

6.5.9 RD7/CPS15

Figure 6-21 shows the diagram for these pins. They are

configurable to function as one of the following:

• a genera l purpo se I/O

• a capacitive sensing input

FIGURE 6-21: BLOCK DIAGRAM OF RD<7:0>

TABLE 6-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000

CPSCON1 — — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0 ---- 0000 ---- 0000

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx xxxx xxxx

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.

Note 1: These registers are not implemented on the PIC16F722/723/726/PIC16LF722/ 723/726 devices, read as ‘0’.

I/O Pin

VDD

VSS

ANSD<7:0>

Data Bus

PORTD

TRISD

PORTD

Note: PORTD is avail a ble on P IC16F72 4/L F7 24 and PIC16F7 27/ LF 727 onl y.

To Cap Sensor

PIC16(L)F722/3/4/6/7

DS40001341F-page 80  2007-2015 Microchip Technology Inc.

6.6 PORTE and TRISE Registers

PORTE is a 4-bit wide, bidirectional port. The

corres pond ing d ata direc tion regis ter is TRISE. Se tting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e.,

enable the output driver and put the contents of the

output latch on the s el ec te d p in ). The exception is RE3,

which is input only and its TRIS bit will always read as

‘1’. Example 6-5 sh ow s h ow to init ia li ze PO RTE.

Readi ng t he PO R T E regi ste r (Register 6-15) reads th e

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch. RE3 reads ‘0’ when

MCLRE = 1.

The TR I SE r eg is t er ( Register 6-16) controls the PORTE

pin output drivers, even when they are being used as

analog inputs. The user should ensure the bits in the

TRISE register are maintained set when using them as

analog inputs. I/O pins configured as analog input always

read ‘ 0’.

EXAMPLE 6-5: INITIALIZING PORTE

Note: RE<2:0> and TRISE<2:0> are not

implem en ted on the PIC16F722/723/726/

PIC16LF722/723/726. Read as ‘0’.

Note: The ANSELE register must be initialized

to conf igure an analo g channel as a di gital

input. Pins configured as analog inputs

will read ‘0’.

BANKSEL PORTE ;

CLRF PORTE ;Init PORTE

BANKSEL ANSELE ;

CLRF ANSELE ;digital I/O

BANKSEL TRISE ;

MOVLW B‘00001100’ ;Set RE<2> as an input

MOVWF TRISE ;and set RE<1:0>

;as outputs

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PIC16(L)F722/3/4/6/7

U-0 U-0 U-0 U-0 R-x R/W-x R/W-x R/W-x

— — — — RE3 RE2(1) RE1(1) RE0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 RE<3:0>: PORTE I/O Pin bits(1)

1 = Port pin is > VIH

0 = Port pin is < VIL

Note 1: RE<2:0> are not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.

U-0 U-0 U-0 U-0 R-1 R/W-1 R/W-1 R/W-1

— — — — TRISE3 TRISE2(1) TRISE1(1) TRISE0(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3 TRISE3: RE3 Port Tri-state Control bit

This bit is always ‘1’ as RE3 is an input only

bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1)

1 = PORTE pin configured as an input (tri-stated)

0 = PORTE pin configured as an output

Note 1: TRISE<2:0> are not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as ‘0’.

PIC16(L)F722/3/4/6/7

DS40001341F-page 82  2007-2015 Microchip Technology Inc.

TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

— — — — — ANSE2(2) ANSE1(2) ANSE0(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively

0 = Digital I/O. Pin is assigned to port or Digital special function.

1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

2: ANSELE register is not implemented on the PIC16F722/723/72 6/PIC16LF722/723/726. Re ad as ‘ 0’

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B it 0 Value on

POR, BOR

Value on

all other

Resets

ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

PORTE ———— RE3 RE2 RE1 RE0 ---- xxxx ---- xxxx

TRISE ————TRISE3

(2) TRISE2(1) TRISE1(1) TRISE0(1) ---- 1111 ---- 1111

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE

Note 1: These registers are not implemented on the PIC16F722/723/726/PIC16LF722/ 723/726 device s, read as ‘0’.

2: This bit is always ‘1’ as RE3 is input only.

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PIC16(L)F722/3/4/6/7

6.6.1 RE0/AN5(1)

Figure 6-22 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

6.6.2 RE1/AN6(1)

Figure 6-22 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

6.6.3 RE2/AN7(1)

Figure 6-22 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

6.6.4 RE3/MCLR/VPP

Figure 6-23 shows the diagram for this pin. This pin is

configurable to function as one of the following:

• a general purpose inpu t

• as Master Clear Reset with weak pull-up

• a programming voltage reference input

Note 1: RE0/AN5 is availab le on

PIC16F724/LF724 and

PIC16F7 27/ LF72 7 o n ly.

Note 1: RE0/AN5 is availab le on

PIC16F724/LF724 and

PIC16F7 27/ LF72 7 o n ly.

Note 1: RE0/AN5 is availab le on

PIC16F724/LF724 and

PIC16F7 27/ LF72 7 o n ly.

PIC16(L)F722/3/4/6/7

DS40001341F-page 84  2007-2015 Microchip Technology Inc.

FIGURE 6-22: BLOCK DIAGRAM OF RE<2:0>

FIGURE 6-23: BLOCK DIAGRAM OF RE3

I/O Pin

VDD

VSS

To A/D Converter

ANSE<0:2>

Data Bus

PORTE

TRISE

PORTE

Note: RE<2:0> are not implemented on PIC16F722/723/726/PIC16LF722/723/726.

I/O Pin

VSS

Data Bus

TRISE

PORTE

VSS

High-Voltage

Detect

In-Circuit Serial Programming™ mode

Pulse Filter

MCLR

MCLR Circuit

Power for Programming Flash

VDD

Weak

ICSP™ Mode Detect

 2007-2015 Microchip Technology Inc. DS40001341F-page 85

PIC16(L)F722/3/4/6/7

7.0 OSCILLATOR MODULE

7.1 Overview

The oscillator module has a wide variety o f clock s ources

and selection features that allow it to be used in a wide

range o f a pplic atio ns wh ile m axim izi ng pe rform ance and

minimizing power consumption. Figure 7-1 illustrates a

block d ia gram of the os cillator mo du le.

Clock sources can be configured from external

oscilla tors, quartz crystal resonators , ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system can be configured to use an internal calibrated

high-frequency oscillator as clock source, with a choice

of se lec t abl e s peed s v ia software.

Clock source modes are configured by the FOSC bits

in Configuration Word 1 (CONFIG1). The oscillator

module can be configured for one of eight modes of

operation.

1. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

2. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

3. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

4. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

5. EC – External clock with I/O on OSC 2/CLKOUT.

6. HS – High Gain Crystal or Ceramic Resonator

mode.

7. XT – Medium Gain Crystal or Ceramic

Resonator Oscillator mode.

8. LP – Low-Power Crystal mode.

FIGURE 7-1: SI MPL I FI ED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

(CPU and Peripherals)

OSC1

OSC2

Sleep

External Oscillator

LP, XT, HS, RC, EC

System Clock

Postscaler

MUX

16 MHz/500 kHz

8 MHz/250 kHz

4 MHz/125 kHz

2 MHz/62.5 kHz

IRCF<1:0>

FOSC<2:0>

(Configu ra ti on Word 1)

Internal Oscillator (OSCCON Register)

500 kHz INTOSC

32x

MUX

PLL

PLLEN

(Configuration Word 1)

PIC16(L)F722/3/4/6/7

DS40001341F-page 86  2007-2015 Microchip Technology Inc.

7.2 Clock Source Modes

Clock source modes can be classified as external or

internal.

• Internal clock source (INTOSC) is contained

within the oscillator module and derived from a

500 kHz high precision oscillator. The oscillator

module has eight selectable output frequencies,

with a maximum internal frequency of 16 MHz.

• Ext ern al c loc k mo de s rely on ext erna l circuitry for

the clock source. Examples are: oscillator

module s (EC mode), quartz crystal res ona tors or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

The syste m cl oc k can be selected betwee n ex ternal or

internal clock sources via the FOSC bits of the

Configuration Word 1.

7.3 Internal Clock Modes

The oscillator module has eight output frequencies

derived from a 500 kHz high precision oscillator. The

IRCF bits of the OSCCON register select the

postscaler applied to the clock source dividing the

frequency by 1, 2, 4 or 8. Setting the PLLEN bit of the

Config ura tion Word 1 loc ks t he inte rna l c lo ck s ourc e to

16 MHz befo re the p ostscal er is sel ecte d by the I RCF

bits. T he P LLEN bit m us t be se t or c lea red at th e ti me

of programming; therefore, only the upper or low four

clock source frequencies are selectable in software.

7.3.1 INTOSC AND INTOSCIO MODES

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the devi ce is pr ogrammed using the o scillator selectio n

or the FOSC<2:0> bits in the CONFIG1 register. See

Section 8.0 “Device Configuration” for more

information.

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT outputs the selected

inter nal oscillator fr equency div ided by 4. Th e CLKOUT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

In INTOSCIO mode, OSC1/CLKIN and

OSC2/CLKOUT are available for general purpose I/O.

7.3.2 FREQUENCY SELECT BITS (IRCF)

The output of the 500 kHz INTOSC and 16 MHz

INT OSC, with Pha se-Locke d Loop en abled, connect to

a postscaler and multiplexer (see Figure 7-1). The

Internal Oscillator Frequency Select bits (IRCF) of the

OSCCON register select the frequency output of the

internal oscillator. Depending upon the PLLEN bit, one

of four frequencies of two frequency sets can be

selected via software:

If PLLEN = 1, frequency selection is as follows:

•16 MHz

• 8 MHz (default after Reset)

•4 MHz

•2 MHz

If PLLEN = 0, frequency selection is as follows:

•500 kHz

• 250 kHz (default after Reset)

•125 kHz

•62.5 kHz

There is no start-up delay before a new frequency

selected in the IRCF bits takes effect. This is because

the old and new fre que nc ies are deri ved from INT O SC

via the post s ca ler and multiplexe r.

Start-up delay specifications are located in the

Table 23-2 in Section 23.0 “Electrical

Specifications”.

Note: Following any Reset, the IRCF<1:0> bits

of the OSCCON register are set to ‘10’ and

the freq uency selec tion is se t to 8 MHz or

250 kHz. The user can modify the IRCF

bits to select a different frequency.

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PIC16(L)F722/3/4/6/7

7.4 Oscillator Control

The Oscillator Control (OSCCON) register (Figure 7-1)

display s the st atus and a llows fre que ncy sele ction of t he

internal oscillator (INTOSC) system clock. The

OSCCON reg is ter c ont a ins the foll ow ing bits:

• Frequency selection bits (IRCF)

• Status Locked bits (ICSL)

• Status Stable bi ts (ICSS)

U-0 U-0 R/W-1 R/W-0 R-q R-q U-0 U-0

—— IRCF1 IRCF0 ICSL ICSS — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 IRCF<1:0>: Internal Oscillator Frequency Select bits

When PLLEN = 1 (16 MHz INTOSC)

11 =16MHz

10 = 8 MHz (POR value)

01 =4MHz

00 =2MHz

When PLLEN = 0 (500 kHz INTOSC)

11 =500kHz

10 = 250 kHz (POR value)

01 =125kHz

00 =62.5kHz

bit 3 ICSL: Internal Clock Oscillator Status Locked bit (2% Stable)

1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) is in lock

0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet locked

bit 2 ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable)

1 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy

0 = 16 MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy

bit 1-0 Unimplemented: Read as ‘0’

PIC16(L)F722/3/4/6/7

DS40001341F-page 88  2007-2015 Microchip Technology Inc.

7.5 Oscillator Tuning

The INTOSC is factory calibrated but can be adjusted

in software by writing to the OSCTUNE register

(Register 7-2).

The default value of the OSCTUNE register is ‘0’. The

value is a 6-bit two’s complement number.

When the OSCTUNE register is modified, the INTOS C

frequency will begin shif tin g to th e new frequen cy. Code

execution continues during this shift. There is no

indication that the shif t has occ urred.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: Frequency Tuning bits

01 1111 = Maximu m frequency

01 1110 =

•

00 0001 =

00 0000 = Oscillator module is running at the factory-calibrated frequency.

11 1111 =

•

10 0000 = Minimum freq uency

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PIC16(L)F722/3/4/6/7

7.6 External Clock Modes

7.6.1 OSCILLATOR START-UP TIMER (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations on the OSC1 pin before the device is

release d from Reset. This occ urs follo wing a Power-on

Reset (POR) and when the Power-up Timer (PWRT)

has expired (if configured), or a wake-up from Sleep.

During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

cryst al res onator or ce ramic res onator, has starte d and

is providing a stable system clock to the oscillator

module.

7.6.2 EC MODE

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 7-2 shows the pin

connections for EC mode.

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC® MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

FIGURE 7-2: E X TERNAL CLOCK (EC)

MODE OPERATION

7.6.3 LP, XT, HS MODES

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 7-3). The mo de select s a low ,

medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier . LP mode current consumption

is the least of the three modes. This mode is bes t suited

to drive resonators with a low drive level specification, for

example, tuning fork type cry st als.

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current c onsumption is the medium of the three mo des.

This mode is best suited to drive resonators with a

medium drive level specification.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier . HS mode current cons umption

is the highest of the three modes. This mode is best

suited for reso nators that require a hi gh d riv e se tting.

Figure 7-3 and Figure 7-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 7-3: QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

OSC1/CLKIN

OSC2/CLKOUT(1)

I/O

Clock from

Ext. System PIC® MC U

Note 1: Alternate pin functions are described in

Secti on 6.1 “Alternate Pin Functi on”.

Note 1: Quartz crystal characteristics vary

according to type, package and

manufacturer. The user should consult the

manuf actu rer da ta shee ts for spec ifi catio ns

and recom mended applicati on.

2: Always veri fy oscill ator performan ce over

the VDD and temperature range that is

expected for the application.

3: For oscillator desig n assistance, reference

the following Microchip Applications Notes:

• AN826, Crystal Oscillator Basics and

Crystal Selection for rfPIC® and PIC®

Devices (DS00826)

• AN849, Basic PIC® Oscillator Design

(DS00849)

• AN943, Practical PIC® Oscillator

Analysis and Design (DS00943)

• AN949, Making Y our Oscillator Work

(DS00949).

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator mode

selected.

Quartz

RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

Crystal

OSC2/CLKOUT

PIC16(L)F722/3/4/6/7

DS40001341F-page 90  2007-2015 Microchip Technology Inc.

FIGURE 7-4: CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

7.6.4 EXTERNAL RC MODES

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

In RC mode, the RC circuit connects to OSC1.

OSC2/CLKOUT outputs the RC oscillator frequency

divide d by 4. This signal ma y b e u se d to provide a clock

for external circuitry, synchronization, calibration, test

or other application requirements. Figure 7-5 shows

the external RC mode connections.

FIGURE 7-5: EXTERNAL RC MODES

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

The RC oscillator frequency is a function of the supply

voltage, the resis t or (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

• threshold voltage variation

• component tolerances

• packaging varia tio ns in capacita nc e

The user also needs to take into account variation due

to tolerance of external RC components used.

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Note 1: A series resistor (RS) may be required for

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

C2 Ceramic RS(1)

OSC1/CLKIN

RF(2) Sleep

To Internal

Logic

PIC® MCU

RP(3)

Resonator

OSC2/CLKOUT

OSC2/CLKOUT(1)

CEXT

REXT

PIC® MCU

OSC1/CLKIN

FOSC/4 o r

Internal

Clock

VDD

VSS

Recommended values: 10 k  REXT  100 k, <3V

3 k  REXT  100 k, 3-5V

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are described in

Section 6.1 “Alternate Pin Function”.

2: Output depend s upon RC or RCIO clock mod e.

I/O(2)

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets(1)

CONFIG1(1) —CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

OSCCON —— IRCF1 IRCF0 ICSL ICSS — — --10 qq-- --10 qq--

OSCTUNE —— TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shade d cells are not used by clock sources.

Note 1: See Configuration Word 1 (Register 8-1) for operation of all bits.

 2007-2015 Microchip Technology Inc. DS40001341F-page 91

PIC16(L)F722/3/4/6/7

8.0 DE VICE CONFIGURATION

Device Configuration consists of Configuration Word 1

and Configuration Word 2 registers, Code Protection

and Device ID.

8.1 Configuration Words

There are several Configuration Word bits that allow

different oscillator and memory protection options.

These are implemented as Configuration Word 1

2008h. These registers are only accessible during

programming.

R/P-1 R/P-1 U-1(4) R/P-1 R/P-1 R/P-1

—— DEBUG PLLEN — BORV BOREN1 BOREN0

bit 15 bit 8

U-1(4) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

—CPMCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13 DEBUG: In-Circuit Debugger Mode bit

1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins

0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger

bit 12 PLLEN: INTOSC PLL Enable bit

0 = INTOSC Frequency is 500 kHz

1 = INTOSC Frequency is 16 MHz (32x)

bit 11 Unimplemented: Read as ‘1’

bit 10 BORV: Brown-out Reset Voltage selection bit

0 = Brown-out Reset Voltage (VBOR) set to 2.5 V nominal

1 = Brown-out Reset Voltage (VBOR) set to 1.9 V nominal

bit 9-8 BOREN<1:0>: Brown-out Reset Selection bits(1)

0x = BOR disabled (Preconditioned State)

10 = BOR enabled during operation and disabled in Sleep

11 = BOR enabled

bit 7 Unimplemented: Read as ‘1’

bit 6 CP: Code Protection bit(2)

1 = Program memory code protection is disabled

0 = Program memory code protection is enabled

bit 5 MCLRE: RE3/ MCLR pin function select bit(3)

1 = RE 3/MCLR pin fu nction is MC LR

0 = RE 3/MCLR pin function is digital input, MCLR internally tied to VDD

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.

3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

4: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.

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bit 4 PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3 WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0 FOSC<2:0>: Oscillator Sele ction bits

111 = RC osci llator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on

RA7/OSC1/CLKIN

100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on

RA7/OSC1/CLKIN

011 = EC: I/O function on RA6/OS C2/CL KOUT pin , CLKIN on RA7/OSC1/CLKIN

010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001 = XT oscil la tor: Cr ys t al /res ona tor on RA6 /O SC 2/CLKOUT and RA7/OSC1/ CL KIN

000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire program memory will be erased when the code protection is turned off.

3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

4: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.

U-1(1) U-1(1) U-1(1) U-1(1) U-1(1) U-1(1)

— — — — — — — —

bit 15 bit 8

U-1(1) U-1(1) R/P-1 R/P-1 U-1(1) U-1(1) U-1(1) U-1(1)

— — VCAPEN1 VCAPEN0 — — — —

bit 7 bit 0

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-6 Unimplemented: Read as ‘1’

bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits

For the PIC16LF72X:

These bits are ignored. All VCAP pin functions are disabled.

For the PIC16F72X:

00 =V

CAP functionality is enabled on RA0

01 =V

CAP functionality is enabled on RA5

10 =V

CAP functionality is enabled on RA6

11 = All VCAP functions are disabled (not recommended)

bit 3-0 Unimplemented: Read as ‘1’

Note 1: MPLAB® X IDE masks unimplemented Configuration bits to ‘0’.

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8.2 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out us ing ICSP™ for verific ation purposes.

8.3 User ID

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during Program/Verify mode. Only

the Le ast Si gnifi can t s eve n bits of the I D loc ati ons are

reported when using MPLAB IDE. See the

“PIC16(L)F72X Memory Programming Specification”

(DS41332) for more information.

Note: The entire Flash program memory will be

erased w hen the code prote ction is turned

off. See the “PIC16(L)F72X Memory

Programming Specification” (DS41332)

for more information.

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9.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 8-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 8-bit binary result via successive

approximation and stores the conversion result into the

ADC result register (ADRES). Figure 9-1 shows the

bloc k diagram of the ADC.

The ADC vol tage referen ce is softw are select able to be

either internally generated or externally supplied.

The AD C can gener ate an i nterrupt upon comple tio n of

a conve rsion. This inte rrupt can be used to wake-up the

device from Sleep.

FIGURE 9-1: ADC BLOCK DIAGRAM

AN0

AN1

AN2

AN4

AVDD

VREF+

ADON

GO/DONE

ADREF = 10

ADREF = 0x

CHS<3:0>

VSS

AN5

AN6

AN7

AN3

AN8

AN9

AN10

AN11

AN12

AN13

Reserved

FVREF

0000

0001

0010

0011

0100

0101

0111

0110

1000

1001

1010

1011

1100

1101

1110

1111

ADC

ADRES

ADREF = 11

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9.1 ADC Configuration

When configuring and using the ADC, the following

functio ns must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conv ersion clock source

• Interrupt control

• Results formatting

9.1.1 PORT CONFIGURATION

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin should be configured for analog by setting the

associate d TRIS and ANSEL bits. Refer to Section 6.0

“I/O Ports” for more information.

9.1.2 CHANNEL SELECTION

The CHS bits of the ADCON0 r egister det ermine whic h

channel is connected to the sample and hold circuit.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

9.1.3 ADC VOLTAGE REFERENCE

The ADREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive

voltage reference can be either VDD, an external

volt age source or the internal Fixed V olt age Refere nce.

The nega tiv e v oltage referenc e i s al w ays c onn ec ted to

the ground reference. See Section 10.0 “Fixed

Voltage Reference” for more details on the Fixed

Voltage Refere nc e.

9.1.4 CONVERSION CLOCK

The source of the conversion clock is software

selectable via the ADCS bits of the ADCON1 register.

There are seven possible clock options:

•F

OSC/2

•FOSC/4

•F

OSC/8

•F

OSC/16

•FOSC/32

•F

OSC/64

•F

RC (dedicated internal oscillator)

The time to complete one bit conversion is defined as

TAD. One full 8-bit conversion requires 10 TAD periods

as sh own in Figure 9-2.

For correct conversion, the appropriate TAD

specif ica tio n m us t be m et . R efe r to th e A/D conv ers io n

requirements in Section 23.0 “Electrical

Specifications” for more information. Table 9-1 gives

examples of appropriate ADC clock selections.

Note: Analo g v ol tages on any pin t hat is d efin ed

as a digital input may cause the input

buffer to conduct excess current.

Note: Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

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TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

ADC Clock Period (TAD) Device Freque ncy (FOSC)

ADC

Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

Fosc/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s

Fosc/4 100 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s4.0 s

Fosc/8 001 400 ns(2) 0.5 s(2) 1.0 s2.0 s8.0 s(3)

Fosc/16 101 800 ns 1.0 s2.0 s4.0 s16.0 s(3)

Fosc/32 010 1.6 s2.0 s4.0 s8.0 s(3) 32.0 s(3)

Fosc/64 110 3.2 s4.0 s8.0 s(3) 16.0 s(3) 64.0 s(3)

FRC x11 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

TAD1 TAD2 TAD3TAD4TAD5 TAD6TAD7 TAD8 TAD9

Set GO/DONE bit

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b7 b6 b5 b4 b3 b2 b1 b0

Tcy to TAD

Conversion Starts

ADRES register is loaded,

GO/DONE bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

TAD0

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9.1.5 INTERRUPTS

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 reg ister. The ADC i nterrupt enabl e is the ADIE b it

in the PIE1 register. The ADIF bit must be cleared in

software.

This interrupt can be generated while the device is

operatin g or while in Sle ep. If the device is in Sle ep, the

interrupt will wake-up the device. Upon waking from

Sleep, the n ext ins tructio n follow ing th e SLEEP instruc-

tion is always executed. If the user is attempting to

wake-up from Sleep and resume in-line code execu-

tion, the GIE and PEIE bits of the INTCON register

must be disabled. If the GIE and PEIE bits of the INT-

CON register are enabled, execution will switch to the

Interr upt Serv ice Routi ne.

Please refer to Section 9.1.5 “Interrupts” for more

information.

9.2 ADC Operation

9.2.1 STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

9.2.2 COMPLETION OF A CONVERSION

When the conversion is complete, th e ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRES register with new conversion

result

9.2.3 TERMINATIN G A CONVERSION

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRES register will be updated with the partially

complete Analog-to-Digital conversion sample.

Incomplete bits will match the last bit converted.

9.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC wa its on e addition al instru ction bef ore sta rting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

9.2.5 SPECIAL EVENT TRIGGER

The Special Event Trigger of the CCP module allows

periodic ADC measurements without software

intervention. When this trigger occurs, the GO/DONE

bit is se t by hard ware an d th e Timer1 counter res et s to

zero.

Using the S pecial Event T rigger does not assure proper

ADC timi ng. I t is the user’s resp onsib ility t o ensu re that

the ADC timing requirements are met.

Refer to Section 15.0 “Capture/Compare/PWM

(CCP) Module” for more information.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the FRC oscillator is selected.

Note: The GO/DONE bit shou ld not be se t in the

same instruction that turns on the ADC.

Refe r to Section 9.2.6 “A/D Conversion

Procedure”.

Note: A devi ce Re se t forc es al l reg is ters to th eir

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

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9.2.6 A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to

perform an Ana log-to-Digital conversion:

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

• Con figure pin as an alog (Ref er to the ANSEL

2. Configure the ADC module:

• Select AD C conv ersi on clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt(1)

4. Wait the required acquisition time(2).

5. Start conversion by setting the GO/DONE bit.

6. Wait fo r ADC co nvers i on to com ple te b y o ne o f

the following:

• Po lli ng the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result.

8. Clear the ADC interru pt flag (requi red if interru pt

is enabled).

EXAMPLE 9-1: A/D CONVERSION

Note 1: The global interrupt can be disabl ed if the

user is at tempti ng to wake -up from Sle ep

and resume in-line code execution.

2: Refer to Section 9.3 “A/D Acquisition

Requirements”.

;This code block configures the ADC

;for polling, Vdd reference, Frc clock

;and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL ADCON1 ;

MOVLW B’01110000’;ADC Frc clock,

;VDD reference

MOVWF ADCON1 ;

BANKSEL TRISA ;

BSF TRISA,0 ;Set RA0 to input

BANKSEL ANSELA ;

BSF ANSELA,0 ;Set RA0 to analog

BANKSEL ADCON0 ;

MOVLW B’00000001’;AN0, On

MOVWF ADCON0 ;

CALL SampleTime ;Acquisiton delay

BSF ADCON0,GO ;Start conversion

BTFSC ADCON0,GO ;Is conversion done?

GOTO $-1 ;No, test again

BANKSEL ADRES ;

MOVF ADRES,W ;Read result

MOVWF RESULT ;store in GPR space

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9.2.7 ADC REGISTER DEFINITIONS

The following registers are used to control the

operati on of the AD C.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 =AN0

0001 =AN1

0010 =AN2

0011 =AN3

0100 =AN4

0101 =AN5

0110 =AN6

0111 =AN7

1000 =AN8

1001 =AN9

1010 =AN10

1011 =AN11

1100 =AN12

1101 =AN13

1110 =Reserved

1111 = Fixed Voltage Reference (FVREF)

bit 1 GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

bit 0 ADON: ADC Enable bit

1 = ADC is enabled

0 = ADC is disabled and consumes no operating current

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U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0

— ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0

bit 7 bit 0

Legend:

R = Readable bit W = Writ able bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0 ’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits

000 =F

OSC/2

001 =F

OSC/8

010 =F

OSC/32

011 =F

RC (clock supplied from a dedicated RC oscillator)

100 =F

OSC/4

101 =F

OSC/16

110 =F

OSC/64

111 =F

RC (clock supplied from a dedicated RC oscillator)

bit 3-2 Unimplemented: Read as ‘0’

bit 1-0 ADREF<1:0>: Voltage Reference Configuration bits

0x =V

REF is connec ted to VDD

10 =VREF is connected to external VREF (RA3/AN3)

11 =V

REF is connec ted to internal Fixed Voltage Reference

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

8-bit conversion result.

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9.3 A/D Acquisition Requirements

For the AD C to meet it s specified accu rac y, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is show n i n Figure 9-3. The source imped-

ance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 9-3. The maximum recommended imped-

ance for analog sources is 10 k. As the source

impedance is decreased, the acquisition time may be

decreased. After the analog input channel is selected

(or changed), an A/D acquisition must be done before

the conversion can be started. To calculate the mini-

mum acquisition time, Equation 9-1 may be used. Thi s

equation assumes th at 1/2 LSb e rror is use d (256 step s

for the ADC). The 1/2 LSb error is the maximum error

allowed for the ADC to meet its specified resolution.

EQUATION 9-1: ACQUISITION TIME EXAMPLE

Note 1: The reference voltage (VREF) h as no effect on the equation, since it can cels itself out.

2: The charge holding capacitor (C HOLD) is not discha rged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=

TAMP TCTCOFF++=

2µs TCTemperature - 25°C0.05µs/°C++=

TCCHOLD RIC RSS RS++ ln(1/511)–=

10pF 1k



10k



++– ln(0.001957)=

1.12

=µs

TACQ 2ΜS1.12ΜS50°C- 25°C0.05ΜS/°C++=

4.42ΜS=

VAPPLIED 1e

Tc–

---------

–







VAPPLIED 11

2n1+

1–

--------------------------–





VAPPLIED 11

2n1+

1–

--------------------------–





VCHOLD=

VAPPLIED 1e

TC–

----------

–







VCHOLD=

;[1] VCHOLD charged to within 1/2 lsb

;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]

The value for TC can be approximated with the following equations:

Solving for TC:

Therefore:

Temperature 50°C and external impedance of 10k



5.0V VDD=

Assumptions:

Note: Where n = number of bits of the ADC.

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FIGURE 9-3: ANALOG INPUT MODEL

FIGURE 9-4: ADC TRANSFER FUNCTION

CPIN

Rs ANx

5 pF

VDD

VT  0.6V

VT  0.6V I LEAKAGE(1)

RIC  1k

Sampling

Switch

SS Rss

CHOLD = 10 pF

VSS/VREF-

Sampling Switch

567891011

(k)

VDD

Legend: CPIN

I LEAKAGE

RIC

CHOLD = Input Capacitance

= Threshold Voltage

= Leakage current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

various junctions

RSS

Note 1: Refer to Section 23.0 “Electrical Specifications”.

RSS = Resistance of Sampling Switch

FFh

FEh

ADC Output Co de

FDh

FCh

04h

03h

02h

01h

00h

Full-Scale

FBh

1 LSB ideal

VSS Zero-Scale

Transition VREF

Transition

1 LSB ideal

Full-Scale Range

Analog Input Voltage

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TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

ADCON0 —— CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ADCON1 — ADCS2 ADCS1 ADCS0 —— ADREF1 ADREF0 -000 --00 -000 --00

ANSELA ——ANSA5ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

ANSELE — — — — — ANSE2 ANSE1 ANSE0 ---- -111 ---- -111

ADRES A/D Result Register Byte xxxx xxxx uuuu uuuu

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

FVRCON FVRRDY FVREN ———— ADFVR1 ADFVR0 q0-- --00 q0-- --00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISE — — — — TRISE3 TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for ADC

module.

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10.0 FIXED VOLTAGE REFERENCE

This device contains an internal voltage regulator. To

provide a reference for the regulator, a band gap

reference is provided. This band gap is also user

accessible via an A/D converter channel.

User level band gap functions are controlled by the

FVRCON register, which is shown in Register 10-1.

R-q R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

FVRRDY FVREN — — — — ADFVR1 ADFVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

q = Value depends on condition

bit 7 FVRRDY(1): Fixed Voltage Reference Ready Flag bit

0 = Fixed Voltage Reference output is not active or stable

1 = Fixed Voltage Referen ce out put is ready for use

bit 6 FVREN(2): Fixed Voltage R efer ence Enable bit

0 = Fixed Voltage Reference is disabled

1 = Fixed Voltage Reference is enabled

bit 5-2 Unimplemented: Read as ‘0’

bit 1-0 ADFVR<1:0>: A/D Converter Fixed Voltage Reference Selection bits

00 = A/D Converter Fixed Voltage Reference Peripheral output is off.

01 = A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V)

10 = A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)

11 = A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)

Note 1: FVRRDY is always ‘1’ for the PIC16F72X devices.

2: Fixed Voltage Reference output cannot exceed VDD.

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11.0 TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

• TMR0 can be used to gate Ti mer1

Figure 11-1 is a block diagram of the Timer0 module.

11 .1 Timer0 Op e ratio n

The T ime r0 module can be used as either an 8-b it timer

or an 8-bit counter.

11.1.1 8-BIT TI MER MODE

The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-Bit Timer mode is

selected by clearing the T0CS bit of the OPTION

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

11.1.2 8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin or the

Capacitive Sensing Oscillator (CPSOSC) signal.

8-Bit Counter mode u sing the T0CKI pin is select ed by

setting the T0CS bit in the OPTION register to ‘1’ and

resetting the T0XCS bit in the CPSCON0 register to ‘0’.

8-Bit Counter mode using the Capacitive Sensing

Oscillator (CPSOSC) signal is selected by setting the

T0CS bit in the OPTION register to ‘1’ and setting the

T0XCS bit in the CPSCON0 register to ‘1’.

The rising or falling tra nsition of the incrementing edge

for either input source is determined by the T0SE bit in

the OPTION register.

FIGURE 11-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Note: The value written to the TMR0 register

can be adjusted, in order to account for

the two instruction cycle delay when

TMR0 is w ritten.

T0CKI

T0SE

TMR0

WDT

Time-out

PS<2:0>

WDTE

Data Bus

Set Flag bi t T0IF

on Overflow

T0CS

8-bit

Prescaler

FOSC/4

PSA

Sync

2 TCY

Overflow to Timer1

Divide by

512

TMR1GE

T1GSS = 11

Cap. Sensing

T0XCS

Oscillator

Low-Power

WDT OSC

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11.1.3 SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignme nt is contro lled by the PSA bit o f the OPTION

must be cleared to a ‘0’.

There are eight prescaler options for the Timer0 mod-

ule ranging from 1:2 to 1:256. The prescale values are

select able via th e PS<2:0> bits of the OPTION registe r .

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

The prescaler is not readable or writable. When

assigned to the T im er0 module, all instructions writing to

the TMR0 register will clear the prescaler.

11.1.4 TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit can only

be cleared in software. The Timer0 interrupt enable is

the T0IE bit of the INTCON register.

11.1.5 8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter m ode, the inc rementing ed ge on

the T0CKI pin must be synchronized to the instruction

clock. Synchronization can be accomplished by

sampling the prescaler output on the Q2 and Q4 cycles

of the ins truction c lock. The high and lo w periods of th e

external clocking source must meet the timing

requirements as shown in Section 23.0 “Electrical

Specifications”.

Note: When the presc aler is a ssigned to W DT, a

CLRWDT inst ruction wi ll clear the p rescaler

along with the WDT.

Note: The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

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TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin

0 = Interrupt on falling edge of INT pin

bit 5 T0CS: TMR0 C loc k Sourc e Sele ct bit

1 = Transition on T0CKI pin or CPSOSC signal

0 = Internal instr uction cycle clock (FOSC/4)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assig nme nt bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS<2:0>: Prescaler Rate Select bits

Name Bit 7 Bit 6 B it 5 B it 4 Bit 3 Bit 2 Bit 1 B i t 0 Value on

POR, BOR

Value on

all other

Resets

CPSCON0 CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS 0--- 0000 0--- 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

TMR 0 Timer0 Mo dule Reg is ter xxxx xxxx uuuu uuuu

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Ti mer0 module.

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

BIT VALUE TMR0 RA TE W DT RATE

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12.0 TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit ti mer/c ounter reg ister p air (TMR1 H:TMR1 L)

• Programmable internal or external clock source

• 3-bit prescaler

• Dedicated LP os cillator circ uit

• Synchronous or asynchronous operation

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external c lock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

• Gat e Sing le-p ulse mode

• Gate Value Status

• Gate Event Interrupt

Figure 12-1 is a block diagram of the Timer1 module.

FIGURE 12-1: TIMER1 BLOCK DIAGRAM

TMR1H TMR1L

T1SYNC

T1CKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow TMR1(2)

TMR1ON

Note 1: ST Buffer is high speed type when using T1CKI.

2: Timer 1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

T1G

T1OSC

FOSC/4

Internal

Clock

T1OSO/T1CKI

T1OSI

T1OSCEN

T1CKI

TMR1CS<1:0>

(1)

Synchronize(3)

det

Sleep input

TMR1GE

From Timer0

From Timer2

T1GPOL

T1GVAL

T1GTM

Single Pulse

Acq. Control

T1GSPM

T1GGO/DONE

T1GSS<1:0>

OUT

FOSC

Internal

Clock

Cap. Sensing

From WDT

Overflow

Match PR2

Overflow

Q1 RD

T1GCON

Data Bus

det

Interrupt TMR1GIF

Set

T1CLK

FOSC/2

Internal

Clock

T1G_IN

TMR1ON

Oscillator

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12.1 Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

When us ed with an interna l clock source, t he modul e is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and

increments on every selected edge of the external

source.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers,

respectively. Table 12-1 displays the Timer1 enable

selections.

12.2 Clock Source S election

The TMR1CS<1:0> and T1OSCEN bits of the T1CON

Table 12-2 displays the c lock s ource selections.

12.2.1 INTERNAL CLOCK SOURCE

When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the Timer1 prescaler.

12.2.2 EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a coun ter.

When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI or the

capacitive sensing oscillator signal. Either of these

external clock sources can be synchronized to the

microcontroller system clock or they can run

asynchronously.

When used as a timer with a clock oscillator, an

external 32.768 kHz c rys tal can be u se d in conjunctio n

with the dedicated internal oscillator circuit.

TABLE 12-1: TIMER1 ENABLE

SELECTIONS

TMR1ON TMR1GE Timer1

Operation

00Off

01Off

10Always On

11Count Enabled Note: In Counter mode, a falling edge must be

registered by the counter prior to the first

inc rement ing ri sing ed ge after any one o r

more of the following conditions:

• Timer1 enabled after POR reset

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON= 1) when T1CKI

is low.

TABLE 12-2: CLOCK SOURCE SELECTIONS

TMR1CS1 TMR1CS0 T1OSCEN Clock Source

01xSystem Cloc k (F OSC)

00xInstruction Clock (FOSC/4)

11xCapacitive Sensing Oscillator

100External Clocki ng on T1C KI Pin

101Oscillator Circuit on T1OSI/T1OSO Pins

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12.3 Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however , the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

12.4 Timer1 Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO

(amplifier output). This internal circuit is to be used in

conjun cti on wi th an ext erna l 32.76 8 kHz cryst al.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register . The oscillator will

continue to run during Sleep.

12.5 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which w ill wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 12.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

12.5.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an e xternal asyn chronous cl ock will ens ure a valid

read (taken care of in hardware). However, the user

should keep i n mind that rea ding t he 16-bi t ti mer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes , it is re commend ed that th e user s imply sto p

the timer and write the desired values. A write

conte ntion may occ ur by writin g to th e time r regi sters,

while the register is incrementing. This may pro duce an

unpredictable va lue in the TMR1H:TMR1L register pair .

Note: The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay obs erv ed prio r to enabli ng Timer1.

Note: When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

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12.6 Timer1 Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 Gate

circuitry. This is also referred to as Timer1 Gate Count

Enable.

Timer1 Gate can also be driven by multiple selectable

sources.

12.6.1 TIMER1 GATE COUNT ENABLE

The T imer1 Gate is en abled by s etting the TMR1GE b it

of the T1GCON register. The polarity of the Timer1

Gate is configured using the T1GPOL bit of the

T1GCON register.

When Timer1 Gate (T1G) input is active, Timer1 will

increment on the rising edge of the Timer1 clock

source. When Timer1 Gate input is inactive, no

increm enting will oc cur and T ime r1 will hol d the current

count. See Figure 12-3 for timing details.

12.6.2 TIMER1 GATE SOURCE

SELECTION

The Timer1 Gate source can be selected from one of

four di f ferent sou rce s. Sou rce s elec tion is c ontroll ed by

the T1GSS bits of the T1GCON register. The polarity

for each available source is also selectable. Polarity

selection is controlled by the T1GPOL bit of the

T1GCON register.

TABLE 12-4: TIMER1 GATE SOURCES

12.6.2.1 T1G Pin Gate Operation

The T1G pin is one source for Timer1 Gate Control. It

can be use d to supply an external so urce to the T ime r1

Gate circuitry.

12.6.2.2 Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a

low-to-high pulse will automatically be generated and

internal ly su ppl ied to the Timer1 Ga te circui try.

12.6.2.3 Timer2 Match Gate Operation

The TMR2 register will increment until it matches the

value in the PR2 register. On the very next increment

cycle, TMR2 will be reset to 00h. When this Reset

occurs, a low-to-high pulse will automatically be

generated and internally supplied to the Timer1 Gate

circuitry.

12.6.2.4 Watchdog Overflow Gate Operation

The Watchdog Timer oscillator, prescaler and counter

will be automatically turn ed on when TMR1GE = 1 and

T1GSS selects the WDT as a gate source for Timer1

(T1GSS = 11). TMR1ON does not factor into the

oscillator, prescaler and counter enable. See

Table 12-5.

The PSA and PS bits of the OPTION register still

control w hat time -out interva l is select ed. Changi ng the

prescaler during operation may result in a spurious

capture.

Enabling the Watchdog Timer oscillator does not

automatically enable a Watchdog Reset or Wake-up

from Sleep upon counter overflow.

As the gate signal coming from the WDT counter will

generate different pulse widths depending on if the

WDT is enabled, when the CLRWDT instruction is

executed, and so on, Toggle mode must be used. A

specific sequence is required to put the device into the

correct state to capture the next WDT counter interval.

TABLE 12-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL T1G Timer1 Operation

00Counts

01Holds Count

10Holds Count

11Counts

T1GSS Tim er1 Ga te Sour ce

00 Timer1 Gate Pin

01 Overflow of Timer0

(TMR0 increments from FFh to 00h)

10 Timer2 match PR2

(TMR2 increments to match PR2)

11 Count Enabled by WDT Overflow

(Watchdog Time-out interval expired)

Note: When using the WDT as a gate source for

T imer1, operations that clear the W atchdog

Timer (CLRWDT, SLEEP instructions) will

aff ect the time interval being measured for

capacitive sensing. This includes waking

from Sleep. All other interrupts that might

wake the device from Sleep should be

disabled to prevent them from disturbing

the measurement period.

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TABLE 12-5: WDT/TIMER1 GATE INTERACTION

12.6.3 TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is

possible to measure the full-cycle length of a Timer1

gate sig nal, as opp osed to the duratio n of a singl e level

pulse.

The Timer1 Gate source is routed through a flip-flop

that changes state on every incrementing edge of the

signal. See Figure 12-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM

bit is c leared, the fl ip-flop is c leared and held c lear . Thi s

is necessary in order to control which edge is

measured.

12.6.4 TIMER1 GATE SINGLE-PULSE

MODE

When Ti mer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCO N register must be se t.

The Timer1 will be fully enabled on the next

incrementing edge. On the next trailing edge of the

pulse, the T1GGO/DONE bit will automatically be

cleared. No other gate events will be allowed to

increment Timer1 until the T1GGO/DONE bit is once

again set in software.

Clearing the T1GSPM bit of the T1GCON register will

also clear the T1GGO/DONE bit. See Figure 12-5 for

timing details.

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the Timer1

Gate source to be measured. See Figure 12-6 for

timing details.

12.6.5 TIMER1 GATE VALUE STATUS

When T imer1 Gat e V alue S tatus is utilized, it is possible

to read the most curre nt lev el of the gate con trol value.

The value is stored in the T1GVAL bit in the T1GCON

Gate is not enabled (TMR1GE bit is cleared).

12.6.6 TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of T1GVAL

occurs, the TMR1GIF flag bit in the PIR1 register will be

set. If the TMR1GIE bit in the PIE1 register is set, then

an interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1

Gate is not enabled (TMR1GE bit is cleared).

WDTE TMR1GE = 1

and

T1GSS = 11

WDT Oscillator

Enable WDT Reset Wake-up WDT Available for

T1G Source

1NYYYN

1YYYYY

0YYNNY

0NNNNN

Note: Enabling Toggle mode at the same time

as chan ging the gate po larity may res ult in

indeterm in ate ope rati on.

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12.7 Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the T ime r1 interru pt flag bi t of the PIR1 re gister i s

set. To enable the interrupt on rollover, you must set

these bits:

• TMR1ON bit of the T1CO N register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

12.8 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynch ronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1 CS bits of the T1CON register must be

configured

• T1OSCEN bit of the T1CON register must be

configured

• TMR1GIE bit of the T1GCON register must be

configured

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

Routine (0004h).

12.9 CCP Capture/Compare Ti me Base

The CCP module uses the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

In Compare mode, an event is triggered wh en the value

CCPR1H:CCPR1L register pair matches the value in

the TMR1H:TMR1L register pair. This event can be a

Special Event Trigger.

For more information, see Section 15.0

“Capture/Compare/PWM (CCP) Module”.

12.10 CCP Special Event Trigger

When the CCP is confi gu r ed to trig ger a sp ec ial even t,

the trigger will clear the TMR1H:TMR1L register pair.

This s pecial event does not cause a Timer1 interrupt.

The CCP modu le may still be configured to generate a

CCP interrupt.

In this mode of operation, the CCPR1H:CCPR1L

Timer1 shou ld be sy nc hron iz ed to the FOSC/4 to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

In the eve nt that a wri te to TMR1H or TMR1L coi ncides

with a Special Event T rigger from the CCP, the write will

take precedence.

For more information, see Section 9.2.5 “Special

Event Trigger”.

FIGURE 12-2: TIMER1 INCREMENTING EDGE

Note: The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter incremen ts.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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FIGURE 12-3: TIMER1 GATE COUNT ENABLE MODE

FIGURE 12-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1 N N + 1 N + 2 N + 3 N + 4

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

TIMER1 N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8

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FIGURE 12-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1 N N + 1 N + 2

T1GSPM

T1GGO/

DONE Set by software Cleared by hard ware on

falling edge of T1GVAL

Set by hardware on

falling edge of T1GVAL

Cleared by softwar e Cleared by

software

TMR1GIF

Counting enabled on

rising edge of T1G

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FIGURE 12-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

TIMER1 NN + 1

N + 2

T1GSPM

T1GGO/

DONE Set by software Cleared by hardware on

falling edge of T1GVAL

Set by hardw are on

falling edge of T1GVAL

Cleared by software Cleared by

software

TMR1GIF

T1GTM

Counting enabled on

rising edge of T1G

N + 4

N + 3

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12.11 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

various features of the Timer1 module.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 TMR1CS<1:0>: Timer 1 Cloc k Source Select bits

11 =Timer1 clock source is Capacitive S ensing Osci llat or (CAPOSC)

10 =Timer1 clock source is pin or oscillator:

If T1OSCEN = 0:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN = 1:

Crystal oscillator on T1OSI/T1OSO pins

01 =Timer1 clock source is system clock (FOSC)

00 =Timer1 clock source is instruction clock (FOSC/4)

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: LP Oscillator Enable Control bit

1 = Dedicated Timer1 oscillator circuit enabled

0 = Dedicated Timer1 oscillator circuit disabled

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> = 1X

1 = Do not synchronize external clock input

0 = Synchronize external clock input with system clock (FOSC)

TMR1CS<1:0> = 0X

This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.

bit 1 Unimplemented: Read as ‘0’

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Clears Timer1 Gate flip-flop

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12.12 Timer1 Gate Control Register

The T imer1 Gate Control register (T1GCON), shown in

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-x R/W-0 R/W-0

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR1GE: Tim er1 Ga te Enabl e bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1 = Timer1 counting is controlled by the Timer1 gate function

0 = Timer1 counts regardless of Timer1 gate function

bit 6 T1GPOL: Timer1 Gate Polarity bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high)

0 = Timer1 gate is active-low (Timer1 counts when gate is low)

bit 5 T1GTM: Timer1 Gate Toggle Mode bit

1 = Timer1 Gate Toggle mode is enabled.

0 = Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared

Timer1 gate flip flop toggles on every rising edge.

bit 4 T1GSPM: Timer1 Gate Single Pulse Mode bit

1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0 = Timer1 gate Single-Pulse mode is disabled

bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Ac quisition Stat us bit

1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge

0 = Timer1 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when T1GSPM is cleared.

bit 2 T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits

00 = Timer1 Gate pin

01 = Timer0 Overflow output

10 = TMR2 Match PR2 output

11 = Watchdog Timer scaler overflow

Watchdog Timer oscillator is turned on if TMR1GE = 1, regardless of the state of TMR1ON

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TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

ANSELB ——ANSB5ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON0000 00-0 uuuu uu-u

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu

Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

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13.0 TIMER2 MODU LE

The Timer2 module is an 8-bit timer with the following

features:

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

See Figure 13-1 for a block diagram of Timer2.

13.1 Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescal er is the n use d to

increm ent the TM R2 regis ter.

The val ues of T MR2 and PR2 are co nstan tly com pared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented.

The match output of the Timer2/PR2 comparator is

then fed into th e T i mer2 post sca ler. The post sca ler ha s

post scal e options of 1:1 to 1: 16 inclus ive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

The TMR2 and PR2 registers are both fully readable

and w rita ble. O n any Rese t, the TMR2 regis ter is set to

00h and the PR2 register is set to FFh.

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Tim er2 is turned off by clearin g

the TMR2ON bit to a ‘0’.

The Timer2 prescale r is contro lle d by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

• A write to TMR2 occurs.

• A write to T2CON occurs.

• Any device Reset occu rs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

FIGURE 13-1: TIMER2 BLOCK DIAGRAM

Note: TMR2 is not cleared when T2CON is

written.

Comparator

TMR2 Sets Flag

TMR2

Output

Reset

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

bit TMR2IF

TOUTPS<3:0>

T2CKPS<1:0>

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TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000 = 1:1 Pos tscaler

0001 = 1:2 Pos tscaler

0010 = 1:3 Pos tscaler

0011 = 1:4 Pos tscaler

0100 = 1:5 Pos tscaler

0101 = 1:6 Pos tscaler

0110 = 1:7 Pos tscaler

0111 = 1:8 Pos tscaler

1000 = 1:9 Pos tscaler

1001 = 1:10 Postscaler

1010 = 1:11 Postscaler

1011 = 1:12 Postscaler

1100 = 1:13 Postscaler

1101 = 1:14 Postscaler

1110 = 1:15 Postscaler

1111 = 1:16 Postscaler

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Va lue on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PR2 Timer2 Module Period Register 1111 1111 1111 1111

TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

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14.0 CAPACITIVE SENSING

MODULE

The capacitive sensing module allows for an inter action

with an end user without a mechanical interface. In a

typical application, the capacitive sensing module is

attached to a pad on a printed circuit board (PCB), which

is electrically isolated from the end user. When the end

user places their finger over the PCB pad, a capacitive

load is added, causi ng a frequency shift in the capacitive

sensing module. The capacitive sensing module

requires software and at least one timer resource to

determine the change in frequency. Key features of this

module include:

• Analog MUX for monitoring multiple inputs

• Capacitive sensing oscillator

• Multiple timer resources

• Software control

• Operation during Sleep

FIGURE 14-1: CAPAC ITIVE SENSING BLOCK DIAGRAM

T0CS

CPS0

CPS1

CPS2

CPS3

CPS4

CPS5

CPS6

CPS7

CPS8(1)

CPS9(1)

CPS10(1)

CPSCH<3:0>(2)

Capacitive

Sensing

Oscillator

CPSOSC

CPSON

CPSRNG<1:0>

TMR0

Set

T0IF

Overflow

T0XCS

T0CKI

T1CS<1:0>

T1OSC/

T1CKI

TMR1H:TMR1L

T1GSEL<1:0>

Timer1 Gate

Control Logic

T1G

CPSOUT

TMR2

Timer2 Module

Set

TMR2IF

Overflow Postscaler

CPS11(1)

CPS12(1)

CPS13(1)

CPS14(1)

CPS15(1)

CPSCLK

Note 1: Channels CPS<15:8> are implemented on PIC16F724/727/PIC16LF724/727 only.

2: CPSC H3 is not implemented on PIC16F722/723/726/PIC16LF722/723/726.

3: If CPSON = 0, disabling capacitive sensing, no channel is selected.

FOSC/4

FOSC

FOSC/4

Timer0 Module

Timer1 Module

CPSON(3)

WDT

Event

Overflow

Watchdog Timer Module

Scaler

PS<2:0>

LP WDT

OSC

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14.1 Analog MUX

The capacitive sensing module can monitor up to 16

inputs. The capacitive sensing inputs are defined as

CPS<15:0>. To determine if a frequency change has

occurred the user must:

• Select the appropriate CPS pin by setting the

CPSCH<3:0> bits of the CPSCON1 register

• Set the corresponding ANSEL bit

• Set the corresponding TRIS bit

• Run the software algorithm

Selection of the CPSx pin while the module is enabled

will c ause the capac itive sensin g osci llator to be on the

CPSx pin. Fail ure to set the c orrespondi ng ANSEL and

TRIS bits can cause the capacitive sensing oscillator to

stop, leading to false frequency readings.

14.2 Capacitive Sensing Oscillator

The ca p acitive sens ing o scil lator c onsi sts of a cons ta nt

current source and a constant current sink, to produce

a triangle waveform. The CPSOUT bit of the

CPSCON0 register shows the status of the capacitive

sensing oscillator, whether it is a sinking or sourcing

current. The oscillator is designed to drive a capacitive

load (sin gle PCB pa d) and at the same time, be a cloc k

source to either Timer0 or Timer1. The oscillator has

three different current settings as defined by

CPSRNG<1:0> of the CPSCON0 register . The different

current settings for the oscillator serve two purposes:

• Maximize the number of counts in a timer for a

fixed time base

• Maximize the count differential in the timer during

a change in frequency

14.3 Timer resources

To measure the change in frequency of the capacitive

sensin g oscillato r , a fixed ti me base is require d. For the

period of the fixed time base, the capacitive sensing

osci llator is used to clock either Timer0 or Timer1. The

frequency of the capacitive sensing oscillator is equal

to the number of counts in the timer divided by the

period of the fixed time base.

14.4 Fixed Ti me Base

To measure the frequency of the capacitive sensing

oscillator, a fixed time base is required. Any timer

resource or software loop can be used to establish the

fixed ti me base. It is up to t he end user to de termine the

method in which the fixed time base is generated.

14.4.1 TIMER0

To select Timer0 as the timer resource for the c apaci tive

sensing module:

• Set the T0XCS bit of the CPSCON0 register

• Clear the T0CS bit of the OPTION register

When Timer0 is chosen as the timer resource, the

capa citive sensi ng osci llator w ill be the cloc k sourc e for

Timer0. Refer to Section 11.0 “Timer0 Module” for

additional information.

14.4.2 TIMER1

To select Timer1 as the timer resource for the

capacitive sensing module, set the TMR1CS<1:0> of

the T1CON register to ‘11’. When Timer1 is chosen as

the tim er resourc e, the cap aciti ve sens ing oscill ator wil l

be the clock source for Timer1. Because the Timer1

module has a gate control, developing a time base for

the frequency measurement can be simplified using

either:

• The Timer0 overflow flag

• The Timer2 overflow flag

• The WDT overflow flag

It is recommend that one of these flags, in conjunction

with the toggle mode of the Timer1 Gate, is used to

develop the fixed time base required by the software

portion of the capacitive sensing module. Refer to

Section 12.0 “T imer1 M odule with Gate Control” for

additional information.

TABLE 14-1: TIMER1 ENABLE FUNCTION

Note: The fi xe d tim e b as e c an n ot be generated

by timer resource the capacitive sensing

oscillator is clocking.

TMR1ON TMR1GE Timer1 Operation

00 Off

01 Off

10 On

11Count Enabled by input

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14.5 Software Control

The softwar e portio n of the ca pacitive sensi ng module

is required to determine the change in frequency of the

capacitive sensing oscillator. This is accomplished by

the followi n g:

• Setting a fixed time base to acquire counts on

Ti mer0 or Timer1

• Establishing the nominal frequency for the

capacitive sensing oscillator

• Establishing the reduced frequency for the

capacitive sensing oscillator due to an additional

capacitive load

• Set the frequency threshold

14.5.1 NOMINAL FREQUENCY

(NO CAPACI TIVE LOA D)

To determine the nominal frequency of the capacitive

sensing oscillator:

• Re move any ex tra capa citive lo ad on the s elected

CPSx pin

• At the start of the fixed time base, clear the timer

resource

• At the end of the fixed tim e base save the value in

the timer resource

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator for the

given time base. The frequency of the capacitive

sensing oscillator is equal to the number of counts on

in the timer div ided by the period of the fixe d time base.

14.5.2 REDUCED FREQUENCY

(ADDITI ONA L CAPACIT IV E LOAD )

The extra capacitive load will cause the frequency of the

capacitive sensing oscil lat or to decre ase. To determ ine

the reduced frequency of the capacitive sensing

oscillator:

• Add a typical capacitive load on the se lecte d

CPSx pin

• Use the same fixed-time base as the nominal

frequenc y measurement

• At the start of the fixed-time base, clear the timer

resource

• At the end of th e fixed-ti me base sav e the val ue in

the timer resource

The value of the timer resource is the number of

oscillations of the capacitive sensing oscillator with an

additional capacitive load. The frequency of the

capacitive sensing oscillator is equal to the number of

count s on in the timer divided by t he peri od of the fixe d

time base. This frequency should be less than the

value obtained during the nominal frequency

measurement.

14.5.3 FREQUENCY THRESHOLD

The frequency threshold should be placed midway

between the value of nominal frequency and the

reduced frequency of the capacitive sensing oscillator.

Refer to Application Note AN1103, Software Handling

for Capacitive Sensing (DS01103) for more detailed

information the software required for capacitive

sensing module.

Note: For more information on general

Capacitive Sensing refer to Application

Notes:

• AN1101, Introduction to Capacitive

Sensing (DS01101)

• AN1102, La yout and Phys ical Design

Guidelines for Capacitive Sensing

(DS01102).

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14.6 Operation during Sleep

The ca p acitive sens ing o scil lator w ill conti nue to run a s

long as th e m odu le i s en abl ed, ind ependent of the part

being in Sl eep . In ord er for th e software to de term in e if

a frequency change has occurred, the part must be

awake. However, the part does not have to be awake

when the timer resource is acquiring counts. One way

to acquire the Timer1 counts while in Sleep is to have

Timer1 ga ted with the overflo w of the W atc hd og Timer.

This can be accomplished using the following steps:

1. Configure the Watchdog Time-out overflow as

the Timer1’s gate source T1GSS<1:0> = 11.

2. Set Timer1 Gate to toggle mode by setting the

T1GTM bit of the T1G C ON register.

3. Set the TMR1GE bit of the T1GCON register.

4. Set TMR1ON bit of the T1CON register.

5. Enable capacitive sensing module with the

appropriate current settings and pin selection.

6. Clear Timer1.

7. Put the part to Sleep.

8. On the first WDT overflow, the capacitive sens-

ing oscillator will begin to increment Timer1.

Then put the part to Sleep.

9. On the second WDT overflow Timer1 will stop

incrementing. Then run the software routine to

determine if a frequency change has occurred.

Refer to Section 12.0 “Timer1 Module with Gate

Control” for addition al information.

Note 1: When using the WDT to set the interval

on Timer1, any other source that wakes

the part up early will cause the WDT

overflow to be delayed, affecting the

value captured by Timer1.

2: Timer0 does not operate when in Sleep,

and therefore cannot be used for

capacitive sense measurements in

Sleep.

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R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R-0 R/W-0

CPSON — — — CPSRNG1 CPSRNG0 CPSOUT T0XCS

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CPSON: Capacitive Sensing Module Enable bit

1 = Capacitive sensing modul e is operating

0 = Capaci tive sensing module is shut off and consumes no oper ating current

bit 6-4 Unimplemented: Read as ‘0’

bit 3-2 CPSRNG<1:0>: Capacitive Sensing Oscillator Ra nge bits

00 = Oscillator is Off.

01 = Oscillator is in low range. Charge/discharge current is nominally 0.1 µA.

10 = Oscillator is in medium range. Charge/discharge current is nominally 1.2 µA.

11 = Oscillator is in high range. Charge/discharge current is nominally 18 µA.

bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit

1 = Oscillator is sourcing current (Current flowing out the pin)

0 = Oscillator is sinking current (Current flowing into the pin)

bit 0 T0XCS: Timer0 External Clock Source Select bit

If T0CS = 1

The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0:

1 = Timer0 Clock Source is the capacitive sensing oscillator

0 = Timer0 Clock Source is the T0CKI pin

If T0CS = 0

Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4.

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PIC16(L)F722/3/4/6/7

TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAP ACITIVE SENSING

U-0 U-0 U-0 U-0 R/W-0(2) R/W-0 R/W-0 R/W-0

— — — — CPSCH3 CPSCH2 CPSCH1 CPSCH0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 CPSCH<3:0>: Capacitive Sensing Channel Select bits

If CPSON = 0:

These bits are ignored. No channel is selected.

If CPSON = 1:

0000 = channel 0, (CPS0)

0001 = channel 1, (CPS1)

0010 = channel 2, (CPS2)

0011 = channel 3, (CPS3)

0100 = channel 4, (CPS4)

0101 = channel 5, (CPS5)

0110 = channel 6, (CPS6)

0111 = channel 7, (CPS7)

1000 = channel 8, (CPS8(1))

1001 = channel 9, (CPS9(1))

1010 = channel 10, (CPS10(1))

1011 = channel 11, (CPS11(1))

1100 = channel 12, (CPS12(1))

1101 = channel 13, (CPS13(1))

1110 = channel 14, (CPS14(1))

1111 = channel 15, (CPS15(1))

Note 1: These channels are not implemented on the PIC16F722/723/726/PIC16LF722/723/726.

2: This bit is not implemented on PIC16F722/723/726/PIC16LF722/723/726, Read as ‘0’

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

ANSELA —— ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

ANSELB —— ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 1111 1111

OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON0000 00-0 0000 00-0

T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.

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15.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events. In Capture mode, the peripheral allows the

timing of the duration of an event. The C ompare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate a pulse-width modulated signal of

varying frequency and duty cycle.

The timer resources used by the module are shown in

Table 15-1.

Additional information on CCP modules is available in

the Application Note AN594, Using the CCP Modules

(DS00594).

TABLE 15-1: CCP MODE – TIMER

RESOURCES REQUIR ED

TABLE 15-2: INTERACTION OF TWO CCP MODULES

CCP Mode Timer Resource

Capture Timer1

Compare Timer1

PWM Timer2

CCP1 Mode CCP2 Mode Interaction

Capture Capture Same TMR1 time base

Capture Compare Same TMR1 time base(1, 2)

Compare C ompare Same TMR1 time base(1, 2)

PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).

The rising edges will be aligned.

PWM Capture None

PWM Compare None

Note 1: If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on

the CCP2 pin.

2: If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1,

af fe cti ng the value captu r ed on the CCP1 pin.

Note: CCPRx and CCPx throughout this

document refer to CCPR1 or CCPR2 and

CCP1 or CCP2, respectively

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PIC16(L)F722/3/4/6/7

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mo de:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM<3:0>: CCP Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP module)

0001 = Unused (reserved)

0010 = Compare mode, toggle output on match (CCPxIF bit of the PIRx register is set)

0011 = Unused (reserved)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode, set output on match (CCPxIF bit of the PIRx register is set)

1001 = Compare mode, clear output on match (CCPxIF bit of the PIRx register is set)

1010 = Comp are mo de, generate software int errup t on m atc h (C CPx IF bit is set of the PIRx register,

CCPx pin is unaffected)

1011 = Compare mode, trigger special event (CCPxIF bit of the PIRx register is set, TMR1 is reset

and A/D conversion(1) is started if the ADC module is enabled. CCPx pin is unaffected.)

11xx = PWM mode.

Note 1: A/D conversion start feature is available only on CCP2.

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15.1 Capture Mode

In Capture mode, CCPRxH:CCPRxL captures the

16-bit val ue of the TMR1 register when an event occurs

on pin CCPx. An event is defined as one of the

following and is configured by the CCPxM<3:0> bits of

the CCPxCON register:

• Every falling edge

• Every rising edge

• Ever y 4th rising edge

• Every 16th rising edge

When a cap ture i s m ade, the I nterrupt Re quest Flag bit

CCPxIF of the PIRx register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value (refer to Figure 15-1).

15.1.1 CCPx PIN CONFIGURATION

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

FIGURE 15-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

15.1.2 TIMER1 MODE SELECTION

T imer1 must be running in Timer mode or Synchronized

Counter mod e for the CCP module to use the capture

feature. In Asynchronous Counter mode or when

Timer1 is clocked at F OSC, the capture operation may

not work.

15.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIEx register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIRx register

following any change in operating mode.

15.1.4 CCP PRESCALER

There are four prescaler settings specified by the

CCPxM<3 :0> bits o f the CCP xCON regis ter . Whenev er

the CCP module is turned off, or the CCP module is not

in Captu re mode, the presca ler count er is clea red. Any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler (refer to Example 15-1).

EXAMPLE 15-1: CHANGING B ETWEE N

CAPTURE PRESCALERS

15.1.5 CAPTURE DURING SLEEP

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

T imer1 module in Capture m ode. It can be dri ven by the

instruction clock (FOSC/4), or by an external clock

source.

If Timer1 is clocked by FOSC/4, then Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

If Timer1 is clocked by an external clock source, then

Capt ure m ode wil l ope rate as defi ned in Section 15.1

“Capture Mode”.

Note: If th e CCPx p in is c onfigured as an output,

a write to the port can cause a capture

condition.

CCPRxH CCPRxL

TMR1H TMR1L

Set Flag bit CCPxIF

(PIRx register)

Capture

Enable

CCPxCON<3:0>

Prescaler

 1, 4, 16

and

Edge Detect

CCPx

System Clock (FOSC)

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

Mode. I n order for Ca pture Mode to recog-

nize the trigger event on the CCPx pin,

Timer1 must be clocked from the Instruc-

tion Clock (FOSC/4) or from an external

clock source .

BANKSEL CCP1CON ;Set Bank bits to point

;to CCP1CON

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

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TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu

CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON

0000 00-0 uuuu uu-u

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 0000 0x00

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture.

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15.2 Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCPx module may:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register.

All Compare modes can generate an interrupt.

FIGUR E 1 5-2: COMPAR E MODE

OPERATION BLOCK

DIAGRAM

15.2.1 CCPx PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

15.2.2 TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

15.2.3 SOFTWARE INTERRUPT MODE

When Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPxIF bit in the PIRx

control of the CCPx pin (refer to the CCPxCON

15.2.4 SPECIAL E VENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Star ts an ADC conversion if ADC is enabled

(CCP2 onl y)

The CCPx module does not assert control of the CCPx

pin in this mode (refer to the CCPxCON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

reset until th e next r ising ed ge of the T imer1 clock. This

allows the CCPRxH, CCPRxL register pair to

effectively provide a 16-bit programmable period

15.2.5 COMPARE DURING SLEEP

The Compare Mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

Note: Clearing the CCPxCON register will force

the CCPx compare output latch to the

default lo w level. This is n ot the POR T I /O

data l atch.

CCPRxH CCPRxL

TMR1H TMR1L

Comparator

ROutput

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxCON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• Clear TMR1H and TMR1L registers.

• NOT set interrupt flag bit TMR1IF of the PIR1 register.

• Set the GO/DONE bit to start the ADC conversion

(CCP2 only).

CCPx 4

Note: Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. For the Compare operation of the

TMR1 register to the CCPRx register to

occur, Timer1 must be clocked from the

Instruction Clock (FOSC/4) or from an

external clock source.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 registe r.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will

preclude the Reset from occurring.

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TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu

CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —TMR1ON

0000 00-0 uuuu uu-u

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE T1GVAL T1GSS1 T1GSS0 0000 0x00 0000 0x00

TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Compare.

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15.3 PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCPx pin. The duty cycle, period and

resolution are determined by the following registers:

•PR2

•T2CON

• CCPRxL

• CCPxCON

In Pulse-Width Modulation (PWM) mode, the CCP

module produce s up to a 10 -bit resol ution PWM outp ut

on the CCPx pin.

Figure 15-3 sh ows a sim plifi ed b loc k dia gram of P WM

operation.

Figure 15-4 shows a typical waveform of the PWM

signal.

For a ste p-by-step proc edure on how t o set up the CC P

module for PWM operation, refer to Section 15.3.8

“Setup for PWM Operation”.

FIGURE 15-3: SIMPLIFIED PWM BLOCK

DIAGRAM

The PWM output (Figure 15-4) has a time base

(period) and a time that the output stays high (duty

cycle).

FIGURE 15-4: CCP PWM OUTPUT

15.3.1 CCPx PIN CONFIGUR ATION

In PWM mode, the CCPx pin is multiplexed with the

PORT data latch. The user must configure the CCPx

pin as an output by clearing th e associated TRIS bit.

Either RC1 or RB3 can be selected as the CCP2 pin.

Refer to Section 6.1 “Alternate Pin Function” for

more information.

CCPRxL

CCPRxH(2) (Slave)

Comparator

TMR2

PR2

(1)

Duty Cycle Registers CCPxCON<5:4>

Clear Timer2 ,

toggle CCPx pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler , to create the 10-bit time

base.

2: In PWM mode, CCPRxH is a read-only register.

TRIS

CCPx

Comparator

Note: Clearing the CCPxCON register will

relinquish CCPx control of the CCPx pin.

Period

Pulse Width

TMR2 = 0

TMR2 = CCPRxL:CCPxCON<5:4>

TMR2 = PR2

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15.3.2 PWM PE RIOD

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 15-1.

EQUATION 15-1: PWM PERIOD

When TM R2 is equa l to PR2, t he followi ng three ev ents

occur on the next increment cycle:

• TMR 2 is cl eare d

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

• The PW M duty c ycle is latc hed fro m CCPRx L int o

CCPRxH.

15.3.3 PWM DUTY CYCL E

The PWM duty cycle is specified by writing a 10-bit value

to multiple registers: CCPRxL register and DCxB<1:0>

bits of the CCPxCON register. The CCPRxL contains

the eight MSbs and the DCxB<1:0> bits of the

CCPxCON register contain the two LSbs. CCPRxL and

DCxB<1:0> bits of the CCPxCON register can be written

to at any time. The duty cycle value is not latched into

CCPRxH until after the period completes (i.e., a match

between PR2 and TMR2 registers occur s). While using

the PWM, the CCPRxH register is read-only.

Equation 15-2 is used to calculate the PWM pulse

width.

Equation 15-3 is used to c alc ul ate the PWM duty cy cl e

ratio.

EQUATION 15-2: PULSE WIDTH

EQUATION 15-3: DUTY CYCLE RATIO

The CCPRxH register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for glitchl ess PWM operation.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two bits

of the prescaler, to create the 10-bit time base. The

system clock is used if the T imer2 prescaler is set to 1:1.

When the 10-bit time base matches the CCPRxH and

2-bit latch, then the CCPx pin is cleared (refer to

Figure 15-3).

Note: The Timer2 postscaler (refer to

Section 13.1 “Timer2 Operation”) is not

used in the determination of the PWM

frequency.

PWM Period PR21+4TOSC =

(TMR2 Prescale Value)

Note: TOSC = 1/FOSC

Pulse Width CCPRxL:CCPxCON<5:4>



TOSC



(TMR2 Prescale Value)

Note: TOSC = 1/FOSC

Duty Cycle Ratio CCPRxL:CCPxCON<5:4>

4PR2 1+

-----------------------------------------------------------------------=

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15.3.4 PWM RESO LUTIO N

The res olution de termine s th e number of av ailable du ty

cycles for a given period. For example, a 10-bit resolution

will r e sult in 10 24 di sc ret e d ut y c ycl es , wh er eas an 8- b it

resol uti on wi ll re su lt in 2 56 di s cre te du ty c ycl es .

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 15-4.

EQUATION 15-4: PWM RESOLUTION

TABLE 15-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

TABLE 15-6: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

15.3.5 OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the mo dule will no t change . If the C CPx

pin is dri ving a value , it wi ll cont inue to d rive th at valu e.

When the device wakes up, TMR2 wil l continue from it s

previous state .

15.3.6 CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock fre-

quency will result in changes to the PWM frequency.

Refer to Section 7.0 “Oscillator Module” for

additional details.

15.3.7 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

15.3.8 SETUP F OR PWM OPERA T ION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCPx) output driver(s) by

setting the associated TRIS bit(s).

2. Load the PR2 register with the PWM period value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

4. Load the CCPRxL register and the DCxBx bits of

the CCPxCON register, with the PWM du ty cy cle

value.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the PIR1

• Configure the T2CKPS bits of the T2CON

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output pin:

• Wait until Timer2 overflows, TMR2IF bit of the

PIR1 register is set. See Note below.

• Enable the PWM pin (CCPx) output driver(s) by

clearing the associated TRIS bit(s).

Note: If the p ulse-wi d th va lue is greater th an the

period, the assigned PWM pin(s) will

remain unchanged.

Resolution 4PR2 1+log

2log

------------------------------------------ bits=

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.6

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09

Maximum Resol ution ( bits) 8 8 8 6 5 5

Note: In order to se nd a complete duty cycle and

period on the firs t PWM out put, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

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PIC16(L)F722/3/4/6/7

TABLE 15-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all ot her

Resets

ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu

CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu

PR2 Timer2 Period Register 1111 1111 1111 1111

T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

TMR2 Timer2 Module Register 0000 0000 0000 0000

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.

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16.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (AUSART)

The Addressable Universal Synchronous

Asynchronous Receiver Transmitter (AUSART)

module is a serial I/O communications peripheral. It

contains all the clock generators, shift registers and

data buffers necessary to perform an input or output

serial data transfer independent of device program

execution. The AUSART, also known as a Serial

Communications Int erface (S CI), can be co nfigured as

a full-duplex asynchronous system or half-duplex

synchronous system. Full-Duplex mode is useful for

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These device s typ icall y do n ot have inter nal cl ocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

The AUSART m odule includes the follow ing capabilities:

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

• One -ch arac ter out put buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

• Input buffer overrun error detection

• Received character framing error detection

• Hal f-du ple x sy nc hron ous master

• Hal f-du ple x sy nc hron ous slave

• Sleep operation

Block diagrams of the AUSART transmitter and

receiver are shown in Figure 16-1 and Figure 16-2.

FIGURE 16-1: AUSART TRA NSM IT BLOCK DIAGRAM

TXIF

TXIE

Interrupt

TXEN

TX9D

MSb LSb

Data Bus

TXREG Register

Transmit Shift Register (TSR)

(8) 0

TX9

TRMT SPEN

TX/CK

Pin Buffer

and Control

SPBRG

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 100

BRGH x10

Baud Rate Generator

•••

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FIGURE 16-2: AUSART RECEIVE BLOCK DIAGRAM

The operation of the AUSART module is controlled

through two registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

These registers are detailed in Register 16-1 and

RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR

FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt

RCIF

RCIE

Data Bus

Stop START

(8) 7 1 0

RX9

• • •

SPBRG

FOSC ÷ n

+ 1 Multiplier x4 x16 x64

SYNC 100

BRGH x10

Baud Rate Generato r

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16.1 AUSART Asynchronous Mode

The AUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL Space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output l evel of that bit wi thout returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark st ate. Each character

transmission consists of one Start bit follow ed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is 8 bits. Each transmitted bit persists for a period

of 1/(Baud Rate). An on-chip dedicated 8-bit Baud Rate

Generator is used to derive standard baud rate

frequencies from the system oscillator. Refer to

Table 16-5 for examples of baud rate Configurations.

The AUSART transmits and receives the LSb first. The

AUSART’s transmitter and receiver are functionally

indepen dent, but share th e sa me dat a format and bau d

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data b it.

16.1.1 AUSART ASYNCHRONOUS

TRANSMITTER

The AUSART transmitter block diagram is shown in

Figure 16-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXREG register.

16.1.1.1 Enabling the Transmitter

The AUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

•TXEN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXSTA r egister enables the

transmitter circuitry of the AUSART. Clearing the SYNC

bit of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCST A register enables the AUSART and automatically

configures the TX/CK I/O pin as an output.

16.1.1.2 Transmitting Data

A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXREG is then tran sferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the S tart bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXREG.

16.1.1.3 Transmit Interrupt Flag

The TXIF interrupt flag bit of the PIR1 register is set

whenever the AUSART transmitter is enabled and no

character is being held for transmission in the TXREG.

In other words, the TXIF bit is only clear when the TSR

is busy with a character and a new char acter ha s been

queued for transmission in the TXREG. The TXIF flag bit

is not cleared immediately upon writing TXREG. TXIF

becomes valid in the second instruction cycle following

the write execut ion. Polling TXIF immediately following

the TXREG write will return invalid results. The TXIF bit

is read-only, it cannot be set or cleared by software.

The TXIF interrupt can be enabled by setting the TXIE

interrupt enable bit of the PIE1 register. However, the

TXIF flag bit will be set whenever the TXREG is empty,

regardless of the state of TXIE enable bit.

To use interrupts when transmitting data, set the TXIE

bit only when there is more data to send. Clear the

TXIE i nterrupt en able bi t upon w riting the last charact er

of the transmission to the TXREG.

Note 1: When the SPEN bit is set the RX/DT I/O

pin is automatically configured as an input,

regardless of the state of the

corresponding TRIS bit and whether or not

the AUSART receiv er is enabled. The RX/

DT pin data can be read via a normal

PORT read bu t PORT latch d ata outpu t is

precluded.

2: The TXIF transmitter interrupt flag is set

when the TXEN enable bit is set.

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16.1.1.4 TSR Status

The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

16.1.1.5 Transmitting 9-Bit Characters

The AUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set the

AUSART will shift nine bits out for each character

transmitted. The TX9D bit of the TXSTA register is the

ninth, and Most Sign ifican t, dat a bit. When transmi tting

9-bit data, the TX9D data bit must be written before

writing the eight Least Significant bits into the TXREG.

All ni ne b its of data wi ll be tran sfe rred to t he T SR sh ift

A special 9-bit Address mode is available for use with

multiple receivers. Refer to Section 16.1.2.7 “Address

Detection” for more information on the Address mode.

16.1.1.6 Asynchronous T ransmission Set-up:

1. Initialize the SPBRG register and the BRGH bit to

achieve the desired baud rate (Refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the asynch ron ous seri al port by cle arin g

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the eight Least Significant data bits are an

address when the receiver is set for address

detection.

4. Enable the transmission by setting the TXEN

contr ol bit . Thi s wi ll c aus e th e TXI F i nte rrup t bi t

to be set.

5. If interrupts are desired, set the TXIE interrupt

enable bit of the PIE1 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

6. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

7. Load 8-bit data into the TXREG register. This

will start the transmission.

FIGURE 16-3: ASYNCHRONOUS TRANSMISSION

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1 Stop bit

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG Word 1

BRG Output

(Shift Clock)

TX/CK pin

TXIF bit

(Transmit Buffer

Empty Flag)

TRMT bit

(Tr an smi t Shi ft

Reg. Empty Flag)

1 TCY

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FIGURE 16-4: ASYNCHRON OUS TR ANSM IS SION (BACK-TO-BACK)

TABLE 16-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG AUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for As ynchr onous Transmission.

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

TX/CK pin

TRMT bit

(Transmit Shif t

Reg. Empty Flag)

Word 1 Wor d 2

Word 1 Word 2

Start bit Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

TXIF bit

(Transmit Buffer

Empty Flag)

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16.1.2 AUSART ASYNCHRONOUS

RECEIVER

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 16-2. The dat a is receiv ed on the RX/DT pin an d

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

or nine bits of the character have been shifted in, they

are immediately transferred to a two character First-In

First-Out (FIFO) memory. The FIFO buffering allows

receptio n of two complete cha rac ters and the s t art of a

third cha rac ter be fore software must start servicing th e

AUSART receiver. The FIFO and RSR registers are not

direc tly ac cessible b y s of tw a r e. Ac cess to the re ceived

data is via the RCREG register.

16.1.2.1 Enabling the Receiver

The AUSART receiver is enabled for asynchronous

operatio n by configuring the fol lowing three control bits:

• CREN = 1

• SYNC = 0

• SPEN = 1

All other AUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCSTA register enables the

receiver circuitry of the AUSART. Clearing the SYNC bit

of the TXSTA register configures the AUSART for

asynchronous operation. Setting the SPEN bit of the

RCST A register enables the AUSART and automatically

configures the RX/DT I/O pin as an input.

16.1.2.2 Receiving Data

The receiver data recovery circuit initiates character

receptio n o n the fallin g edge of the first bit. The f irst bi t,

also known as the Start bit, is always a zero. The data

recovery circuit co unt s one-h alf bi t time to the c enter of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit c ounts a full bit time to the ce nter of the

next bit. The bit is then sampled by a majority detect

circuit and the resultin g ‘0’ or ‘1’ is shif ted into the RS R.

This repeats until all data bits have been sampled and

shif ted into the RSR. One final bit time is measured and

the le ve l samp le d . Thi s is th e St op bi t , wh ic h is alwa ys

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

charact er , otherwise th e framing error is c leared for thi s

character. Refer to Section 16.1.2.4 “Receive

Framing Error” for more information on framing

errors.

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the AUSART receive FIFO and the RCIF interrupt

flag bit of the PIR1 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCREG register.

16.1.2.3 Receive Interrupts

The RCIF interrupt flag bit of the PIR1 register is set

whenever the AUSAR T receiver i s enabled an d there is

an unread character in the receive FIFO. The RCIF

interrupt fla g bit is read-o nly, it canno t be s et or cleare d

by software.

RCIF interrupts are enabled by setting all of the

following bits:

• RCIE interrupt enable bit of the PIE1 register

• PEIE periphe ral interru pt enab le bit of the

INTCON register

• GIE global interrupt enable bit of the INTCON

The RCIF interrupt flag bit of the PIR1 register will be

set when there is an unread character in the FIFO,

regardless of the state of interrupt enable bits.

Note: When the SPEN bit is set the TX/CK I/O

pin is automatically configured as an

output, regardless of the state of the

corresponding TRIS bit and whether or

not the AUSART transmitter is enabled.

The PORT latch is disconnected from the

output dri ver so it is no t possible to use the

TX/CK pin as a general purpose output.

Note: If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. Refer to

Section 16.1.2.5 “Receive Overrun

Error” for more information on overrun

errors.

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16.1.2.4 Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indic ates t hat a St op bit was not seen at the ex pected

time. The framing error status is accessed via the

FERR bit of the RCSTA register. The FERR bit

represen ts the s ta tus o f the top u nread charac ter in the

receive FIFO. Therefore, the FERR bit must be read

before reading the R CREG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCSTA register which resets the AUSART.

Clearing the CREN bit of the RCSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

16.1.2.5 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be genera ted if a th ird charac ter , in it s

entirety , is receive d before the FIFO is accessed. When

this happens the OERR bit of the RCST A register is set.

The characters already in the FIFO buffer can be read

but no additional characters will be received until the

error is cleared. The error must be cleared by either

clearing the CREN bit of the RCSTA register or by

setting the AUSART by clearing the SPEN bit of the

RCSTA register.

16.1.2.6 Rec eivi ng 9- bit Chara cters

The AUS ART support s 9-bit c haracter rece ption. When

the RX9 bit of the RCSTA register is set the AUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth and Most Significant data bit of the top unread

charact er in the recei ve FIFO. When read ing 9- bit dat a

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

16.1.2. 7 Address Detec tion

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCSTA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

rece iv e FI F O bu ffe r, there by s et t i ng th e R CI F i nte r r up t

bit of the PIR1 register. All other characters will be

ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When u se r s of tware detec t s th e end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note: If all receive characters in the receive

FIFO hav e fram ing erro rs, repe ated rea ds

of the RCREG will not clear the FERR bit.

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16.1.2.8 Asynchronous Reception Set-up:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If in terrup ts ar e desire d, set the RCI E bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. If 9-bit reception is desired, set the RX9 bit.

5. Enable reception by setting the CREN bit.

6. The RCIF interrupt flag bit of the PIR1 register

will be set when a character is transferred from

the RSR to the receive buffer . An inter rupt will be

generated if the RCIE bit of the PIE1 register

was also set.

7. Read the RCSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data b it.

8. Get the received eig ht Least Significant data bit s

from the receive buffer by reading the RCREG

9. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

16.1.2.9 9-bit Address Detection Mode Set-up

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

3. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

4. Enable 9-bit reception by setting the RX9 bit.

5. Enable addr ess dete ction by s etting the ADDEN

bit.

6. Enable reception by setting the CREN bit.

7. The RCIF interrupt flag bit of the PIR1 register

will be set whe n a chara cter with t he nin th bit s et

is transferred from the RSR to the receive buffer .

An interrupt will be generated if the RCIE inter-

rupt enabl e bit of th e PIE1 regi ster w as also se t.

8. Read th e RC STA regi ste r to get the erro r f lags.

The ninth data bit will always be set.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCREG

device’s address.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 16-5: ASYNCHRONOUS RECEPTION

Start

bit bit 7/8

bit 1bit 0 bi t 7/8 bit 0Stop

bit

Start

bit Start

bit

bit 7/8 Stop

bit

RX/DT pin

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG Word 2

RCREG

Stop

bit

Note: This timin g diagram sho ws three words appearing on the RX input. The RCREG (receive buffer) is r ead after the third word,

causing the OERR (overrun) bit to be set.

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TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCREG AUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.

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R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: AUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 Unimplemented: Read as ‘0’

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode

bit 1 TRMT: Transmit Shift Registe r Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: Ninth bit of Transmit Data

Can be ad dress/d ata bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Synchronous mode.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit(1)

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1 = En ables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care

bit 4 CREN: Conti nuo us Rec eive Enable bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Don’t care

Synchronous mode:

Must be set to ‘0’

bit 2 FERR: Framing Error bit

1 = Framing error (can be update d by reading RCREG regi ster and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure

TRISx = 1.

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16.2 AUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit timer that

is dedicated to the support of both the asynchronous

and synchronous AUSART operation.

The SPBRG register determines the period of the free

running baud rate timer. In Asynchronous mode the

multiplier of the baud rate period is determined by the

BRGH bit of the TXSTA register. In Synchronous mode,

the BRGH bit is ignored.

Table 16-3 contains the formulas for determining the

baud rate . Example 16-1 provides a s ample calcul ation

for determining the baud rate and baud rate error.

Typical baud rates and error values for various

asynchronous modes have been computed for your

convenience and are shown in Table 16-3. It may be

advant ageous to use the high baud rate (BRG H = 1), to

reduce the baud rate error.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures that

the BRG does not wait for a timer overflow before

outputting the new baud rate.

EXAMPLE 16-1: CALCULATING B AUD

RATE ERROR

TABLE 16-3: BAUD RATE FORMULAS

TABLE 16-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

For a device with FOSC of 16 MHz, desired baud rate of

9600, and A synchronous m ode with SY NC = 0 and BRGH

= 0 (as seen in Table 16-3):

Sol vi n g fo r SPBR G:

SPBRG FOSC

64 Desired Baud Rate

---------------------------------------------------------





1–=

Desired Baud Rate FOSC

64 SPBRG 1+

---------------------------------------=

16000000

64 9600

------------------------





1–=

25.04225==

Actual Baud Rate 16000000

64 25 1+

---------------------------=

9615=

Error Actual Baud Rate Desired Baud Rate –

Desired Baud Rate

--------------------------------------------------------------------------------------------------





100=

9615 9600–

9600

------------------------------





100 0.16%==

Configur ation Bits AUSART Mode Baud Rate Formula

SYNC BRGH

00 Asynchronous FOSC/[64 (n+1)]

01 Asynchronous FOSC/[16 (n+1)]

1x Synchronous FOSC/[4 (n+1)]

Legend: x = D on’t care, n = value of SPBRG register

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Value on

all other

Resets

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.

PIC16(L)F722/3/4/6/7

DS40001341F-page 150  2007-2015 Microchip Technology Inc.

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

SYNC = 0, BRGH = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 — — — — — — —— — —— —

1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143

2400 2404 0.16 129 2400 0.00 119 2403 0.16 103 2400 0.00 71

9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17

10417 10417 0.00 29 10286 -1.26 27 10416 -0.01 23 10165 -2.42 16

19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8

57.6k — — — 57.60k 0.00 7—— —

57.60k 0.00 2

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 0

FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 — — — 300 0.16 207 300 0.00 191 300 0.16 51

1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12

2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —

9600 9615 0.16 12 — — — 9600 0.00 5 — — —

10417 10417 0.00 11 10417 0.00 5 — — — — — —

19.2k — — — — — — 19.20k 0.00 2 — — —

57.6k — — — — — — 57.60k 0.00 0 — — —

115.2k — — — — — — — — — — — —

BAUD

RATE

SYNC = 0, BRGH = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.0000 MHz FOSC = 11.0592 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 —— — —— — —— — —— —

1200 — — — — — — — — — — — —

2400 — — — — — — — — — —— —

9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71

10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65

19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35

57.6k 56.82k -1.36 21 57.60k 0.00 19 58.8k 2.12 16 57.60k 0.00 11

115.2k 113.64k -1.36 10 115.2k 0.00 9 — — — 115.2k 0.00 5

 2007-2015 Microchip Technology Inc. DS40001341F-page 151

PIC16(L)F722/3/4/6/7

BAUD

RATE

SYNC = 0, BRGH = 1

FOSC = 8.000 MHz FOSC = 4.000 MHz F OSC = 3.6864 MHz FOSC = 1.000 MHz

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

Actual

Rate %

Error

SPBRG

value

(decimal)

300 —— — — — — — — — 300 0.16 207

1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51

2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25

9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —

10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5

19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —

57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —

115.2k — — — — — — 115.2k 0.00 1 — — —

TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES

PIC16(L)F722/3/4/6/7

DS40001341F-page 152  2007-2015 Microchip Technology Inc.

16.3 AUSART Synchronous Mode

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary cir-

cuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The AUSART can operate as either a master or slave

device.

Start and Stop bits are not used in synchronous

transmissions.

16.3.1 SYNCHRONOUS MASTER MODE

The following bits are used to configure the AUSART

for Synchronous Master operation:

• SYNC = 1

• CSRC = 1

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures

the de vi c e f or sy n ch ronous op era ti on . Se tting the CS RC

bit of the TXSTA register configures the device as a

master. Clearing the SREN and CREN bits of the RCST A

regis ter ensures that the d ev ice i s in the T ra ns m it mo de,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

16.3.1.1 Master Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device

configured as a master transmits the clock on the TX/

CK line. The TX/CK pin output driver is automatically

enabled when the AUSART is configured for

synchronous transmit or receive operation. Serial data

bits change on the leading edge to ensure they are

valid at th e trai ling edg e of each clock . One cl ock cy cle

is generated for each data bit. Only as many clock

cycles are generated as there are data bits.

16.3.1.2 Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are

automat ically e nabled w hen the AUSAR T is configure d

for synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXREG reg is ter. If the TSR still cont a ins al l or part of a

previous character, the new character data is held in

the TXREG until the last bit of the previous character

has been tran smitted. If this is the first ch aracter, or the

previous character has been completely flushed from

the TSR, the data in the TXREG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXREG.

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

16.3.1.3 Synchronous Master Transmission

Setup:

1. Initialize the SPBRG register and the BRGH bit

to achieve the desired baud rate (refer to

Section 16.2 “AUSART Baud Rate Generator

(BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. Disable Receive mode by clearing bits SREN

and CREN.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading dat a to the TXREG

Note: The TSR register is not mapped in data

memory, so it is not available to the user.

 2007-2015 Microchip Technology Inc. DS40001341F-page 153

PIC16(L)F722/3/4/6/7

FIGURE 16-6: SYNCHRONOUS TRANSMISSION

FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 16-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG AUSART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.

bit 0 bit 1 bit 7

Word 1 bit 2 bit 0 bit 1 bit 7

RX/DT

Write to

TXREG Reg

TXIF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT b it

Write Word 1 Write Word 2

Note: Synchronous M ast er mode, SPBRG = 0, continuous transmission of two 8-bit words.

TX/CK pin

RX/DT pin

TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bi t

PIC16(L)F722/3/4/6/7

DS40001341F-page 154  2007-2015 Microchip Technology Inc.

16.3.1.4 Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

AUSAR T is config ured fo r synch ronous master receiv e

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCSTA register) or the Continuous Receive Enable bit

(CREN of the RCSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character . The SREN bit is automatically cleared

at the com pletio n of one c har acter. When CREN is set,

clocks are continuously generated until CREN is

cleared . If CREN is cleared in the middle of a c haracter

the CK clo ck sto p s imm ed iat ely and t he p a rtia l charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cl eared at the co mpletion of the first cha racter

and CREN takes precedence.

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

receive d into the RSR, t he RCIF bit of the PIR1 reg ister

is set and the character is automatically transferred to

the two character receive FIFO. The Least Significant

eight bits of the top character in the receive FIFO are

available in RCREG. The RCIF bit remains set as long

as there are unread characters in the receive FIFO.

16.3.1.5 Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous wi th the data. A device configured

as a slave receives the cloc k on the TX/CK line . The TX/

CK pin output driver is automatically disabled when the

device is configured for synchronous slave transmit or

receive operation. Serial dat a bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One data bit is transferred for each clock cycle.

Only as many clock cycles should be received as there

are data bits.

16.3.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be genera ted if a th ird charac ter , in it s

entirety, is received before RCREG is read to access

the FIFO. When this happens the OERR bit of the

RCSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be recei ved until the erro r is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCSTA register.

16.3.1.7 Receiving 9-bit Characters

The AUSAR T support s 9-bit chara cter receptio n. When

the RX9 bit of the RCSTA register is set, the AUSART

will shift 9-bits into the RSR for each character

received. The RX9D bit of the RCSTA register is the

ninth, and Most Significant, data bit of the top unread

charact er i n t he rec eiv e FIFO . Whe n r ead ing 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCREG.

Address detection in Synchronous modes is not

supported, therefore, the ADDEN bit of the RCSTA

16.3.1.8 Synchronous Master Reception

Setup:

1. Initialize the SPBRG re gis ter for the appropria te

baud rate. Set or clear the BRGH bit, as

required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit reception is desired, set bit RX9.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

8. Interrupt flag bi t RCIF of the PIR 1 register wil l be

set when reception of a character is complete.

An interrupt will be generated if the RCIE

interr upt en abl e bit of the PIE1 regi ster was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

resets the AUSART.

 2007-2015 Microchip Technology Inc. DS40001341F-page 155

PIC16(L)F722/3/4/6/7

FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCREG AUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

CREN bit

RX/DT

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RCREG

‘0’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘0’

Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.

TX/CK pin

PIC16(L)F722/3/4/6/7

DS40001341F-page 156  2007-2015 Microchip Technology Inc.

16.3.2 SYNCHRONOUS SLAVE MODE

The following bits are used to configure the AUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit

of the TX STA regist er configures t he device as a sl ave.

Clearing the SREN and CREN bits of the RCST A register

ensures that the device is in the Transmit mode,

otherwise the device will be configured to receive. Setting

the SPEN bit of the RCSTA register enables the

AUSART.

16.3.2.1 AUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes are identical (refer to Section 16.3.1.2

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

2. The second wo rd will remai n in TXREG r egister.

3. The TXIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXREG register will transfer the second

character to the TSR and the TXIF bit will now be

set.

5. If the PEIE and TXIE bits are set, the interrupt

will wa ke the dev ice from Sleep and e xecute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

16.3.2.2 Synchronous Slave Transmission

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the CREN and SREN bits.

3. If using interrupt s, ensure tha t the GIE and PEIE

bits of the INTCON register are set and set the

TXIE bit.

4. If 9-bit transmission is desired, set the TX9 bit.

5. Enable transmission by setting the TXEN bit.

6. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant eight bits to the TXREG register.

TABLE 16-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXREG AUS ART Transmit Data Register 0000 0000 0000 0000

TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.

 2007-2015 Microchip Technology Inc. DS40001341F-page 157

PIC16(L)F722/3/4/6/7

16.3.2.3 AUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 16.3.1.4 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

nev er Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is rec eived, th e RSR regist er will tran sfer the da ta

to the RCREG register. If the RCIE interrupt enable bit

of the PIE1 register is set, the interrupt generated will

wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

16.3.2.4 Synchronous Slave Reception

Setup:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. If 9-bit reception is desired, set the RX9 bit.

4. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

5. Set the CREN bit to enable reception.

6. The RCIF bit of the PIR1 register will be set

when re ce pt io n i s co mp le te . An i n t err u pt will be

generated if the RCIE bit of the PIE1 register

was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

8. Retrieve the eig ht L east Si gnific ant bi ts from th e

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Valu e on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCREG AUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000X 0000 000X

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.

PIC16(L)F722/3/4/6/7

DS40001341F-page 158  2007-2015 Microchip Technology Inc.

16.4 AUSART Operation During Sleep

The AUSAR T will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the

necessary signals to run the Transmit or Receive Shift

registers during Sleep.

Synchronous Slave mode uses an external ly generated

clock to run the Transmit and R eceive Shift registers.

16.4.1 SYNCHRONOUS RECEIVE DURING

SLEEP

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Reception

(refer to Section 16.3.2.4 “Synchronous Slave

Reception Setup:”).

• If interrupts are d esired, s et the RCI E bit of the

PIE 1 regi ster and th e PEIE bit of the INTCON

• The RCIF interrupt flag must be cleared by

reading RCREG to unload any pending

characters in the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been c om ple tel y

clocked in by the external device, the RCIF interrupt

flag bi t of th e PIR1 regis ter will be s et. The reb y, wakin g

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE global

interrupt enable bit of the INTCON register is also set,

then the Interrupt Service Routine at address 0004h

will be called.

16.4.2 SYNCHRONOUS TRANSMIT

DURING SLEEP

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCSTA and TXSTA Control registers must be

configured for Synchronous Slave Transmission

(refer to Section 16.3.2.2 “Synchronous Slave

Transmission Setup:”).

• The TXIF interrup t fl ag must be c lea red by wr it ing

the output data to the TXREG, thereby filling the

TSR and transmit buffer.

• If interrupts are desired, set the TXIE bit of the

PIE1 register and the PEIE bit of the INTCON

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXREG will transfer to the TSR and

the TXIF flag will be set. Thereby, waking the processor

from Sleep. At this point, the TXREG is available to

accept another character for transmission, which will

clear the TXIF flag.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the GIE global

interrupt enable bit is also set th en the Interrupt Service

Routine at address 0004h will be called.

 2007-2015 Microchip Technology Inc. DS40001341F-page 159

PIC16(L)F722/3/4/6/7

17.0 SSP MODULE OVERVIEW

The Synchronous Serial Port (SSP) module is a serial

interface useful for communicating with other

peripherals or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift

module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C)

17.1 SPI Mode

The SPI mode allows eight bits of data to be

synchronously transmitted and received,

simultaneously. The SSP module can be operated in

one of two SPI mo des:

• Master mode

• Slave mode

SPI is a full-duplex protocol, with all communication

being bidirectional and initiated by a mast er device. All

clocking is provided by the master device and all bits

are transmitted, MSb first. Care must be taken to

ensure that all devices on the SPI bus are setup to

allow all controllers to send and receive data at the

same time.

A typical SPI connection between microcontroller

devices is shown in Figure 17-1. Addressing of more

than one slave device is accomplished via multiple

hardware slave select lines. External hardware and

additional I/O pins must be used to support multiple

slave select addressing. This prevents extra overhead

in software for communication.

For SPI communication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Seri al Clock (SCK)

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS)

FIGURE 17-1: TYPICAL SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

Processor 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buf fe r

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

Processor 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

Slave Select

General I/O (optional)

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FIGURE 17-2: SPI MODE BLOCK

DIAGRAM

Read Write

Internal

Data Bus

SDI

SDO

RA5/SS

SCK

SSPSR Reg

SSPBUF Reg

SSPM<3:0>

bit 0 Shift

Clock

Control

Enable

Edge

Select

Clock Select

TMR2

FOSC

Prescaler

4, 16, 64

TRISx

RA0/SS SSSEL

Output

2

Edge

Select

bit 7

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17.1.1 MASTER MODE

In Master mode, data transfer can be initiated at any

time bec ause the master contro ls th e SCK line. Mas ter

mode determines when the slave (Figure 17-1,

Processor 2 ) transmit s d at a via control of the SC K lin e.

17.1.1.1 Master Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

first. The SSPBUF regis ter hold s the d ata t hat is wr itten

out of the master until the received data is ready. Once

the eight bits of data have been received, the byte is

moved to the SSPBUF register. The Buffer Full Status

bit, BF of the SSPSTAT register, and the SSP Interrupt

Flag bi t, SSP IF of the PIR1 reg is te r, are then set.

Any write to the SSPBUF register during

transmission/reception of data will be ignored and the

Write Collision Detect bit, WCOL of the SSPCON

bit so that it can be determined if the following write(s)

to the SSPBUF register completed successfully.

When the application software is expecting to receive

valid da ta, the SSPBUF shoul d be read before th e next

byte of d ata is written to the SSPBUF. The BF bit of the

SSPSTAT register is set when SSPBUF has been

loaded with the received data (transmission is

complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. The SSP interrupt may be used to

determine when the transmission/reception is

complete and the SSPBUF must be read and/or

written. If interrupts are not used, then software polling

can be done to ensure that a write collision does not

occur. Example 17-1 shows the loa ding of the SSPBUF

(SSPSR) for data transmission.

17.1.1.2 Enabling Master I/O

To enable the serial port, the SSPEN bit of the

SSPCON register, must be set. To reset or reconfigu re

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON register and then set the SSPEN bit. If a

Master mode of operation is selected in the SSPM bit s

of the SSPCON register, the SDI, SDO and SCK pins

will be assigned as serial por t pins.

For thes e pi ns to function as serial p ort pi ns, they must

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO conf igu red as output

• SCK configured as output

17.1.1. 3 Master Mod e Setup

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is loaded with a byte

value. If the mast er is only going to receive, SDO out put

could be disabled (programmed and used as an input).

The SSPSR register will continue to shift in the signal

present on the SDI pin at the programmed clock rate.

When initializing SPI Master mode operation, several

options need to be specified. This is accomplished by

programming the appropriate control bits in the

SSPCON and SSPSTAT registers. These control bits

allow the following to be specified:

• SCK as clock output

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

• Clock bit rate

In Master mode, the SPI clock rate (bit rate) is user

selectable to be one of the following:

•F

OSC/4 (or TCY)

•F

OSC/16 (or 4  TCY)

•FOSC/64 (or 16  TCY)

• (Timer2 output)/2

This allows a maximum data rate of 5 Mbps

(at FOSC =20MHz).

Figure 17-3 shows the waveforms for Master mode.

The clock polarity is selected by appropriately program-

ming the CKP bit of the SSPCON register. When the

CKE bit is set, the SDO data is valid before there is a

clock edge on SCK. The sample time of the input data

is shown based on the state of the SMP bit and can

occur at the middle or end of the data output time. The

time when the SSPBUF is loaded with the received

dat a is shown.

17.1.1.4 Sleep in Master Mode

In Master mode, all module clocks are halted and the

transmission/reception will remain in the ir current state,

paused, until the device wakes from Sleep. After the

device wakes up from Sleep, the module will continue

to transmit/receive data.

Note: The SSPSR is not directly readable or

writable and can only be accessed by

addressing the SSPBUF register.

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FIGURE 17-3: SPI MASTER MODE WAVEFORM

EXAMPLE 17-1: LOADING THE SSPBUF (SSPSR) REGISTER

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7 bit 0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

BANKSEL SSPSTAT ;

LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?

GOTO LOOP ;No

BANKSEL SSPBUF ;

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

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17.1.2 SLAVE MODE

For any SPI device acting as a slave, the data is

transmitted and received as external clock pulses

appear on SCK pin. This external clock must meet the

minimum high and low times as specified in the

electrical specifications.

17.1.2.1 Slave Mode Operation

The SSP consists of a transmit/receive shift register

(SSPSR) and a buf fer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data i s ready.

The slave has no control as to when data will be

clocked in or out of the device. All data that is to be

transmitted, to a master or another slave, must be

loaded into the SSPBUF register before the first clock

pulse is received.

Once eight bits of data have been received:

• Received byte is moved to the SSPBUF register

• BF bit of the SSPSTAT register is set

• SSPIF bit of the PIR1 register is set

Any write to the SSPBUF register during

transmission/reception of data will be ignored and the

Write Collision Detect bit, WCOL of the SSPCON

WCOL bit so that it can be determined if the following

write(s) to the SSPBUF register completed

successfully.

The user’s firmware must read SSPBUF, clearing the

BF flag, or the SSPOV bit of the SSPCON register will

be set with the reception of the next byte and

communication will be disabled.

A SPI module tran smit s and rece ives at the sa me time,

occasionally causing dummy data to be

transmitted/received. It is up to the user to determine

which data is to be used and what can be discarded.

17.1.2.2 Enabling Slave I/O

To enable the serial port, the SSPEN bit of the

SSPCON register must be set. If a Slave mode of

operatio n is selec ted i n the SSPM bits of the SSPCON

serial port pins.

For thes e pi ns to function as s eri al p ort pin s, th ey m us t

have their corresponding data direction bits set or

cleared in the associated TRIS register as follows:

• SDI configured as input

• SDO configured as output

• SCK configured as input

Optionally, a fourth pin, Slave Select (SS ) may be used

in Slave mode. Slave Select may be configured to

operate on one of the following pins via the SSSEL bit in

the APFCON register.

•RA5/AN4/SS

•RA0/AN0/SS

Upon selection of a Slave Select pin, the appropriate

bits must be set in the ANSELA and TRISA registers.

Slave Select must be set as an input by setting the

corresponding bit in TRISA, and digital I/O must be

enabled on the SS pin by clearing the corresponding bit

of the ANSELA register.

17.1.2.3 Slave Mode Setup

When initializing the SSP module to SPI Slave mode,

compati bility must be ensure d with the ma ster de vice.

This is done by programming the appropriate control

bits of the SSPCON and SSPSTAT registers. These

control bits allow the following to be specifi ed:

• SCK as clock input

• Idle state of SCK (CKP bit)

• Data input sample phase (SMP bit)

• Output data on rising/falling edge of SCK (CKE bit)

Figure 17-4 and Figure 17-5 show exam ple wavefo rms

of Slave mode operation.

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FIGURE 17-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Optional

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Not Optional

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17.1.2.4 Slave Select Operation

The SS pin allows Synchronous Slave mode operation.

The SPI must be in Slave mode with SS pin control

enabled (SSPM<3:0> = 0100). The associated TRIS bit

for the SS pin must be set, making SS an input.

In Slave Select mode, when:

•SS

= 0, The device operates as s pecified in

Section 17.1.2 “Slave Mode”.

•SS

= 1, The SPI module is held in Reset and the

SDO pin will be tri-stated.

When the SPI m od ul e re sets, the bi t c oun ter i s cl eare d

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit. Figure 17-6

shows the timing waveform for such a synchronization

event.

17.1.2.5 Sleep in Slave Mode

While in Sleep mode, the slave can transmit/receive

data. The SPI Transmit/Recei ve Sh ift regi ste r o pe rate s

asynchronously to the device on the externally supplie d

clock source. This allows the device to be placed in

Sleep mode and data to be shifted into the SPI Trans-

mit/Receive Shift register. When all eight bits have

been received, the SSP Interrup t Flag bit will be set and

if enabled, will wake the device from Sleep.

FIGURE 17-6: SLAVE SELECT SYNCHRONIZATION W A VEFORM

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPM<3:0> = 0100),

the SPI module will reset if the SS pin is

driven high.

2: If the SPI is used in Slave mode with CKE

set, the SS pin control must be enabled.

Note: SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO b it 7 bit 6 bit 7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7 bit 0

SSPSR must be reinitialized by writing to

the SSPBUF register before the data can

be clocked out of the slave again.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the

overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPBUF register.

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1)

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clo ck Polar ity Select bit

1 = Idle stat e for clock is a high l evel

0 = Idle state for clock i s a low level

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4

0001 = SPI Master mode, clock = FOSC/16

0010 = SPI Master mode, clock = FOSC/64

0011 = SPI Master mode, clock = TMR2 output/2

0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pi n.

Note 1: When enabled, these pins must be properly configured as input or output.

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R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: SPI Data Input Sample Phase bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SP I is used in Slav e mode

bit 6 CKE: SPI Clock Edge Select bit

SPI mode, CKP = 0:

1 = Data stable on rising edge of SCK

0 = Data stable on falling edge of SCK

SPI mode, CKP = 1:

1 = Data stable on falling edge of SCK

0 = Data stable on rising edge of SCK

bit 5 D/A: Da ta/Address bit

Used in I2C mode only.

bit 4 P: Stop bit

Used in I2C mode only.

bit 3 S: Start bit

Used in I2C mode only.

bit 2 R/W: Read /W ri te Information b i t

Used in I2C mode only.

bit 1 UA: Update Address bit

Used in I2C mode only.

bit 0 BF: Buffer Full Status bit

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

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TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

othe r Resets

ANSELA ——ANSA5ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 --11 1111 --11 1111

APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PR2 Timer2 Period Register 1111 1111 1111 1111

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

T2CON —TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.

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17.2 I2C Mode

The SSP module, in I2C mode, implements all slave

functions, except general call support. It provides

inter rupts on S ta rt and S top bit s in hardware to fac ilitate

firmwa re im ple me nt ations of the mast er func tio ns . The

SSP module implements the I2C Standard mode

specifications:

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

• Start and Stop bit interrupts enabled to support

firmware Master mode

•Address masking

Two pins are used for d at a tra nsfer; the SCL pin (clock

line) and the SDA pin (data line). The user must

configure the two pin’s data direction bits as inputs in

the appropriate TRIS register. Upon enabling I2C

mode, the I2C slew rate limiters in the I/O pads are

controlled by the SMP bit of SSPSTAT register. The

SSP module functions are enabled by setting the

SSPEN bit of SSPCON register.

Data is sampled on the rising edge and shifted out on

the fallin g edge of the cloc k. This ensu res that the SDA

signal is va lid dur ing the SCL hi gh tim e. The SC L cl ock

input must have minimum high and low times for proper

operation. Refer to Section 23.0 “Electrical

Specifications”.

FIGURE 17-7: I2C MODE BLOCK

DIAGRAM

FIGURE 17-8: TYPICAL I2C

CONNECTIONS

The SSP module has six registers for I2C operation.

They are:

• SSP Control (SSPCON) register

• SSP Status (SSPSTAT) register

• Serial Receive/Transmit Buffer (SSPBUF) register

• SSP Shift Register (SSPSR), not directly

accessible

• SSP Address (SSPADD) register

• SSP Address Mask (SSPMSK) register

17.2.1 HARDWARE SETUP

Selection of I2C mode, with the SSPEN bit of the

SSPCON register set, fo rces th e SCL an d SDA pi ns to

be open d rain, p rovided th ese pins are programme d as

inputs by setting the appropriate TRISC bits. The SSP

module will override the input state with the output dat a,

when required, such as for Acknowledge and

slave-transmitter sequences.

Read Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Det ect

SSPBUF Reg

Internal

Data Bus

Addr Match

SCL

SDA

Shift

Clock

MSb LSb

SSPMSK Reg

Note: Pull-up resistors must be provided

externally to the SCL and SDA pins for

proper operation of the I2C module

Slave 1

Master

SDA

SCL

VDD VDD

SDA

SCL

Slave 2

SDA

SCL

(optional)

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17.2.2 START AND STOP CONDITIONS

During times of no data transfer (Idle time), both the

clock l ine (SCL ) and th e dat a line (SDA) are pulled high

through external pull-up resistors. The Start and Stop

conditions determine the start and stop of data trans-

missi on. Th e Star t c on dit ion is d efi ned as a high-to-low

transition of the SDA line while SCL is high. The Stop

condition is defined as a low-to-high transition of the

SDA line while SCL is high.

Figure 17-9 shows the Start and Stop conditions. A

master device generates these conditions for starting

and terminating data transfer. Due to the definition of

the Start and Stop conditions, when data is being

transmitted, the SDA line can only change state when

the SCL line is low.

17.2.3 ACKNOWLEDGE

After the valid reception of an address or data byte, the

hardware automatically will generate the Acknowledge

(ACK) pulse and load the SSPBUF register with the

received value currently in the SSPSR register. There

are certain conditions that will cause the SSP module

not to generate this ACK pulse. They include any or all

of the following:

• The Buffer Full bit, BF of the SSPSTAT register,

was set before the transfer was received.

• The SSP O verflow bit, SSPOV of the SSPCON

• The SSP Module is being operated in Firmware

Master mode .

In such a case, th e SSPSR regi ster value is no t loade d

into the SSPBUF, but bit SSPIF of the PIR1 register is

set. Table 17-2 shows the results of when a data

transfer byte is receiv ed, given the statu s of bits BF and

SSPOV. Flag bit BF is cleared by reading the SSPBUF

FIGURE 17-9: START AND STOP CONDITIONS

TABLE 17-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received SSPSR  SSPBUF Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Yes Yes

10 No No Yes

11 No No Yes

0 1 No No Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

SDA

SCL P

Stop

Condition

Start

Condition

Change of

Data Allowed

Change of

Data Allowed

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17.2.4 ADDRESSING

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the eight bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock line (SCL).

17.2.4.1 7-bit Addressing

In 7-bit Addressing mode (Figure 17-10), the value of

the falling edge of the eighth clock (SCL) pulse. If the

addresses match, and the BF and SSPOV bits are

clear, the following events occur:

• The SSPSR register value is loaded into the

SSPBUF register.

• The BF bit is set.

•An ACK

pulse is generated.

• SSP interrupt flag bit, SSPIF of the PIR1 register,

is set (interrupt is generated if enabled) on the

falling edge of the ninth SCL pulse.

17.2.4.2 10-bit Addressing

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 17-11). The five Most

Significant bits (MSbs) of the first address byte specify

if it is a 10-bit address. The R/W bit of the SSPSTAT

receive the se co nd ad dres s byte. Fo r a 1 0-bi t a ddress,

the first byte would equal ‘1111 0 A9 A8 0’, wh ere

A9 and A8 are the two MSbs of the address.

The sequ ence of e vents for 10-bit a ddress is as follows

for reception:

1. Load SSP ADD register with high byte of address.

2. Receive first (high) byte of address (bits SSPIF,

BF and UA of the SSPSTAT register are set).

3. Read the SSPBUF register (clears bit BF).

4. Clear the SSPIF flag bit.

5. Update the SSPADD register with second (low)

byte of address (clears UA bit and releases the

SCL line).

6. Receive low byte of address (bits SSPIF, BF and

UA are set).

7. Update the SSPADD register with the high byte

of address. If match releases SCL line, this will

clear bit UA.

8. Read the SSPBUF register (clears bit BF).

9. Clear flag bit SSPIF.

If data is requested by the master, once the slave has

been addressed:

1. Receive repeated Start condition.

2. Receive repeat of high byte address with

R/W =1, indicat ing a r ead.

3. BF bit is set and th e CKP bit is cl eared, stop ping

SCL and indicating a read request.

4. SSPBUF is written, setting BF, with the data to

send to the master device.

5. CKP is set in software, releasing the SCL line.

17.2.4. 3 Addres s Mask ing

The Address Masking register (SSPMSK) is only

accessible while the SSPM bits of the SSPCON

select which bits of a received address the hardware

will compare when determining an address match. Any

bit that is set to a zero in the SSPMSK register, the

corresponding bit in the received address byte and

SSPADD register are ignored when determining an

address match. By default, the register is set to all

ones, requiring a complete match of a 7-bit address or

the lower eight bits of a 10-bit address.

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17.2.5 RECEPTION

When th e R/W bit of the rece ived addres s byte is clear,

the master will write data to the slave. If an address

match occurs, the received address is loaded into the

SSPBUF register. An address byte overflow will occur

if that loaded address is not read from the SSPBUF

before the next complete byte is received.

An SSP interrupt is generated for each data transfer byte.

The BF, R /W and D/A bits of the SSPSTAT register are

used to determine th e status of the la st re ce iv ed byte.

FIGURE 17-10 : I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

765

D5D6

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 12345678912345678912

Bus Master

sends Stop

condition

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK Receiving Data

Receiving Data D0

D3D4D5D6

ACK

R/W = 0

Receiving Address

SSPIF

SSPOV

ACK

ACK is not sent.

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FIGURE 17-11: I2C SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)

SSPIF

Receive Data Byte

R/W

Receive First Byte of Address

Cleared in softwa re

Cleared in software

Receive Second Byte of Address

Cleared by har dwar e

when SSPADD is updated

with low byte of address

Clock is held low until

update of SSPADD has

taken place

UA is set indicating

that the SSPADD needs to

be updated

UA is set indicating

that SSPA DD needs to

be updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written

with contents of SSPSR Dummy read of SSPBUF

to clear BF flag

CKP

Receive Data Byte

Bus master

sends Stop

condition

ACK

Cleared in software Cleared in software

SSPOV

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

Clock is held low until

update of SSPADD has

taken plac e

SDA

SCL S123456789 123456789 12345 789P

11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D1 D0

ACK

ACK D2

ACK

12345789

D7 D6 D5 D4 D3 D1 D0D2

ACK

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17.2.6 TRANSMISSION

When the R/W bit of the received address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set and the slave will respond to

the master by reading out data. After the address match,

an ACK pulse is generated by the slave ha rdware and

the SCL pin is held low (clock is automatically stretched)

until the slave is ready to respond. See Section 17.2.7

“Clock Stretching”. The data the slave will transmit

must be loaded into the SSPBUF register, which sets

the BF bit. The SCL line is released by setting the CKP

bit of the SSPCON register .

An SSP interru pt is generated for e ach transferred da ta

byte. The SSPIF flag bit of the PIR1 regi ster initiates an

SSP interrupt, and must be cleared by software before

the nex t byte is transmi tted. The BF bi t of the SSPSTA T

received clock pulse. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

Following the eighth falling clock edge, control of the

SDA line is released back to the master so that the

master can acknowledge or not acknowledge the

response. If the master sends a not acknowledge, the

slave’s transmission is complete and the slave must

monitor for the next Start condition. If the master

acknowledges, control of the bus is returned to the

slave to transmi t another byt e of data. Just as with the

previous b yte, t he clo ck is st retched b y the slave, data

must be loaded into the SSPBUF and CKP must be set

to release the clock line (SCL).

FIGURE 17-12 : I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF

CKP

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

Transmitting DataR/WReceiving Address

123456789 123456789 P

Cleared in software

Set bit after writing to SSPBUF

SData in

sampled SCL held low

while CPU

responds to SSPIF

(the SSPBUF must be written to

before the CKP bit can be set)

Dummy read of SSPBUF

to clear BF flag SSPBUF is written in software From SSP Interrupt

Servi ce Routine

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PIC16(L)F722/3/4/6/7

FIGURE 17-13 : I2C SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS)

SDA

SCL

SSPIF

S123456789 123456789 12345 789 P

11110A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11110 A8

R/W = 1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus Master

sends S top

condition

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address.

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address.

SSPBUF is written with

contents of SSPSR Dummy read of SSPBUF

to clear BF flag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Transmitting Data Byte

Dummy read of SSPBUF

to clear BF flag

Cleared in software

Write of SSPBUF

Cleared in software

Completion of

clears BF flag

CKP

CKP is set in software, initiates transmission

CKP is automatically cleared in hardware holding SCL low

Clock is held low until

update of SSPADD has

taken place

data transmission

Clock is held low until

CKP is set to ‘1’

Bus Master

sends Restarts

condition

Dummy read of SSPBUF

to clear BF flag

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17.2.7 CLOCK STRETCHING

During any SCL low phase, any device on the I2C bus

may hold the SCL line low and delay, or pause, the

transmission of dat a. This “stretchi ng” of a transmission

allows devices to slow down communication on the

bus. The SCL line must be constantly sampled by the

master to ensure that all devices on the bus have

released SCL for more data.

Stretching usually occurs after an ACK bit of a

transmi ssio n, d el ayi ng the fi rst bit of th e n ext b yte. The

SSP module hardware automatically stretches for two

conditions:

• After a 10-bit address byte is received (update

SSPADD register)

• Anytime the CKP bit of the SSPCON register is

cleared by hardware

The module will hold SCL low until the CKP bit is set.

This all ows the use r slave so ftware to updat e SSPBUF

with data that may not be readily available. In 10-bit

addressing modes, the SSPADD register must be

updated after receiving the first and second address

bytes. The SSP module will hold the SCL line low until

the SSPADD has a byte written to it. The UA bit of the

SSPSTAT register will be set, along with SSPIF,

indicating an address update is needed.

17.2.8 FIRMWARE MASTER MODE

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits of

the SSPSTAT register are cleared from a Reset or

when the SSP module is disabled (SSPEN cleared).

The Stop (P) and Start (S) bits will toggle based on the

Start and Stop conditions. Control of the I2C bus may

be t aken when the P bit i s set or the bus is Idl e and both

the S and P bits are clear.

In Firmware Master mode, the SCL and SDA lines are

manipulated by s etting/clearing the correspo nding TRIS

bit(s). The output level is always low, irrespective of the

value(s) in the corresponding PORT register bit(s).

When transmitting a ‘1’, the TRIS bit must be set (input)

and a ‘0’, the TRIS bit must be clear (output).

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Firmware Master Mode of operation can be done with

either the Slave mode Idle (SSPM<3:0> = 1011), or

with either of the Slave modes in which interrupts are

enabled. When both master and slave functionality is

enabled, the software needs to differentiate the

source(s) of the interrupt.

Refer to Application Note AN554, Software

Implementation of I2C™ Bus Master (DS00554) for more

information.

17.2.9 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allow the

determin ation of when the bu s is free. The S top (P) an d

S tart (S) bits are cl eared from a Reset or when the SSP

module is disabled. The Stop (P) and Start (S) bits will

toggle based on the Start and Stop conditions. Control

of the I2C bus may be taken when the P bit of the

SSPSTAT register is set or when the bus is Idle, and

both the S and P bits are clear. When the bus is busy,

enabling the SSP Interrupt will generate the interrupt

when the Stop condition occurs.

In Multi-Master operation, the SDA line must be

monitored to see if the signal level is the expected

output level. This check only needs to be done when a

high lev el is output. If a high lev el is expec ted and a low

level is present, the device needs to release the SDA

and SCL lines (set TRIS bits). There are two stages

wher e this arbi trati on of the bu s can be los t. T hey are

the Address Transfer and Data Transfer stages.

When the slav e log ic is enab led, th e sla ve co ntinue s to

receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be

generated. If arbitration was lost during the data

transfer stage, the device will need to re-transfer the

data at a later time.

Refer to Application Note AN578, Use of the SSP

Module in the I2C™ Multi-Master Environment

(DS00578) for more information.

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PIC16(L)F722/3/4/6/7

17.2.10 CLOCK SYNCHRONIZATION

When th e CKP bit is cleared, th e SCL output is held l ow

once it is sampled low. therefore, the CKP bit will not

stretch the SCL lin e unti l an exte rnal I2C master dev ice

has alread y asserted the SC L line low . The SCL outp ut

will remain low until the CKP bit is set and all other

devices on the I2C bus have released SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL

(Figure 17-14).

17.2.11 SLEEP OP ER AT IO N

While in Sleep mode, the I2C module can receive

addresses of data, and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if SSP interrupt is enabled).

FIGURE 17-14: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX-1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON

CKP

Master device

deasserts clock

Master device

asserts clock

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit

1 = A byte is re ce ived while the SSPBUF reg is ter is s til l hol din g the previous b yte. SSPOV is a “d on’ t

care” in Transmit mode. SSPOV must be cleared in software in either mode.

0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

1 = Enables the serial port and configures the SDA and SCL pins as serial port pins(2)

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clo ck Polar ity Select bit

1 = Release control of SCL

0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

0110 = I2C Slave mode, 7-bit address

0111 = I2C Slave mode, 10-bit address

1000 = Reserved

1001 = Load SSPMSK register at SSPADD SFR Address(1)

1010 = Reserved

1011 = I2C Firmware Controlled Master mode (Slave Idle)

1100 = Reserved

1101 = Reserved

1110 = I2C Slave mode, 7-bit address w ith Start and Stop bit interrupts enabled

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Note 1: When this mode is selected, any reads or writes to the SSP ADD SFR address accesses the SSPMSK register .

2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.

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PIC16(L)F722/3/4/6/7

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: SPI Data Input Sam ple Phase bit

1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard Mode (100 kHz and 1 MHz).

0 = Slew Rate Control (limiting) enabled. Operating in I2C Fast Mode (400 kHz).

bit 6 CKE: SPI Clock Edge Select bit

This bit must be maintained clear. Used in SPI mode only.

bit 5 D/A: DATA/ADDRESS bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit

This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.

1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0 = Stop bit was not detected last

bit 3 S: Start bit

This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.

1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0 = Start bit was not detected last

bit 2 R/W: READ/WRITE bit Information

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match

to the next Start bit, Stop bit or ACK bit.

1 = Read

0 = Write

bit 1 UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

Receive:

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit:

1 = Transmit in progress, SSPBUF is full

0 = Transmi t co m plet e, SSPB U F is e mp t y

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TABLE 17-7: REGISTERS ASSOCIATED WITH I2C OPERATION

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-1 M SK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match

0 = The received address bit n is not used to detect I2C address match

bit 0 MSK<0>: Mask b i t fo r I 2C Slave Mo de, 10-bit Address

I2C Slave Mode, 10-bit Address (SSPM<3:0> = 0111):

1 = The received address bit ‘0’ is compared to SSPADD<0> to detect I2C address match

0 = The received address bit ‘0’ is not used to detect I2C address match

All other SSP modes: this bit has no effect.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADD<7:0>: Address bits

Received address

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

all other

Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Trans mit Register xxxx xxxx uuuu uuuu

SSPADD Sync hronous Ser ial Port (I2C mode) Address Register 0000 0000 0000 0000

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

SSPMSK(2) Synchronous Serial Port (I2C mode) Address Mas k Register 1111 1111 1111 1111

SSPSTAT SMP(1) CKE(1) D/A PSR/WUA BF 0000 0000 0000 0000

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I2C

mode.

Note 1: Maintain these bits clear in I2C mode.

2: Accessible only when SSPM<3:0> = 1001.

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PIC16(L)F722/3/4/6/7

18.0 PROGRAM MEMORY READ

The Flash program memory is readable during normal

operatio n over the ful l VDD range of the dev ice. To rea d

data from Program Memory, five Special Function

Registers (SFRs) are used:

•PMCON1

•PMDATL

•PMDATH

• PMADRL

• PMADRH

The value written to the PMADRH:PMADRL register

pair determines which program memory location is

read. The read operation will be initiated by setting the

RD bit of the PMCON1 register. The program memory

flash controller takes two instructions to complete the

read, causing the second instruction after the setting

the RD bit will be ignored. To avoid conflict with

program execution, it is recommended that the two

instructions following the setting of the RD bit are NOP.

When the read completes, the result is placed in the

PMDATLH:PMDATL register pair. Refer to

Example 18-1 for sample code.

EXAMPLE 18-1: PROGRAM MEMORY READ

Note: Code-protect does not effect the CPU

from performing a read operation on the

program memory. For more information,

refer to Section 8.2 “Code Protection”.

BANKSEL PMADRL ;

MOVF MS_PROG_ADDR, W;

MOVWF PMADRH ;MS Byte of Program Address to read

MOVF LS_PROG_ADDR, W;

MOVWF PMADRL ;LS Byte of Program Address to read

BANKSEL PMCON1 ;

BSF PMCON1, RD ;Initiate Read

NOP

NOP ;Any instructions here are ignored as program

;memory is read in second cycle after BSF

BANKSEL PMDATL ;

MOVF PMDATL, W ;W = LS Byte of Program Memory Read

MOVWF LOWPMBYTE ;

MOVF PMDATH, W ;W = MS Byte of Program Memory Read

MOVWF HIGHPMBYTE ;

Required

Sequence

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R-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0

Reserved — —l — — — —RD

bit 7 bit 0

Legend: S = Setable bit, cleared in hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Reserved: Read as ‘1’. Maintain this bit set.

bit 6-1 Unimplemented: Read as ‘0’

bit 0 RD: Read Control bit

1 = Initiates a n program m emory read (Th e RD is clea red in hardwa re; the RD bi t can only be set (no t

cleared) in software).

0 = Does not initiate a program memory read

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— PMD13 PMD12 PMD11 PMD10 PMD9 PMD8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PMD7 PMD6 PMD5 PMD4 PMD3 PMD2 PMD1 PMD0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a

program memory read command.

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PIC16(L)F722/3/4/6/7

TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY READ

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — PMA12 PMA11 PMA10 PMA9 PMA8

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 PMA<12:8>: Program Memory Read Address bits

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PMA7 PMA6 PMA5 PMA4 PMA3 PMA2 PMA1 PMA0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 PMA<7:0>: Program Memory Re ad Addre ss bits

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR Value on all

other Re s e ts

PMCON1 Reserved ——————RD1--- ---0 1--- ---0

PMADRH — — — Program Memory Read Address Register High Byte ---x xxxx ---x xxxx

PMADRL Program Memory Read Addres s Registe r Low Byte xxxx xxxx xxxx xxxx

PMDATH —— Program Mem ory Read Data Register High Byte --xx xxxx --xx xxxx

PMDAT L Program Mem ory Read Data Register Low Byte xxxx xxxx xxxx xxxx

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Program Memory

Read.

PIC16(L)F722/3/4/6/7

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19.0 POWER-DOWN MODE (SLEEP)

The Power-down mode is entered by executing a

SLEEP instruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

•PD bit of the STATUS register is cleared.

•TO bit of the STATUS register is set.

• Oscillator driver is turned off.

• Timer1 oscillator is unaffected

• I/O ports maintain the status they had before

SLEEP was executed (driving high, low or high-

impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin. I/O pins that

are hi gh-impedanc e inputs s hould be pul led high or low

externally to avoid switching currents caused by float-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on-chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level when

external MCLR is enabled.

19.1 Wake-up from Sleep

The dev ice ca n wa ke up f rom Sle ep t hrough o ne of th e

following events:

1. External Reset input on MCLR pin.

2. Watchdog Timer wake-up (if WDT was

enabled).

3. Interrupt from RB0/INT pin, PORTB change or a

peripheral interrupt.

The firs t event wi ll ca use a de vice Res et. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device Reset.

The PD b it, w hic h is se t on pow er- up, is clea re d when

Sleep is invoked. TO bit is cleared if WDT wake-up

occurred.

The follo wing periphe ral interrupt s can wake the device

from Sleep:

1. TMR1 Interrupt. T imer1 must be operating as an

asynchronous counter.

2. USART Receive Interrupt (Synchronous Slave

mode only)

3. A/D conversion (when A/D clock source is RC)

4. Interrupt-on-change

5. External Interrupt from INT pin

6. Capture event on CCP1 or CCP2

7. SSP Interrupt in SPI or I2C Slave mode

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up thro ugh an interrupt event, the correspondin g

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

ins tructi on after t he SLEEP instruction. If the GIE bit is

set (enabled), the device ex ecutes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should hav e a NOP after the SLEEP instru ction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

Note: A Reset generated by a WDT time out

does not drive MCLR pin low. Note: If the glo bal interru pts ar e disable d (GIE is

cleared), but any int errupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEP instru ction is com pletely executed.

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PIC16(L)F722/3/4/6/7

19.2 Wake-up Using Interrupts

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt fla g bit s et, one of the fo llowin g wil l occur:

• If the interrupt occurs before the execution of a

SLEEP instruction, the SLEEP instruction will

complete as a NOP. Therefo re, the WDT an d WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be clea red.

• If the interrupt occurs during or after the

execution of a SLEEP instruc ti on, the devic e wi ll

immediately wa ke-up from Sleep. The SLEEP

instruc t io n will be com pl etel y ex ec ute d befo re the

wake-up. The refore, the WDT and WDT pres caler

and pos tsc aler (i f enabl ed) wi ll be cle ared, the T O

bit will be set and the PD bit will be cleare d.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP i nstructi on execu ted, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruction

should be executed before a SLEEP instruction.

FIGURE 19-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR, BOR Value on all

other Resets

IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 0000 0000 0000

PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1(1)

CLKOUT(4)

INT pin

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2 0004h 0005h

Dummy Cycle

TOST(2)

PC + 2

Note 1: XT, HS or LP Oscillator mode assume d.

2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

PIC16(L)F722/3/4/6/7

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20.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process allowing the

device to be p ro gramme d w ith t he most recen t f irm war e

or a custom firmware. Fiv e pins are need ed for ICSP™

programming:

• ICSPCLK

• ICSPDAT

•MCLR

/VPP

•VDD

•VSS

The device is placed into Program/Verify mode by

holding the ICSPCLK and ICSPDAT pins low then

raising the voltage on MCLR/VPP from 0v to VPP. In

Program/Verify mode the program memory, User IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is a

bidirectional I/O used for transferring the serial data and

the ISCPCLK pin is the clock input. For more inform ation

on ICSP, refer to the “PIC16(L)F72x Memory

Programmin g Spe cif ica tion ” (DS41332).

FIGURE 20-1: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

Note: The IC D 2 produce s a VPP voltage greater

than the maximum VPP specification of the

PIC16(L)F722/3/4/6/7. When using this

programmer, an external circuit, such as

the AC164112 MPLAB ICD 2 VPP voltage

limiter, is required to keep the VPP volt a ge

within the device specifications.

VDD

VPP

GND

External D e vi ce to be

Data

Clock

VDD

MCLR/VPP

VSS

ICSPDAT

ICSPCLK

To Normal Connections

*Isolation devices (as required).

10k

Programming

Signals Programmed

VDD

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PIC16(L)F722/3/4/6/7

21.0 INSTRUCTION SET SUMMARY

The PIC16(L)F722/3/4/6/7 instruction set is highly

orthogonal and is comprised of three basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction typ e and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 21-1, while the various opcode

fields are sum m ariz ed in Table 21-1.

Table 21-2 lists the instructions recognized by the

MPASMTM assembler.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W regis ter . If ‘d’ is one, the res ult is place d

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

One instr uction cycle co nsists of four os cillator periods ;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 s. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

21.1 Read-Modify -Write Operations

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

For example, a CLRF PORTB instruction will read

PORTB, clear all the data bits, then write the result

back to PORTB. This example would have the

unintended consequence of clearing the condition that

set the RBIF flag.

TABLE 21-1: OPCODE FIELD

DESCRIPTIONS

FIGURE 21-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

f Register file address (0x00 to 0x7F)

W Working register (accumulator)

b Bit address within an 8-bit file register

k Literal field, constant data or label

x Don’t care location (= 0 or 1).

The assembler will generate code with x = 0. It is

the recommended form of use for

compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC Progr am Counter

TO Time-ou t bit

C Carry bit

DC Digit carry bit

Z Zero bit

PD Power-down bit

Byte-oriented f ile r e gister operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriente d file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (litera l )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

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TABLE 21-2: PIC16(L)F722/3/4/6/7 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f thr ough Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C, DC, Z

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1, 2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

–

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C, DC, Z

TO, PD

C, DC, Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value pres ent

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

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21.2 Instructi on Descriptions

ADDLW Add literal and W

Syntax: [ label ] ADDLW k

Operands: 0  k  255

Operation: (W) + k  (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are added to the 8-bit literal ‘k’

and the result is placed in the

W register.

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) + (f)  (destination)

Status Affected: C, DC, Z

Desc ription: Add the conten ts of the W regis ter

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W registe r . I f

‘d’ is ‘1’, the result is stored back

in register ‘f’.

ANDLW AND literal with W

Syntax: [ label ] ANDLW k

Operands: 0  k  255

Operation: (W) .AND. (k)  (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the 8-bit literal ‘k’.

The result is placed in the W reg-

ister.

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0  f  127

d 0,1

Operation: (W) .AND. (f)  (destination)

Status Affected: Z

Description: AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is sto r ed bac k in regi ste r ‘f’.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0  f  127

0  b  7

Operation: 0  (f<b>)

Status Affe cte d: None

Description: Bit ‘b’ in register ‘f’ is cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0  f  127

0  b  7

Operation: 1  (f<b>)

Status Affe cte d: None

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0  f  127

0  b  7

Operation: skip if (f<b>) = 0

Status Affe cte d: None

Descr iption: If bit ‘b’ in regis ter ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f ’, is ‘0’, the

next instru ction is discarded, and

a NOP is executed instead, making

this a 2-cycle instruction.

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BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0  f  127

0  b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Desc ription: If bi t ‘b’ in regi ster ‘f’ is ‘0’, the ne xt

instructi on is exec uted .

If bit ‘b’ is ‘1’, then the next

instructi on is disca rded and a NOP

is exec ute d i nst ead, making thi s a

2-cycle instruction.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0  k  2047

Operation: (PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<4:3>)  PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The 11-bit immediate

address is loaded into PC bits

<10:0>. The upper bits of the PC

are load ed from PCLA TH. CALL is

a 2-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0  f  127

Operation: 00h  (f)

1  Z

Status Affected: Z

Desc ript ion : The content s of regi ste r ‘f’ are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h  (W)

1  Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h  WDT

0  WDT prescaler,

1  TO

1  PD

Status Affe cte d: TO, PD

Description: CLRWDT instruction resets the

W atchdog T imer . It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (destination)

Status Affe cte d: Z

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination)

Status Affe cte d: Z

Description: Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

stored back in register ‘f’.

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DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) - 1  (destination);

skip if result = 0

Status Affected: None

Description: The contents of register ‘f’ are

decrem ented. If ‘d’ is ‘0’, th e result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

If the result is ‘1’, the next

instruction is executed. If the

resu lt is ‘0’, then a NOP is

executed instead, making it a

2-cycle instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0  k  2047

Operation: k  PC<10:0>

PCLATH<4:3>  PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The 11-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a

2-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination)

Status Affected: Z

Description: The contents of register ‘f’ are

incremen ted. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0  f  127

d  [0,1]

Operation: (f) + 1  (destination),

skip if result = 0

Status Affe cte d: None

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

registe r ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOP is executed

instead, making it a 2-cycle

instruction.

IORLW Inclusive OR literal with W

Syntax: [ label ] IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  (W)

Status Affe cte d: Z

Descr iption: The con tents of t he W register a re

OR’ed with th e 8-bit literal ‘k ’. The

result is placed in the

W register.

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .OR. (f)  (destination)

Status Affe cte d: Z

Description: Inclusive OR the W register with

placed in the W register. If ‘d’ is

‘1’, the result is pla ce d back in

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MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f)  (dest)

Status Affected: Z

Description: The contents of register f is

moved to a destina tion dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1 is useful to test a file

affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W= value in FSR

Z= 1

MOVLW Move literal to W

Syntax: [ label ] MOVLW k

Operands: 0  k  255

Operation: k  (W)

Status Affected: None

Description: The 8-bit literal ‘k’ is loaded into W

assemble as ‘0’s.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W= 0x5A

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0  f  127

Operation: (W)  (f)

Status Affe cte d: None

Description: Move data from W register to

Words: 1

Cycles: 1

Example: MOVW

FOPTION

Before Instruction

OPTION= 0xFF

W = 0x4F

After Instruction

OPTION= 0x4F

W = 0x4F

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affe cte d: None

Description: No operation.

Words: 1

Cycles: 1

Example: NOP

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PIC16(L)F722/3/4/6/7

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS  PC,

1  GIE

Status Affected: None

Description: Return from Interrupt. Stack is

POPed an d Top-of-S tack (T OS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE (INT-

CON<7>). This is a 2-cycle

instruction.

Words: 1

Cycles: 2

Example: RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with literal in W

Syntax: [ label ] RETLW k

Operands: 0  k  255

Operation: k  (W);

TOS  PC

Status Affe cte d: None

Description: The W register is loaded with the

8-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a 2-cycle instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE;W contains

table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS  PC

Status Affe cte d: None

Description: Return from subroutine. The stack

is POPed an d t he top of th e s t a ck

(TOS) is loaded into the program

counter. This is a 2-cycle instruc-

tion.

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RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W = 1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0  f  127

d  [0,1]

Operation: See description below

Status Affected: C

Desc ript ion : The cont en t s of regis te r ‘f’ are

rotat ed one bit to the r ight throug h

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is place d

back in register ‘f ’.

SLEEP Enter Sleep mode

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT prescaler,

1  TO,

0  PD

Status Affe cte d: TO, PD

Descripti on: The power-down S tat us bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with th e oscillat or stopped.

SUBLW Subtract W from literal

Syntax: [ label ] SUBLW k

Operands: 0 k 255

Operation: k - (W) W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

compl ement method) fro m the 8-bit

literal ‘ k’. The resul t is placed in the

W register.

C = 0W  k

C = 1W  k

DC = 0W<3:0>  k<3:0>

DC = 1W<3:0>  k<3:0>

 2007-2015 Microchip Technology Inc. DS40001341F-page 195

PIC16(L)F722/3/4/6/7

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 f 127

d  [0,1]

Operation: (f) - (W) destination)

Status Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from register ‘f ’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0  f  127

d  [0,1]

Operation: (f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

‘0’, the result is placed in the W

placed in register ‘f’.

C = 0W  f

C = 1W  f

DC = 0W<3:0>  f<3:0>

DC = 1W<3:0>  f<3:0>

XORLW Exclusive OR literal with W

Syntax: [ label ] XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W)

Status Affe cte d: Z

Description: The contents of the W register

are XOR’ed with the 8-bi t

literal ‘k’. The result is placed in

the W register.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0  f  127

d  [0,1]

Operation: (W) .XOR. (f) destination)

Status Affe cte d: Z

Description: Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

stored back in register ‘f’.

PIC16(L)F722/3/4/6/7

DS40001341F-page 196  2007-2015 Microchip Technology Inc.

22.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers (MCU) and dsPIC® digital

signal controllers (DSC) are supported with a ful l range

of software and hardware development tools:

• Integrated Development Environment

- MPLAB® X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

-MPASM

TM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB X SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

- PICkit™ 3

• Devic e Progra mmers

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Third-party development tools

22.1 MPLAB X Integrated Devel opment

Environment Software

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows®,

Linux and Mac OS® X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

With com plete projec t managem ent, visual cal l graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multipl e project s with simu ltane ous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

Feature-Rich Editor:

• Color syntax highlighting

• Smart code completion makes suggestions and

provides hints as you type

• Au tomati c c od e f orm atti ng bas ed on us er-d efi ned

rules

• Liv e parsing

User-Friendly, Customizabl e Interfa ce :

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project -Bas ed Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Si mu lt aneous debugg in g sess io ns

File History and Bug Tracking:

• Loc al file history feature

• Built-in support for Bugzilla issue tracker

 2007-2015 Microchip Technology Inc. DS40001341F-page 197

PIC16(L)F722/3/4/6/7

22.2 MPLAB XC Compilers

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

MPLAB XC Co mpilers inc lude an asse mbler , li nker and

utilities. The assembler generates relocatable object

files that can t hen b e arc hiv ed o r linked wi th ot her rel o-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler inclu de:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Ri ch dire cti ve set

• Flexible macro language

• MPLAB X IDE compatibility

22.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly co de

• Conditional assembly for multipurpose

sour ce fil es

• Directives that allow complete control over the

assembly process

22.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLI B Obje ct Libra rian man ages th e creati on and

modification of library files of precompiled code. When

a rout in e from a l ibra ry is called fro m a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion an d extraction

22.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archi ved or link ed with other rel ocat ab le objec t

files and archives to create an executable file. Notable

features of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

• Ric h dire cti ve set

• Flexible macro language

• MPLAB X IDE compatibility

PIC16(L)F722/3/4/6/7

DS40001341F-page 198  2007-2015 Microchip Technology Inc.

22.6 MPLAB X SIM Software Simulator

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most pe ripherals an d internal regi sters.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

22.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MP LAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cable s.

22.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 int erface and is connected to t he target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

22.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of P IC and dsPIC Flash microcontrollers at a most

af fordable pr ice point us ing the powerfu l graphica l user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

22.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Devic e Programmer ca n read, verif y and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 h as high-spe ed co mmunicat ions an d

optimized algorithms for quick programming of large

memory devices, and incorpo rates an MMC card for file

storage and data applications.

 2007-2015 Microchip Technology Inc. DS40001341F-page 199

PIC16(L)F722/3/4/6/7

22.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

use d in teaching envi ronments, for prototyping c ustom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a l ine of evaluation k its and demo nstra-

tion software for analog fil ter desi gn, KEELOQ® security

ICs, CAN, IrDA®, PowerSmart battery management,

SEEVAL® evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience t he specified d evice. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

22.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companie s, such as Gimpel

and Trace S ystems

• Pro toc ol A nal yz ers fro m comp anies, such as

Saleae and Total Phase

• Demonstration Boards from companies, such as

MikroElektronika, Digilent® and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika®

PIC16(L)F722/3/4/6/7

DS40001341F-page 200  2007-2015 Microchip Technology Inc.

23.0 ELECTRICAL SPECIFICATIONS

Absolute Maxim um Ratings(†)

Ambient temperature under bias.......................................................................................................-40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS, PIC16F72X ............................................................................... -0.3V to +6.5V

Voltage on VCAP pin with respect to VSS, PIC16F72X ....................................................................... -0.3V to +4.0V

Voltage on VDD with respect to VSS, PIC16LF72X ............................................................................. -0.3V to +4.0V

Voltage on MCLR with respect to Vss .................................................................................................-0.3V to +9.0V

Voltage on all other pins with respect to VSS ............................................................................-0.3V to (VDD + 0.3V)

Total power dissipation(1) ...............................................................................................................................800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 70 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin...............................................................................................25 mA

Maximum current sunk by all ports(2), -40°C  TA  +85°C for industrial ........................................................200 mA

Maximum current sunk by all ports(2), -40°C  TA  +125°C for extended........................................................90 mA

Maximum current sourced by all ports(2), 40°C  TA  +85°C for industrial ................................................... 140 mA

Maximum current sourced by all ports(2), -40°C  TA  +125°C for extended...................................................65 mA

Note 1: Power diss ip ation is ca lcula ted as fo llows: PDIS = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device . This is a stre ss rating onl y and functi onal operati on of the devi ce at those or an y other condi tions abov e those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

 2007-2015 Microchip Technology Inc. DS40001341F-page 201

PIC16(L)F722/3/4/6/7

23.1 DC Characteristi cs: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended)

PIC16LF722/3/4/6/7 Stand ard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F722/3/4/6/7 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param.

No. Sym. Characteristic Min. Typ† Max. Units Conditions

D001 VDD Supply Voltage

PIC16LF722/3/4/6/7 1.8

1.8

2.3

2.5

—

3.6

FOSC  16 MHz: HFINTOSC, EC

FOSC  4MHz

FOSC  20 MHz , EC

FOSC  20 MHz , HS

D001 PIC16F722/3/4/6/7 1.8

1.8

2.3

2.5

—

5.5

FOSC  16 MHz: HFINTOSC, EC

FOSC  4 MHz

FOSC  20 MHz, EC

FOSC  20 MHz, HS

D002* VDR RAM Data Retention Voltage(1)

PIC16LF722/3/4/6/7 1.5 — — V Device in Sleep mode

D002* PIC16F722/3/4/6/7 1.7 — — V Device in Sleep mode

VPOR*Po wer-on Reset Release Vol tage —1.6— V

VPORR*Power-on Reset Rearm Voltage

PIC16LF722/3/4/6/7 — 0.8 — V Device in Sleep mode

PIC16F722/3/4/6/7 —1.7 — V Device in Sleep mode

D003 VFVR Fixed Voltage Reference Volt age,

Initial Accuracy -8

-8

—

VFVR = 1.024V, VDD  2.5V

VFVR = 2.048V, VDD  2.5V

VFVR = 4.096V, VDD 4.75V;

-40 TA85°C

-8

—

VFVR = 1.024V, VDD  2.5V

VFVR = 2.048V, VDD  2.5V

VFVR = 4.096V, VDD 4.75V;

-40 TA125°C

D004* SVDD VDD Rise Rate to ensure internal

Power-on Reset signal 0.05 — — V/ms See Section 3. 2 “Po w er-o n Reset

(POR)” for details.

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These paramet ers are for design guidance only and are

not tested.

Note 1: T his is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PIC16(L)F722/3/4/6/7

DS40001341F-page 202  2007-2015 Microchip Technology Inc.

FIGURE 23-1: POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

VSS

NPOR

TPOR(3)

POR REARM

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

TVLOW(2)

 2007-2015 Microchip Technology Inc. DS40001341F-page 203

PIC16(L)F722/3/4/6/7

23.2 DC Characteristi cs: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended)

PIC16LF722/3/4/6/7 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for indu strial

-40°C  TA  +125°C for extended

PIC16F722/3/4/6/7 Standard Operating Condit ion s (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for indu strial

-40°C  TA  +125°C for extended

Param

No. Device

Characteristics Min. Typ† Max. Units Conditions

VDD Note

Supply Current (IDD)(1, 2)

D009 LDO Regulator —350 —A — HS, EC OR INTOSC/IN TOSCIO (8-16 MHZ)

Clock modes with all VCAP pins disabled

—50 —A — All VCAP pins disabled

—30 —A — VCAP enabled on RA0, RA5 or RA6

— 5 — A — LP Clock mode and Sleep (requires F VR and

BOR to be disabled)

D010 — 7.0 12 A1.8F

OSC = 32 kHz

LP Oscillator mode (Note 4),

-40°C  TA  +85°C

—9.014 A3.0

D010 —11 20 A1.8 FOSC = 32 kHz

LP Oscillator mode (Note 4),

-40°C  TA  +85°C

—14 22 A3.0

—15 24 A5.0

D011 — 7.0 12 A1.8

FOSC = 32 kHz

LP Oscillator mode

-40°C  TA  +125°C

—9.018 A3.0

D011 —11 21 A1.8 FOSC = 32 kHz

LP Oscillator mode (Note 4)

-40°C  TA  +125°C

—14 25 A3.0

—15 27 A5.0

D011 — 110 150 A1.8F

OSC = 1 MHz

XT Oscillator mode

— 150 215 A3.0

D011 —120 175 A1.8 FOSC = 1 MHz

XT Oscillator mode (Note 5)

—180 250 A3.0

—240 300 A5.0

D012 — 230 300 A1.8F

OSC = 4 MHz

XT Oscillator mode

— 400 600 A3.0

D012 —250 350 A1.8 FOSC = 4 MHz

XT Oscillator mode (Note 5)

—420 650 A3.0

—500 750 A5.0

D013 — 125 180 A1.8F

OSC = 1 MHz

EC Oscillator mode

— 230 270 A3.0

D013 —150 205 A1.8 FOSC = 1 MHz

EC Oscillator mode (Note 5)

—225 320 A3.0

—250 410 A5.0

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA ) with REXT in k

4: FVR and BOR are disabled.

5: 0.1 F capacitor on VCAP (RA0).

PIC16(L)F722/3/4/6/7

DS40001341F-page 204  2007-2015 Microchip Technology Inc.

Supply Current (IDD)(1, 2)

D014 — 290 330 A1.8FOSC = 4 MHz

EC Oscillator mode

— 460 500 A3.0

D014 —300 430 A1.8 FOSC = 4 MHz

EC Oscillator mode (Note 5)

—450 655 A3.0

—500 730 A5.0

D015 — 100 130 A1.8F

OSC = 500 kHz

MFINTOSC mode

— 120 150 A3.0

D015 —115 195 A1.8 FOSC = 500 kHz

MFINTOSC mode (Note 5)

—135 200 A3.0

—150 220 A5.0

D016 — 650 800 A1.8F

OSC = 8 MHz

HFINTOSC mode

— 1000 1200 A3.0

D016 —625 850 A1.8 FOSC = 8 MHz

HFINTOSC mode (Note 5)

—1000 1200 A3.0

—1100 1500 A5.0

D017 — 1.0 1.2 mA 1.8 FOSC = 16 MHz

HFINTOSC mode

— 1.5 1.85 mA 3.0

D017 — 1 1.2 mA 1.8 FOSC = 16 MHz

HFINTOSC mode (Note 5)

—1.5 1.7 mA 3.0

—1.7 2.1 mA 5.0

D018 — 210 240 A1.8F

OSC = 4 MHz

EXTRC mode (Note 3, Note 5)

— 340 380 A3.0

D018 —225 320 A1.8 FOSC = 4 MHz

EXTRC mode (Note 3, Note 5)

—360 445 A3.0

—410 650 A5.0

D019 — 1.6 1.9 mA 3.0 FOSC = 20 MHz

HS Oscillator mode

—2.02.8mA3.6

D019 —1.6 2mA 3.0 FOSC = 20 MHz

HS Oscillator mode (Note 5)

—1.9 3.2 mA 5.0

23.2 DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Industrial, Extended) (Continued)

PIC16LF722/3/4/6/7 Standard Operat ing Condition s (unless otherwise s tated)

Operating temperature -40°C  TA  +85°C for indu strial

-40°C  TA  +125°C for extended

PIC16F722/3/4/6/7 Standard Opera ting Conditions (unless othe r wise stat e d)

Operating temperature -40°C  TA  +85°C for indu strial

-40°C  TA  +125°C for extended

Param

No. Device

Characteristics Min. Typ† Max. Units Conditions

VDD Note

Note 1: The test conditions for all IDD measurem ents in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended

by the formula IR = VDD/2REXT (mA ) with REXT in k

4: FVR and BOR are disabled.

5: 0.1 F capacitor on VCAP (RA0).

 2007-2015 Microchip Technology Inc. DS40001341F-page 205

PIC16(L)F722/3/4/6/7

23.3 DC Characteristi cs: PIC16(L)F722/3/4/6/7-I/E (Power-Down)

PIC16LF722/3/4/6/7 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F722/3/4/6/7 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Characteristics Min. Typ† Max.

+85°C Max.

+125°C Units Conditions

VDD Note

Power-down Base Current (IPD)(2)

D020 — 0.02 0.7 3.9 A 1.8 WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

— 0.08 1.0 4.3 A3.0

D020 —4.3 10.2 17 A1.8 WDT, BOR, FVR, and T1OSC

disabled, all Peripherals Inactive

— 5 10.5 18 A3.0

—5.5 11.8 21 A5.0

D021 — 0.5 1.7 4.1 A 1.8 LPWDT Current (Note 1)

— 0.8 2.5 4.8 A3.0

D021 — 6 13.5 18 A1.8 LPWDT Current (Note 1)

—6.5 14.5 19 A3.0

—7.5 16 22 A5.0

D021A — 8.5 14 19 A 1.8 F VR curr ent (Note 1. Note 3)

— 8.5 14 20 A3.0

D021A —23 44 48 A1.8 FVR current (Note 1, Note 3,

Note 5)

—25 45 55 A3.0

—26 60 70 A5.0

D022 — — — — A 1.8 BOR Current (Note 1, Note 3)

— 7.5 12 22 A3.0

D022 — — — — A1.8 BOR Current (Note 1, Note 3,

Note 5)

—23 42 49 A3.0

—25 46 50 A5.0

D026 — 0.6 2 — A 1.8 T1OSC Current (Note 1)

—1.83.0 — A3.0

D026 —4.5 11.1 —A1.8 T1OSC Current (Note 1)

— 6 12.5 —A3.0

— 7 13.5 —A5.0

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD curr e n t fr om thi s l im i t. Max

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Pow er-down curre nt is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled

4: A/D oscillator source is FRC

5: 0.1 F capacitor on VCAP (RA0).

PIC16(L)F722/3/4/6/7

DS40001341F-page 206  2007-2015 Microchip Technology Inc.

Power-down Base Current (IPD)(2)

D027 — 0.06 0.7 5.0 A 1.8 A/D Current (Note 1, Note 4), no

conversion in progress

— 0.08 1.0 5.5 A3.0

D027 — 6 10.7 18 A1.8 A/D Current (Note 1, Note 4), no

conversion in progress

— 7 10.6 20 A3.0

—7.2 11.9 22 A5.0

D027A — 250 400 — A 1.8 A/D Current (Note 1, Note 4),

conversion in progress

— 250 400 — A3.0

D027A —280 430 —A1.8 A/D Current (Note 1, Note 4,

Note 5), conversion in progress

—280 430 —A3.0

—280 430 —A5.0

D028 — 2.2 3.2 14.4 A 1.8 Cap Sense Low Power

Oscillator mode

— 3.3 4.4 15.6 A3.0

D028 —6.5 13 21 A1.8 Cap Sense Low Power

Oscillator mode

— 8 14 23 A3.0

— 8 14 25 A5.0

D028A — 4.2 6 17 A 1.8 Cap Sens e Medium Power

Oscillator mode

—6 7 18A3.0

D028A —8.5 15.5 23 A1.8 Cap Sense Medium Power

Oscillator mode

—11 17 24 A3.0

—11 18 27 A5.0

D028B — 12 14 25 A 1.8 Cap Sense High Power

Oscillator mode

—3235 44 A3.0

D028B —16 20 31 A1.8 Cap Sense High Power

Oscillator mode

—36 41 50 A3.0

—42 49 58 A5.0

23.3 DC Characteristi cs: PIC16(L)F722/3/4/6/7-I/E (Power-Down) (Cont inued)

PIC16LF722/3/4/6/7 Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

PIC16F722/3/4/6/7 Standard Operati ng Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Device Characteristics Min. Typ† Max.

+85°C Max.

+125°C Units Conditions

VDD Note

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral  current can be determined by subtracting the base IDD or IPD current from th i s l imit. Ma x

values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Powe r-down curre nt is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

3: Fixed Voltage Reference is automatically enabled whenever the BOR is enabled

4: A/D oscillator source is FRC

5: 0.1 F capacitor on VCAP (RA0).

 2007-2015 Microchip Technology Inc. DS40001341F-page 207

PIC16(L)F722/3/4/6/7

23.4 DC Characteristics: PIC16(L)F722/3/4/6/7-I/E

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

VIL Input L ow Vo ltage

I/O PORT:

D030 with TTL buffer — — 0.8 V 4.5V  VDD  5.5V

D030A — — 0.15 VDD V1.8V  VDD  4.5V

D031 with Schmitt Trigger buffer — — 0.2 VDD V2.0V  VDD  5.5V

with I2C levels — — 0.3 VDD V

D032 MCLR, OSC1 (RC mode)(1) ——0.2VDD V

D033A OSC1 (HS mode) — — 0.3 VDD V

VIH Input High Voltage

I/O po rts : — —

D040 with TTL buffer 2.0 — — V 4.5V  VDD 5.5V

D040A 0.25 VDD +

0.8 ——V1.8V  VDD  4.5V

D041 with Sc hmitt Trigger buffer 0.8 VDD ——V2.0V  VDD  5.5V

with I2C levels 0.7 VDD ——V

D042 MCLR 0.8 VDD ——V

D043A OSC1 (HS mode) 0.7 VDD ——V

D043B OSC1 (RC mode) 0.9 VDD ——V(No te 1)

IIL Input Leakage Current(2)

D060 I/O ports — ± 5

± 5

± 125

± 1000

VSS  VPIN  VDD, Pin at high-

impedance, 85°C

125°C

D061 MCLR(3) —± 50± 200nAVSS  VPIN  VDD, 85°C

IPUR PORTB Weak Pull-up Current

D070* 25

25 100

140 200

300 AVDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS

VOL Output Low Voltage(4)

D080 I/O ports ——0.6V

IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V

IOL = 1.8mA, VDD = 1.8V

VOH Output High Voltage(4)

D090 I/O ports VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V

IOH = 1mA, VDD = 1.8V

Capacitive Lo ading Specs on Output Pins

D101* COSC2 OSC 2 pin — — 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO All I/O pins — — 50 pF

Program Flash Memory

Legend: T BD = To Be Determined

*These parameters are characterized but not tested.

†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at differ ent input voltages.

4: Including OSC2 in CLKOUT mode.

PIC16(L)F722/3/4/6/7

DS40001341F-page 208  2007-2015 Microchip Technology Inc.

D130 EPCell Endurance 100 1k — E/W Tem perat ure during programm ing:

10°C  TA  40°C

D131 VDD for Read VMIN ——V

Voltage on MCLR/VPP during

Erase/Program 8.0 — 9.0 V Temperat ure during programm ing:

10°C  TA  40°C

VDD for Bulk Erase 2.7 3 — V Temperature during programm ing:

10°C  TA  40°C

D132 VPEW VDD for Write or Row Erase 2.7 — — V VMIN = Minimum operating voltage

VMAX = Maximum operating

voltage

IPPPGM Current on MCLR/VPP during

Erase/Write ——5.0mA

Temperat ure during programm ing:

10°C  TA  40°C

IDDPGM Current on VDD during Erase/

Write —5.0 mA Tem perat ure during programming:

10°C  TA  40°C

D133 TPEW Erase/Write cycle time — 2.8 ms Tem perat ure during programming:

10°C  TA  40°C

D134 TRETD Characteristic Retention 40 — — Year Provided no other specifications

are violated

VCAP Capacitor Charging

D135 Charging current — 200 — A

D135A Source/sink capability when

charging complete —0.0—mA

23.4 DC Characteristics: PIC16(L)F722/3/4/6/7-I/E (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C  TA  +85°C for industrial

-40°C  TA  +125°C for extended

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

Legend: TBD = To Be Determined

*These parameters are characterized but not tested.

†Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at differ ent input voltages.

4: Including OSC2 in CLKOUT mode.

 2007-2015 Microchip Technology Inc. DS40001341F-page 209

PIC16(L)F722/3/4/6/7

23.5 Thermal Considerations

Stand ard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Typ. Units Conditions

TH01 JA Thermal Resistance Junction to Ambient 60 C/W 28-pin SPDIP package

80 C/W 28-pin SOIC package

90 C/W 28-pin SSOP package

27.5 C/W 28-pin UQFN 4x4mm packag e

27.5 C/W 28-pin QFN 6x6mm package

47.2 C/W 40-pin PDIP package

46 C/W 44-pin TQFP package

24.4 C/W 44-pin QFN 8x8mm package

TH02 JC Thermal Resistance Junction to Case 31.4 C/W 28-pin SPDIP package

24 C/W 28-pin SOIC package

24 C/W 28-pin SSOP package

24 C/W 28-pin UQFN 4x4mm package

24 C/W 28-pin QFN 6x6mm package

24.7 C/W 40-pin PDIP package

14.5 C/W 44-pin TQFP package

20 C/W 44-pin QFN 8x8mm package

TH03 TJMAX Maximum Junction Temperature 150 C

TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O

TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)

TH06 PI/OI/O Powe r Dissipation — W PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature

3: TJ = Junction Temperature

PIC16(L)F722/3/4/6/7

DS40001341F-page 210  2007-2015 Microchip Technology Inc.

23.6 Timing Paramet er Symbology

The timing parameter symbols have been created with

one of the following formats:

FIGURE 23-2: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O PORT t1 T1CKI

mc MCLR wr WR

Uppe rcase lett ers an d thei r meanings:

SFFall PPeriod

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

Legend: CL = 50 pF for all pins, 15 pF for

OSC2 output

Load Con dition

 2007-2015 Microchip Technology Inc. DS40001341F-page 211

PIC16(L)F722/3/4/6/7

23.7 AC Characteristi cs: PIC16F72X-I/E

FIGURE 23-3: CLOCK TIMING

FIGURE 23-4: PIC16F722/3/4/6/7 VOLTAGE FREQUENCY GRAPH, -40°C





+125°C

OSC1/CLKIN

OSC2/CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

OS02

OS03OS04 OS04

OSC2/CLKOUT

(LP,X T,HS Modes)

(CLKOUT Mode)

1.8

2.5

2.0

2.3

Frequency (MHz)

VDD (V)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 23-1 for each Oscillator mode’s supported frequencies.

420

10 16

5.5

3.6

PIC16(L)F722/3/4/6/7

DS40001341F-page 212  2007-2015 Microchip Technology Inc.

FIGURE 23-5: PI C16L F72 2/3/ 4/6/7 VOLTAGE FREQUENCY GRAPH, -40°C





+125°C

FIGURE 23-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

1.8

2.5

2.0

2.3

Frequency (MHz )

VDD (V)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 23-1 for each Oscillator mode’s supported frequencies.

420

10 16

3.6

125

2.0

VDD (V)

4.0 5.04.5

Temperature (°C)

2.5 3.0 3.5 5.5

1.8

Note 1: This chart covers both regulator enabled and regulator disabled states.

2: Regulator Nominal voltage

3.3(2)

-40

-20

+ 5%

± 2%

+ 5%

 2007-2015 Microchip Technology Inc. DS40001341F-page 213

PIC16(L)F722/3/4/6/7

TABLE 23-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Stand ard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS01 FOSC External CLKIN Frequency(1) DC — 37 kHz LP Oscillator mode

DC — 4 MHz XT Oscillator mode

DC — 20 MHz HS Oscillator mode

DC — 20 MHz EC Oscillator mode

Oscillator Frequency(1) — 32.768 — kHz LP Oscillator mode

0.1 — 4 MHz XT Oscillator mode

1 — 20 MHz HS Oscillator mode

DC — 4 MHz RC Oscillator mode

OS02 TOSC External CLKIN Period(1) 27 — s LP Oscillator mode

250 — ns XT Oscillator mode

50 — ns HS Oscillator mode

50 — ns EC Oscillator mode

Oscillator Period(1) — 30.5 — s LP Oscillator mode

250 — 10,000 ns XT Oscillator mode

50 — 1,000 ns HS Oscillator mode

250 — — ns RC Oscillator mode

OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC

OS04* TosH,

TosL External CLKIN High,

External CLKIN Low 2——s LP oscillator

100 — — ns XT oscillator

20 — — ns HS oscillator

OS05* TosR,

TosF External CLKIN Rise,

External CLKIN Fall 0—ns LP oscillator

0—ns XT oscillator

0—ns HS oscillator

* These parameters are characterized but not tested.

† Data in “T yp” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All sp ecified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at “min” values with an ex ternal clock applied to OSC1 pin. When an external

clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

PIC16(L)F722/3/4/6/7

DS40001341F-page 214  2007-2015 Microchip Technology Inc.

TABLE 23-2: OSCILLATOR PARAMETERS

FIGURE 23-7: CLKOUT AND I/O TIMING

Standard Operating Condi t ions (unless otherwise stated)

Operating Temperature - 40°C TA +125°C

Param

No. Sym. Characteristic Freq.

Tolerance Min. Typ† Max. Units Conditions

OS08 HFOSC Internal Calibrated HFINTOSC

Frequency(2) 2% — 16.0 — MHz 0°C  TA  +85°C,

VDD V

5% — 16.0 — MH z -40°C  TA  +125°C

OS08A MFOSC Internal Calibrated MFINTOSC

Frequency(2) 2% — 500 — kHz 0°C  TA  +85°C

VDD V

5% — 500 10 kHz -40 °C  TA  +125°C

OS10* TIOSC ST HFIN TOSC Wake-up from Sleep

Start-up Time ——58s

MFINTOSC Wake-up from Sleep

Start-up Time — — 20 30 s

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These paramet ers are for design guidance only and are

not tested.

Note 1: Ins truction cyc le period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current

consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an

external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

3: By design.

FOSC

CLKOUT

I/O pi n

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

OS11

OS19

OS13

OS15

OS18, OS19

OS20

OS21

OS17 OS16

OS14

OS12

OS18

Old Value New Value

Write Fetch Read ExecuteCycle

 2007-2015 Microchip Technology Inc. DS40001341F-page 215

PIC16(L)F722/3/4/6/7

TABLE 23-3: CLKOUT AND I/O TIMING PARAMETERS

FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMI NG

Standard Operating Condi t ions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

OS11 TosH2ckL Fosc to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V

OS12 TosH2ckH Fosc to CLKOUT (1) — — 72 ns VDD = 3.3-5.0V

OS13 TckL2ioV CLKOUT to Port out valid(1) — — 20 ns

OS14 TioV 2ckH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns

OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid — 50 70* ns VDD = 3.3-5.0V

OS16 TosH2ioI Fosc (Q2 cycle) to Port input invalid

(I/O in hold time) 50 — — ns VDD = 3.3-5.0V

OS17 TioV2osH P ort input valid to Fosc(Q2 cycle)

(I/O i n se tu p ti me) 20 — — ns

OS18 TioR Port output rise time(2) —

—40

15 72

32 ns VDD = 2.0V

VDD = 3.3-5.0V

OS19 TioF Port output fall time(2) —

—28

15 55

30 ns VDD = 2.0V

VDD = 3.3-5.0V

OS20* Tinp INT pin input high or low time 25 — — ns

OS21* Trbp PORTB interrupt-on-change new input level

time TCY ——ns

* These parameters are characterized but not tested.

† Data in “ Typ” column is at 3.0V, 25C unless otherwise stated.

Note 1: Meas urements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Start-Up Time

Internal Reset(1)

Wat c hdog Timer

I/O pins

Note 1: Asserted low.

Reset(1)

PIC16(L)F722/3/4/6/7

DS40001341F-page 216  2007-2015 Microchip Technology Inc.

FIGURE 23-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS

VBOR

VDD

(Device in Brown-out Reset) (Device not in Brown-out Reset)

33(1)

Note 1: 64 ms delay only if P W RTE bit in the Configuration Word register is programmed to ‘0’.

Reset

(due to BOR)

VBOR and VHYST

 2007-2015 Microchip Technology Inc. DS40001341F-page 217

PIC16(L)F722/3/4/6/7

TABLE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET PARAMETERS

FIGURE 23-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

30 TMCLMCLR Pulse Width (low) 2

5—

——

—s

sVDD = 3.3-5V, -40°C to +85°C

VDD = 3.3-5V

31 TWDTLP Low Power Watchdog Timer Time-

out Period (No Prescaler) 10 18 27 ms VDD = 3.3V-5V

32 TOST Oscilla tor S tart-up Timer Period(1 ), (2) — 1024 — Tosc (Note 3)

33* TPWRT Power-up Timer Period, PWRTE =040 65 140 ms

34* TIOZ I/O high-impedance from MCLR Low

or Watchdog Timer Reset ——2.0s

35 VBOR Brown -out Reset Voltage 2. 38

1.80 2.5

1.9 2.73

2.11 VBORV=2.5V

BORV=1.9V

36* VHYST Brown-out Reset Hyster esis 0 25 50 mV -40°C to +85 °C

37* TBORDC Brown-out Reset DC Response

Time 135

10 sVDD  VBOR, -40°C to +85°C

VDD  VBOR

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note1: Instruction cycle period (TCY) equals fou r tim es the i npu t os ci llator time base p eriod. All specifi ed v al ues are

based on char act erization dat a for th at p articu lar os cill ator ty pe un der st andard opera ting c ondit ions with th e

device ex ecuting co de. Exceedi ng these specif ied limit s may resu lt in an unst able osci llator operat ion and/or

higher than ex pecte d cu rrent con sumpt ion. All de vice s are tested to op erate at “min” v alues with an exte rnal

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no

clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 F and 0.01 F values in parallel are recommended.

T0CKI

T1CKI

40 41

45 46

47 49

TMR0 or

TMR1

PIC16(L)F722/3/4/6/7

DS40001341F-page 218  2007-2015 Microchip Technology Inc.

TABLE 23-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

FIGURE 23-11: CAPTURE/COMPARE/PWM TIMINGS (CCP)

TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Stand ard Operating Conditions (unless otherwise stated)

Operating Tempe rature -40°C TA +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 1 0 — — ns

41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns

With Prescaler 1 0 — — ns

42* TT0P T0 CK I Period Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* TT1H T1CKI High

Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous, with Prescaler 15 — — ns

Asynchronous 30 — — ns

46* TT1L T1CKI Low

Time Synchronous, No Prescaler 0.5 TCY + 20 — — ns

Synchronous, with Prescaler 15 — — ns

Asynchronous 30 — — ns

47* TT1P T1CKI Input

Period Synchronous Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Asynchronous 60 — — ns

48 FT1 Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN) 32.4 32.768 33.1 kHz

49* TCKEZTMR1 Delay from External Clock Edge to Timer

Increment 2 TOSC —7 TOSC — Timers in Sync mode

* These parameters are characterized but not tested.

† Data in “T yp” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Stand ard Operating Conditions (unless otherwise stated)

Operating Tempe rature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

CC01* TccL CCPx Input Low Time No Prescaler 0. 5TCY + 20 — — ns

With Prescaler 20 — — ns

CC02* TccH CCPx Input High Time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 20 — — ns

CC03* TccP CCPx Inp ut Period 3TCY + 40

N— — ns N = prescale value (1, 4 or 16)

* These parameters are characterized but not tested.

† Data in “T yp” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 23-2 for load conditions.

(Capture mode)

CC01 CC02

CC03

CCPx

 2007-2015 Microchip Technology Inc. DS40001341F-page 219

PIC16(L)F722/3/4/6/7

TABLE 23-7: PIC16F722/3/4/6/7 A/D CONVERTER (ADC) CHARACTERISTICS:

TABLE 23-8: PIC16F722/3/4/6/7 A/D CONVERSION REQUIREMENTS

Stand ard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD01 NRResolution — — 8 bit

AD02 EIL Integral Err or — — ±1.7 LSb VREF = 3.0V

AD03 EDL Differential Error — — ±1 LS b No missing codes

VREF = 3.0V

AD04 EOFF Offset Error — — ±2.2 LSb VREF = 3.0V

AD05 EGN Gain Error — — ±1.5 LSb VREF = 3.0V

AD06 VREF Reference Voltage(3) 1.8 — VDD V

AD07 VAIN Full-Scale Range VSS —VREF V

AD08 ZAIN Recommended Impedance of

Analog Voltage Source —— 50kCan go higher if external 0.01F capacitor is

present on input pin.

† Data in “T yp” column is at 3.0V , 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Total Absolute Error includes integral, differ ential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification

includes any such leakage from the ADC module.

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +125°C

Param

No. Sym. Characteristic Min. Typ† Max. Units Conditions

AD130* TAD A/D Clock Period 1.0 — 9.0 sTOSC-based

A/D Internal RC Oscillator

Period 1.0 2.0 6.0 s ADCS<1:0> = 11 (ADRC mode)

AD131 TCNV Conversion Time (not including

Acquisition Time)(1) —10.5—TAD Set GO/DONE bit to conversion

complete

AD132* TACQ Acquisition Time — 1.0 — s

* These parameters are characterized but not tested.

† Data in “T yp” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: The ADRES register may be read on the following TCY cycle.

PIC16(L)F722/3/4/6/7

DS40001341F-page 220  2007-2015 Microchip Technology Inc.

FIGURE 23-12: PIC16F722/3/4/6/7 A/D CONVERSION TIMING (NORMAL MODE)

FIGURE 23-13: PIC16F722/3/4/6/7 A/D CONVERSION TIMING (SLEEP MODE)

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

765 3210

Note 1: I f the A/D clock source is selected as RC, a time of TCY is added before the A/D clo ck starts. This allows the

SLEEP instruction to be executed.

1 TCY

AD134 (TOSC/2(1))

1 TCY

AD132

AD131

AD130

BSF ADCON0, GO

A/D CLK

A/D Data

ADRES

ADIF

Sample

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

7 5 3210

Note 1: I f the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be ex ecuted.

AD134

1 TCY

(TOSC/2 + TCY(1))

1 TCY

 2007-2015 Microchip Technology Inc. DS40001341F-page 221

PIC16(L)F722/3/4/6/7

FIGURE 23-14: U SA RT SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 23-9: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 23-15: U SA RT SYNCHRONO US RECEIVE (MASTER/SLAVE) TIMING

TABLE 23-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid 3.0-5.5V — 80 ns

1.8-5.5V — 100 ns

US121 TCKRF Clock out rise time and fall ti me

(Master mode) 3.0-5.5V — 45 ns

1.8-5.5V — 50 ns

US122 TDTRF Data-out rise time and fall time 3.0-5.5V — 45 ns

1.8-5.5V — 50 ns

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No. Symbol Characteristic Min. Max. Units Conditions

US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK  (DT hold time) 10 — ns

US126 TCKL2DTL Data-hold after CK  (DT hold time) 15 — ns

Note: Refer to Figure 23-2 for load conditions.

US121 US121

US120 US122

Note: Refer to Figure 23-2 for load conditions.

US125

US126

PIC16(L)F722/3/4/6/7

DS40001341F-page 222  2007-2015 Microchip Technology Inc.

FIGURE 23-16 : SPI MASTE R MODE TIMING (CKE = 0, SMP = 0)

FIGURE 23-17 : SPI MASTE R MODE TIMING (CKE = 1, SMP = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP70

SP71 SP72

SP73 SP74

SP75, SP76

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In LSb In

bit 6 - - - -1

Note: Refer to Figure 23-2 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP81

SP71 SP72

SP74

SP75, SP76

SP78

SP80

MSb

SP79

SP73

MSb In

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

LSb

Note: Refer to Figure 23-2 for load conditions.

 2007-2015 Microchip Technology Inc. DS40001341F-page 223

PIC16(L)F722/3/4/6/7

FIGURE 23-18 : SPI SLAVE MODE TIMING (CKE = 0)

FIGURE 23-19 : SPI SLAVE MODE TIMING (CKE = 1)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP70

SP71 SP72

SP73

SP74

SP75, SP76 SP77

SP78

SP79

SP80

SP79

SP78

MSb LSb

bit 6 - - - - - -1

MSb In bit 6 - - - -1 LSb In

SP83

Note: Refer to Figure 23-2 for load conditions.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

SP70

SP71 SP72

SP82

SP74

SP75, SP76

MSb bit 6 - - - - - -1 LSb

SP77

MSb In bit 6 - - - -1 LSb In

SP80

SP83

Note: Refer to Figure 23-2 for load conditions.

PIC16(L)F722/3/4/6/7

DS40001341F-page 224  2007-2015 Microchip Technology Inc.

TABLE 23-11: SPI MODE REQUIREMENTS

FIGURE 23-20 : I2C BUS START/STOP BITS TIMING

Param

No. Symbol Characteristic Min. Typ† Max. Units Conditions

SP70* TSSL2SCH,

TSSL2SCLSS to SCK or SCK input TCY ——ns

SP71* TSCH SC K input high time (Slave mode) TCY + 20 — — ns

SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns

SP73* TDIV2SCH,

TDIV2SCLSetup time of SDI data input to SC K edge 100 — — ns

SP74* TSCH2DIL,

TSCL2DILHold time of SDI data input to SCK edge 100 — — ns

SP75* TDOR SDO data output rise time 3.0-5.5V — 10 25 ns

1.8-5.5V — 25 50 ns

SP76* TDOF SDO data output fa ll time — 10 25 ns

SP77* TSSH2DOZSS to SDO output high-impedance 10 — 50 ns

SP78* TSCR SCK output rise time

(Master mode) 3.0-5.5V — 10 25 ns

1.8-5.5V — 25 50 ns

SP79* TSCF SC K output fall time (Master mode) — 10 25 ns

SP80* TSCH2DOV,

TSCL2DOVSDO data output valid after SCK

edge 3.0-5.5V — — 50 ns

1.8-5.5V — — 145 ns

SP81* TDOV2SCH,

TDOV2SCLSDO data output set up to SCK edge Tcy — — ns

SP82* TSSL2DOV SDO data output valid a fter SS edge — — 50 ns

SP83* TSCH2SSH,

TSCL2SSHSS after SCK edge 1.5TCY + 40 — — ns

* These parameters are characterized but not tested.

† Data in “T yp” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note: Refer to Figure 23-2 for load conditions.

SP91

SP92

SP93

SCL

SDA

Start

Condition Stop

Condition

SP90

 2007-2015 Microchip Technology Inc. DS40001341F-page 225

PIC16(L)F722/3/4/6/7

TABLE 23-12: I2C BUS START/STOP BITS REQUIREMENTS

FIGURE 23-21 : I2C BUS DATA TIMING

Param

No. Symbol Characteristic Min. Typ Max. Units Conditions

SP90* TSU:STA Start condition 100 kHz mode 4700 — — ns Only relevant for Repeated

Start conditio n

Setup time 400 kHz mode 600 — —

SP91* THD:STA Start condition 100 kHz mode 4000 — — ns After this period, the first

clock pulse is generated

Hold time 400 kHz mode 600 — —

SP92* TSU:STO Stop condition 100 kHz mo de 4700 — — ns

Setup time 400 kHz mode 600 — —

SP93 THD:STO Stop condition 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

Note: Refer to Figure 23-2 for load conditions.

SP90

SP91 SP92

SP100 SP101

SP103

SP106 SP107

SP109 SP109 SP110

SP102

SCL

SDA

Out

PIC16(L)F722/3/4/6/7

DS40001341F-page 226  2007-2015 Microchip Technology Inc.

TABLE 23-13: I2C BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min. Max. Units Conditions

SP100* THIGH Clock high time 100 kHz mode 4.0 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — s Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

SP101* TLOW Clock low time 100 kHz mode 4.7 — s Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — s Device must operate at a

minimum of 10 MHz

SSP Module 1.5TCY —

SP102* TRSDA and SCL rise

time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1CB300 ns CB is specified to be from

10-400 pF

SP103* TFSDA and SCL fall time 100 kHz mode — 250 ns

400 kHz mode 20 + 0.1CB250 ns CB is specified to be from

10-400 pF

SP106* THD:DAT Data input hold time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

SP109* TAA Output valid from

clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

SP110* TBUF Bus free time 100 kHz mode 4.7 — s T ime the bus must be free

before a new transmission

can start

400 kHz mode 1.3 — s

SP111 CBBus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement

TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of

the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA

line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the S tandard mode I2C bus specification), before the SCL

line is released.

 2007-2015 Microchip Technology Inc. DS40001341F-page 227

PIC16(L)F722/3/4/6/7

TABLE 23-14: CAP SENSE OSCILLATOR SPECIFICATIONS

FIGURE 23-22: CAP SENSE OSCILLATOR

Param.

No. Symbol Characteristic Min. Typ† Max. Units Conditions

CS01 ISRC Current Source High — -5.8 -6 A-40, -85°C

Medium — -1.1 -3.2 A

Low — -0.2 -0.9 A

CS02 ISNK Current Sink High — 6.6 6 A-40, -85°C

Medium — 1.3 3.2 A

Low — 0.24 0.9 A

CS03 VCHYST Cap Hys tere sis High — 525 — mV VCTH-VCTL

Medium — 375 — mV

Low — 280 — mV

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

ISRC

VCTH

VCTL

ISNK

EnabledEnabled

PIC16(L)F722/3/4/6/7

DS40001341F-page 228  2007-2015 Microchip Technology Inc.

24.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS

FIGURE 24-1: PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, EC MO DE, VCAP = 0.1 µF

FIGURE 24-2: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE

1.8V

2.5V

3.6V

0.00

200.00

400.00

600.00

800.00

1,000.00

1,200.00

1,400.00

1,600.00

1,800.00

2,000.00

2,200.00

1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz

VDD (V)

Typic al: Sta tisti ca l Mean @25°C

Maximum: Mea n (Worst -Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

1.8V

2.5V

3.3V

3.6V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2,200

2,400

1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MH z

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(- 40°C to 125°C)

FOSC

IDD (µA)

 2007-2015 Microchip Technology Inc. DS40001341F-page 229

PIC16(L)F722/3/4/6/7

FIGURE 24-3: PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1 µF

FIGURE 24-4: PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, EC MODE

1.8V

2.5V

3.6V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz

Typica l : Stati stica l Mean @ 25° C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

FOSC

IDD (µA)

1.8V

2.5V

3.3V

3.6V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2,200

1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

PIC16(L)F722/3/4/6/7

DS40001341F-page 230  2007-2015 Microchip Technology Inc.

FIGURE 24-5: PIC16F722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE,

VCAP = 0.1 µF

FIGURE 24-6: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE

1 MHz

4 MHz

100

200

300

400

500

600

1.8 2 2.5 3 3.3 3.6 4.2 4.5 5

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40 °C to 125°C)

IDD (µA)

VDD (V)

1 MHz

4 MHz

100

150

200

250

300

350

400

450

500

1.8 2 2.5 3 3.3 3.6

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 231

PIC16(L)F722/3/4/6/7

FIGURE 24-7: PIC16F722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE,

VCAP = 0.1 µF

FIGURE 24-8: PIC16LF722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE

1 MHz

4 MHz

100

150

200

250

300

350

400

450

1.8 2 2.5 3 3.3 3.6 4.2 4.5 5

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

VDD (V)

IDD (µA)

1 MHz

4 MHz

100

150

200

250

300

350

400

450

1.8 2 2.5 3 3.3 3.6

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

VDD (V)

IDD (µA)

PIC16(L)F722/3/4/6/7

DS40001341F-page 232  2007-2015 Microchip Technology Inc.

FIGURE 24-9: PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, HS MO DE, VCAP = 0.1 µF

FIGURE 24-10: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE

3.6V

4.5V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

Fosc

IDD (mA)

2.5V

3.6V

0.00

0.50

1.00

1.50

2.00

2.50

4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Fosc

IDD (mA)

3.3V

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PIC16(L)F722/3/4/6/7

FIGURE 24-11: PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1 µF

FIGURE 24-12: PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, HS MODE

3.6V

4.5V

0.00

0.50

1.00

1.50

2.00

4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Fosc

IDD (mA)

2.5V

3.3V

0.00

0.50

1.00

1.50

2.00

2.50

4 MHz 6 MHz 8 MHz 10 MH z 13 MHz 16 MHz 20 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (mA)

Fosc

3.6V

PIC16(L)F722/3/4/6/7

DS40001341F-page 234  2007-2015 Microchip Technology Inc.

FIGURE 24-13: PIC16F722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1 µF

FIGURE 24-14: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE

1 MHz

4 MHz

100

200

300

400

500

600

1.8 2 2.5 3 3.3 3.6 4.2 4.5 5

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

1 MHz

4 MHz

100

200

300

400

500

600

1.8 2 2.5 3 3.3 3.6

IDD (µA)

Typical: St atistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 235

PIC16(L)F722/3/4/6/7

FIGURE 24-15: PIC16F722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1 µF

FIGURE 24-16: PIC16LF722/3/4/6/7 TYPICAL IDD vs. VDD OVER FOSC, XT MODE

1 MHz

4 MHz

100

200

300

400

500

600

1.8 2 2.5 3 3.3 3.6 4.2 4.5 5

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

1 MHz

4 MHz

100

200

300

400

500

600

1.8 2 2.5 3 3.3 3.6

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 236  2007-2015 Microchip Technology Inc.

FIGURE 24-17 : PIC16F72 2/3 /4/6/ 7 IDD vs. VDD, LP MODE, VCAP = 0.1 µF

FIGURE 24-18 : PIC16LF72 2/3/ 4/6/7 IDD vs. VDD, LP MODE

32 kHz Typical

32 kHz Maximum

10.0

12.5

15.0

17.5

20.0

1.8 3 5

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

32 kHz Typical

32 kHz Maximum

1.8 3 3.3 3.6

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 237

PIC16(L)F722/3/4/6/7

FIGURE 24-19: PIC16F722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE,

VCAP = 0.1 µF

FIGURE 24-20: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE

110

120

130

140

150

160

170

180

190

200

210

62.5 kHz 125 kHz 250 kHz 500 kHz

3.6V

1.8V

2.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

FOSC

IDD (µA)

1.8V

2.5V

3.6V

100

110

120

130

140

150

160

170

62.5 KHz 125 KHz 250 KHz 500 KHz

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

FOSC

IDD (µA)

PIC16(L)F722/3/4/6/7

DS40001341F-page 238  2007-2015 Microchip Technology Inc.

FIGURE 24-21 : PIC16F72 2/3 /4/6/ 7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP =1µF

FIGURE 24-22: PIC16LF722/3/4/6/7 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2 MHz 4 MHz 8 MHz 16 MHz

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

1.8V

2.5V

3.6V

1.8V

2.5V

3.6V

250

500

750

1,000

1,250

1,500

1,750

2,000

2,250

2 MHz 4 MHz 8 MHz 16 MHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

 2007-2015 Microchip Technology Inc. DS40001341F-page 239

PIC16(L)F722/3/4/6/7

FIGURE 24-23 : PIC16F72 2/3 /4/6/ 7 TY PICA L IDD vs. FOSC OVE R VDD, INTOSC MODE, VCAP =0.1µF

FIGURE 24-24: PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE

1.8V

2.5V

3.6V

100

110

120

130

140

150

160

62.5 kHz 125 kHz 250 kHz 500 kHz

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

3.6V

1.8V

2.5V

100

110

120

130

140

62.5 kHz 125 kHz 250 kHz 500 kHz

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

PIC16(L)F722/3/4/6/7

DS40001341F-page 240  2007-2015 Microchip Technology Inc.

FIGURE 24-25: PIC16F722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE,

VCAP = 0.1 µF

FIGURE 24-26: PIC16LF722/3/4/6/7 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE

1.8V

2.5V

3.6V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2 MHz 4 MHz 8 MHz 16 MHz

Typical: Statistical Mean @25°C

Maximu m: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

FOSC

3.6V

1.8V

2.5V

200

400

600

800

1,000

1,200

1,400

1,600

1,800

2,000

2 MHz 4 MHz 8 MHz 16 MHz

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IDD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 241

PIC16(L)F722/3/4/6/7

FIGURE 24-27: PIC16F722/3/4/6/7 MAXIMUM BASE IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-28: PIC16LF722/3/4/6/7 MAXIMUM BASE IPD vs. VDD

85°C

125°C

1.8V 2V 3V 3.6V 4V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

125°C

85°C

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 242  2007-2015 Microchip Technology Inc.

FIGURE 24-29 : PIC16F72 2/3 /4/6/ 7 TYPICAL BASE IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-30: PIC16LF722/3/4/6/7 TYPICAL BASE IPD vs. VDD

25°C

1.8V 2V 3V 3.6V 4V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

25°C

100

150

200

250

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (nA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 243

PIC16(L)F722/3/4/6/7

FIGURE 24-31 : PIC16F722/3 /4/6/7 FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-32 : PIC16LF72 2/3/ 4/6/7 FIXED VOLTAGE REFERENCE IPD vs. VDD

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maxi mum: Mean (Wors t-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 2.5V 3V 3.6V

Typica l: Stati stica l Mean @ 25° C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 244  2007-2015 Microchip Technology Inc.

FIGURE 24-33: PIC16F722/3/4/6/7 BOR IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-34: PIC16LF722/3/4/6/7 BOR IPD vs. VDD

Typ. 25°C

Max. 125°C

Max. 85°C

2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 125°C

Max. 85°C

2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 245

PIC16(L)F722/3/4/6/7

FIGURE 24-35: PIC16F722/3/4/6/7 CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-36: PIC16LF722/3/4/6/7 CAP SENSE HIGH POWER IPD vs. VDD

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 246  2007-2015 Microchip Technology Inc.

FIGURE 24-37: PIC16F722/3/4/6/7 CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-38: PIC16LF722/3/4/6/7 CAP SENSE MEDIUM POWER IPD vs. VDD

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(- 40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 247

PIC16(L)F722/3/4/6/7

FIGURE 24-39: PIC16F722/3/4/6/7 CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-40: PIC16LF722/3/4/6/7 CAP SENSE LOW POWER IPD vs. VDD

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 125°C

Max. 85°C

1.8V 2V 2.5V 3V 3.6V

Typical: St atistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40 °C to 125°C)

IPD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 248  2007-2015 Microchip Technology Inc.

FIGURE 24-41: PIC16F722/3/4/6/7 T1OSC 32 KHZ IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-42: PIC16LF722/3/4/6/7 T1OSC 32 kHz IPD vs. VDD

Typ. 25° C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ.

Max. 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 249

PIC16(L)F722/3/4/6/7

FIGURE 24-43: PIC16F722/3/4/6/7 TYPICAL ADC IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-44: PIC16LF722/3/4/6/7 TYPICAL ADC IPD vs. VDD

Typ. 25°C

5.0

5.5

6.0

6.5

7.0

7.5

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

100

150

200

250

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maxim um: Mean (Wor st -C ase Tem p) + 3

(-40°C to 125°C)

IPD (nA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 250  2007-2015 Microchip Technology Inc.

FIGURE 24-45: PIC16F722/3/4/6/7 ADC IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-46: PI C16LF72 2/3/ 4/6/ 7 ADC IPD vs. VDD

Max. 85°C

Max. 125°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

Max. 85°C

Max. 125°C

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximu m: Me an (Wor st-C a se Temp ) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

 2007-2015 Microchip Technology Inc. DS40001341F-page 251

PIC16(L)F722/3/4/6/7

FIGURE 24-47: PIC16F722/3/4/6/7 WDT IPD vs. VDD, VCAP = 0.1 µF

FIGURE 24-48: PIC16LF722/3/4/6/7 WDT IPD vs. VDD

Typ. 25°C

Max. 85°C

1.8V 2V 3V 3.6V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40 °C to 125°C)

IPD (µA)

VDD (V)

Typ. 25°C

Max. 85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.8V 2V 2.5V 3V 3.6V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

IPD (µA)

VDD (V)

PIC16(L)F722/3/4/6/7

DS40001341F-page 252  2007-2015 Microchip Technology Inc.

FIGURE 24-49: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

FIGURE 24-50: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

Max. -40°

Typ. 25°

Min. 125 °

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.8 3.6 5.5

Maximu m: Me an + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

VIN (V)

VDD (V)

Typical: Mean @25°C

VIHMin. 125°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.8 3.6 5.5

VIN (V)

VDD (V)

VIHMax. -40°C

Maximum: Mean + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

Typi cal: Me an @ 25° C

 2007-2015 Microchip Technology Inc. DS40001341F-page 253

PIC16(L)F722/3/4/6/7

FIGURE 24-51: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

FIGURE 24-52 : VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V

0.0

0.5

1.0

1.5

2.0

2.5

3.0

1.8 3.6 5.5

VIN (V)

VDD (V)

VIL Min. 125°C

VIL Max. -40°C

Maximu m: Mea n + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

Typical: Mean @25°C

Max. -40°

Min. 125°

Typ. 25°

5.1

5.2

5.3

5.4

5.5

5.6

-5.0-4.2-3.4-2.6-1.8-1.0-0.2

Maximum: Mean + 3 (-40°C to 125°C)

Minimu m: Me an - 3  (-40°C to 125°C)

Typical: Mean @25°C

VOH (V)

IOH (mA)

PIC16(L)F722/3/4/6/7

DS40001341F-page 254  2007-2015 Microchip Technology Inc.

FIGURE 24-53 : VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V

FIGURE 24-54 : VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V

2.6

2.8

3.2

3.4

3.6

3.8

-5.0-4.2-3.4-2.6-1.8-1.0-0.2

Maxi mum: Mean + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

Typical: Mean @25°C

VOH (V)

IOH (mA)

Max. -40°

Typ. 25°

Min. 125°

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-2.0-1.8-1.6-1.4-1.2-1.0-0.8-0.6-0.4-0.20.0

VOH (V)

IOH (mA)

Max. -40°

Typ. 25°

Min. 125°

Maxi mum: Mean + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

Typi cal: Me an @ 25° C

 2007-2015 Microchip Technology Inc. DS40001341F-page 255

PIC16(L)F722/3/4/6/7

FIGURE 24-55 : VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V

FIGURE 24-56 : VOL vs. IOL OVER TEMPERATURE, VDD = 3.6V

Min. -40°

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

5.0 6.0 7.0 8.0 9.0 10.0

VOL (V)

IOL (mA )

Max. 125°

Typ. 25°

Maxi mum: Mean + 3 (-40°C to 125°C)

Minimum: Me an - 3 (-40°C to 125°C)

Typical: Mean @25°C

Min. -40°

Typ. 25°

Max. 125°

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

4.0 5.0 6.0 7.0 8.0 9.0 10.0

Maximu m: Me an + 3 (-40°C to 125° C)

Minimum: Mean - 3 (-40°C to 125°C)

Typical: Mean @25°C

VOL (V)

IOL (mA)

PIC16(L)F722/3/4/6/7

DS40001341F-page 256  2007-2015 Microchip Technology Inc.

FIGURE 24-57 : VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V

FIGURE 24-58: PIC16F722/3/4/6/7 PWRT PERIOD

0.2

0.4

0.6

0.8

1.2

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8

Maxi mum: Mean + 3 (-40°C to 125°C)

Minimum: Mean - 3 (-40°C to 125°C)

T ypical: Mean @25°C

VOL (V)

IOL (mA)

Max. 125°

Min. -40°

Max. -40°C

Min. 125°C

105

1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V

TIME (ms)

VDD

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

Typ. 25°C

 2007-2015 Microchip Technology Inc. DS40001341F-page 257

PIC16(L)F722/3/4/6/7

FIGURE 24-59: PIC16F722/3/4/6/7 WDT TIME-OUT PERIOD

FIGURE 24-60: PIC16F722/3/4/6/7 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME

Typ. 25°C

Max. -40°C

Min. 125°C

10.00

12.00

14.00

16.00

18.00

20.00

22.00

24.00

1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-Case Temp) + 3

(-40°C to 125°C)

TIME (ms)

VDD

Max.

Typ.

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V

Typical: Statistical Mean @25°C

Maximum: Mea n (Worst-Case Temp) + 3

(-40°C to 125°C)

TIME (us)

VDD

PIC16(L)F722/3/4/6/7

DS40001341F-page 258  2007-2015 Microchip Technology Inc.

FIGURE 24-61: PIC16F722/3/4/6/7 A/D INTERNAL RC OSCILLATOR PERIOD

FIGURE 24-62: PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH

Max.

Min.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

1.8V 3.6V 5.5V

Typical: Statistical Mean @25°C

Maximu m: Me an (Wor st-C a se Temp ) + 3

(-40°C to 125°C)

Period (µs)

VDD(V)

-15000

-10000

-5000

5000

10000

15000

20000

1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5

Current (nA)

VDD(V)

Min. Sink -40°C

Typ. Sink 25°C

Max. Sink 85°C

Min. Source 85°C

Typ. Source 25°C

Max. Source -40°C

 2007-2015 Microchip Technology Inc. DS40001341F-page 259

PIC16(L)F722/3/4/6/7

FIGURE 24-63: PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM

FIGURE 24-64: PIC16F722/3/4/6/7 CAP SENSE OUTPUT CURRENT, POWER MODE = LOW

-3000

-2000

-1000

1000

2000

3000

1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5

Current (nA)

VDD(V)

Max. Sink -40°C

Typ. Sink 25°C

Min. Sink 85°C

Min. Sourc e 85°C

Typ. Source 25°C

Max. Source -40°C

-800

-600

-400

-200

200

400

600

1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5

Curr en t (n A)

VDD(V)

Max. Sink 85°C

Typ. Sink 25°C

Min. Sink -40°C

Min. Source 85°C

Typ. Sour ce 25° C

Max. Source -40°C

PIC16(L)F722/3/4/6/7

DS40001341F-page 260  2007-2015 Microchip Technology Inc.

FIGURE 24-65: PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = HIGH

FIGURE 24-66: PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM

300

400

500

600

700

1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5

Max. 125°C

Max. 85°C

Typ. 25°C

Min. 0°C

Min. -40°C

VDD(V)

250

300

350

400

450

500

550

1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5

Max. 125°C

Typ. 25°C

Min. 0°C

Min. -40°C

VDD(V)

Max. 85°C

 2007-2015 Microchip Technology Inc. DS40001341F-page 261

PIC16(L)F722/3/4/6/7

FIGURE 24-67: PIC16F722/3/4/6/7 CAP SENSOR HYSTERESIS, POWER MODE = LOW

FIGURE 24-68: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V

150

200

250

300

350

400

450

1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5

Max. 125°C

Max. 85°C

Typ. 25°C

Min. 0°C

VDD(V)

Min -40°C

-1.5

-1

-0.5

0.5

1.5

1.8 2.5 3 3.6 4.2 5.5

Voltage

Percent Change (%)

PIC16(L)F722/3/4/6/7

DS40001341F-page 262  2007-2015 Microchip Technology Inc.

FIGURE 24-69: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C

-3

-2.5

-2

-1.5

-1

-0.5

0.5

1.5

-40 0 45 85 125

Temperature (°C)

Percent C ha ng e (%)

 2007-2015 Microchip Technology Inc. DS40001341F-page 263

PIC16(L)F722/3/4/6/7

25.0 PACKAGING INFORMATION

25.1 Package Marking Info rmation

*Standard PICmicro® device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Legend: XX...X Customer-specific info rma tio n

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calen dar ye ar)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC® designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microc hip p art num ber cann ot be mar ked on on e line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific informatio n.

28-Lead SPDIP

XXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F722

0810017

-I/SP

40-Lead PDIP

XXXXXXXXXXXXXXXXXX

YYWWNNN

Example

PIC16F724

0810017

-I/P

Example

28-Lead QFN/UQFN

XXXXXXXX

YYWWNNN

16F722

-I/ML

0810017

PIC16(L)F722/3/4/6/7

DS40001341F-page 264  2007-2015 Microchip Technology Inc.

Package Marking Information (Continued)

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

Example

0810017

28-Lead SSOP

XXXXXXXXXXXX

YYWWNNN

Example

PIC16F722

0810017

XXXXXXXXXX

44-Lead QF N

XXXXXXXXXX

YYWWNNN

Example

PIC16F724

-I/ML

0810017

44-Lead TQFP

XXXXXXXXXXX

YYWWNNN

Example

PIC16F727

0810017

-I/SO

PIC16F722

-I/SS

-I/PT

 2007-2015 Microchip Technology Inc. DS40001341F-page 265

PIC16(L)F722/3/4/6/7

25.2 Package Details

The following sections give the technical details of the packages.

/HDG6NLQQ\3ODVWLF'XDO,Q/LQH63±PLO%RG\>63',3@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 6LJQLILFDQW&KDUDFWHULVWLF

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV ,1&+(6

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

7RSWR6HDWLQJ3ODQH $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

%DVHWR6HDWLQJ3ODQH $  ± ±

6KRXOGHUWR6KRXOGHU:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

7LSWR6HDWLQJ3ODQH /   

/HDG7KLFNQHVV F   

8SSHU/HDG:LGWK E   

/RZHU/HDG:LGWK E   

2YHUDOO5RZ6SDFLQJ H% ± ± 

NOTE 1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F722/3/4/6/7

DS40001341F-page 266  2007-2015 Microchip Technology Inc.

/HDG3ODVWLF'XDO,Q/LQH3±PLO%RG\>3',3@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 6LJQLILFDQW&KDUDFWHULVWLF

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV ,1&+(6

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

7RSWR6HDWLQJ3ODQH $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± 

%DVHWR6HDWLQJ3ODQH $  ± ±

6KRXOGHUWR6KRXOGHU:LGWK (  ± 

0ROGHG3DFNDJH:LGWK (  ± 

2YHUDOO/HQJWK '  ± 

7LSWR6HDWLQJ3ODQH /  ± 

/HDG7KLFNQHVV F  ± 

8SSHU/HDG:LGWK E  ± 

/RZHU/HDG:LGWK E  ± 

2YHUDOO5RZ6SDFLQJ H% ± ± 

NOTE 1

123

A1 b1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

 2007-2015 Microchip Technology Inc. DS40001341F-page 267

PIC16(L)F722/3/4/6/7

/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@

ZLWKPP&RQWDFW/HQJWK

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 3DFNDJHLVVDZVLQJXODWHG

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $   

6WDQGRII $   

&RQWDFW7KLFNQHVV $ 5()

2YHUDOO:LGWK ( %6&

([SRVHG3DG:LGWK (   

2YHUDOO/HQJWK ' %6&

([SRVHG3DG/HQJWK '   

&RQWDFW:LGWK E   

&RQWDFW/HQJWK /   

&RQWDFWWR([SRVHG3DG .  ± ±

DEXPOSED D2

NOTE 1

TOP VIEW BOTTOM VIEW

PAD

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F722/3/4/6/7

DS40001341F-page 268  2007-2015 Microchip Technology Inc.

/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@

ZLWKPP&RQWDFW/HQJWK

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

 2007-2015 Microchip Technology Inc. DS40001341F-page 269

PIC16(L)F722/3/4/6/7

/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 3DFNDJHLVVDZVLQJXODWHG

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $   

6WDQGRII $   

&RQWDFW7KLFNQHVV $ 5()

2YHUDOO:LGWK ( %6&

([SRVHG3DG:LGWK (   

2YHUDOO/HQJWK ' %6&

([SRVHG3DG/HQJWK '   

&RQWDFW:LGWK E   

&RQWDFW/HQJWK /   

&RQWDFWWR([SRVHG3DG .  ± ±

DEXPOSED

PAD

NOTE 1

BOTTOM VIEW

TOP VIEW

A3 A1

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F722/3/4/6/7

DS40001341F-page 270  2007-2015 Microchip Technology Inc.

/HDG3ODVWLF4XDG)ODW1R/HDG3DFNDJH0/±[PP%RG\>4)1@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

 2007-2015 Microchip Technology Inc. DS40001341F-page 271

PIC16(L)F722/3/4/6/7

/HDG3ODVWLF6PDOO2XWOLQH62±:LGHPP%RG\>62,&@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 6LJQLILFDQW&KDUDFWHULVWLF

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $  ± ±

6WDQGRII $  ± 

2YHUDOO:LGWK ( %6&

0ROGHG3DFNDJH:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

&KDPIHURSWLRQDO K  ± 

)RRW/HQJWK /  ± 

)RRWSULQW / 5()

)RRW$QJOH7RS  ± 

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E  ± 

0ROG'UDIW$QJOH7RS  ± 

0ROG'UDIW$QJOH%RWWRP  ± 

NOTE 1

123

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F722/3/4/6/7

DS40001341F-page 272  2007-2015 Microchip Technology Inc.

/HDG3ODVWLF6KULQN6PDOO2XWOLQH66±PP%RG\>6623@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI3LQV 1 

3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± ±

2YHUDOO:LGWK (   

0ROGHG3DFNDJH:LGWK (   

2YHUDOO/HQJWK '   

)RRW/HQJWK /   

)RRWSULQW / 5()

/HDG7KLFNQHVV F  ± 

)RRW$QJOH   

/HDG:LGWK E  ± 

NOTE 1 b

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

 2007-2015 Microchip Technology Inc. DS40001341F-page 273

PIC16(L)F722/3/4/6/7

/HDG3ODVWLF7KLQ4XDG)ODWSDFN37±[[PP%RG\PP>74)3@

1RWHV

 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD

 &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\

 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH

 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0

%6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV

5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

8QLWV 0,//,0(7(56

'LPHQVLRQ/LPLWV 0,1 120 0$;

1XPEHURI/HDGV 1 

/HDG3LWFK H %6&

2YHUDOO+HLJKW $ ± ± 

0ROGHG3DFNDJH7KLFNQHVV $   

6WDQGRII $  ± 

)RRW/HQJWK /   

)RRWSULQW / 5()

)RRW$QJOH   

2YHUDOO:LGWK ( %6&

2YHUDOO/HQJWK ' %6&

0ROGHG3DFNDJH:LGWK ( %6&

0ROGHG3DFNDJH/HQJWK ' %6&

/HDG7KLFNQHVV F  ± 

/HDG:LGWK E   

0ROG'UDIW$QJOH7RS   

0ROG'UDIW$QJOH%RWWRP   

NOTE 1 NOTE 2

123

0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &%

PIC16(L)F722/3/4/6/7

DS40001341F-page 274  2007-2015 Microchip Technology Inc.

/HDG3ODVWLF7KLQ4XDG)ODWSDFN37±[[PP%RG\PP>74)3@

1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW

KWWSZZZPLFURFKLSFRPSDFNDJLQJ

 2007-2015 Microchip Technology Inc. DS40001341F-page 275

PIC16(L)F722/3/4/6/7

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

PIC16(L)F722/3/4/6/7

DS40001341F-page 276  2007-2015 Microchip Technology Inc.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2007-2015 Microchip Technology Inc. DS40001341F-page 277

PIC16(L)F722/3/4/6/7

APPENDIX A: DATA SHEE T

REVISION HISTORY

Revision A (12/2007)

Original release.

Revision B (08/2008)

Electrical Specification updates; Package Drawings;

miscellaneous updates.

Revision C (04/2009)

Revised data sheet title; Revised Low-Power Features

section; Revised Section 6.2.2.4 RA3/AN3/VREF;

Revised Figure 16-8 Synchronous Reception.

Revision D (07/2009)

Removed the Preliminary Label; Updated the

“Electrical Characteristics” section; Added charts in the

“Char. Data” section; Deleted “Based 8-Bit CMOS”

from title; Updated the “Special Microcontroller

Features” section and the “Peripheral Features”

sectio n; Changed the title of the “Low Power Fea tures”

section into “Extreme Low-Power Management

PIC16LF72X with nanoWatt XLP” and updated this

section; Inserted new section – “Analog Features”

(page 1); Chang ed the title of th e “Peripheral Features”

section into “Peripheral Highlights” and updated the

section.

Revision E (10/2009)

Added paragraph to section 5.0 (LDO Voltage

Regulator); Updated the Electrical Specifications

section (Added another absolute Maximum Rating;

Update d section 23.1 an d Table 23-4); Updat ed the Pin

Diagrams with the UQFN package; Updated Table 1,

adding UQFN; Updated section 23.5 (Thermal

Considerations); Updated the Packaging Information

section adding the UQFN Package; Updated the

Product Identification System section.

Revision F (12/2015)

Updated Table 2; Updated 23.1, 23.3 and 9.2.4

Sections; Updated Figure 23-9; Other minor

corrections.

APPENDIX B: MIGRATING FROM

OTHER PIC®

DEVICES

This discusses some of the issues in migrating from

other PIC® devices to the PIC16F72X family of

devices.

B.1 PIC16F77 to PIC16F72X

TABLE B-1: FEATURE COMPARISON

Feature PIC16F77 PIC16F727

Max. Operating Speed 20 MHz 20 MHz

Max. Program

Memory (Words) 8K 8K

Max. SRAM (Bytes) 368 368

A/D Resolution 8-bit 8-bit

Timers (8/16-bit) 2/1 2/1

Oscillator Modes 4 8

Brown-out Reset Y Y

Internal Pull -up s RB<7:0> RB<7:0>

Interrupt-on-change RB<7:4> RB<7:0>

Comparator 0 0

USART Y Y

Extended WDT N N

Software Control

Option of WDT/BOR NN

INTOSC Frequencies None 500 kH z -

16 MHz

Clock Switch in g N N

PIC16(L)F722/3/4/6/7

DS40001341F-page 278  2007-2015 Microchip Technology Inc.

THE MICROCHIP WEBSITE

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser , the website contains t he following information:

•Product Support – Da ta sheets an d errata, a ppl i-

cation note s and samp le prog ram s, des ig n

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchi p con su lt an t

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

change s, updates, rev isions or errat a related to a s pec-

ified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sal es Office

• Field Application Engineer (FAE)

• Technical Support

Cust omers should contact their distributor, representa-

tive or Field Application Engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A l isting of sal es offic es and locat ions is inc luded in

the back of this document.

Technical support is available through the website

at: http://www.microchip.com/support

 2007-2015 Microchip Technology Inc. DS40001341F-page 279

PIC16(L)F722/3/4/6/7

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: PIC16F722, PIC16LF722, PIC16F722T, PIC16LF722T(1)

PIC16F723, PIC16LF723, PIC16F723T, PIC16LF723T(1)

PIC16F724, PIC16LF724, PIC16F724T, PIC16LF724T(1)

PIC16F726, PIC16LF726, PIC16F726T, PIC16LF726T(1)

PIC16F727, PIC16LF727, PIC16F727T, PIC16LF727T(1)

Tape and Reel

Option: I= -40C to +85C

E= -40C to +125C

MV = Micro Lead Frame (UQFN)

Temperature

Range: I= -40C to +85C (Industrial)

E= -40C to +125C (Extended)

Package: ML = Micro Lead Fr ame (QFN)

P = Plastic DIP

PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic DIP

SS = SSOP

Examples:

a) PIC16F722-E/SP 301 = Extended Temp.,

skinny PDIP package, QTP pattern #301

b) PIC16F722-I/SO = Industrial Temp., SOIC

package

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package. Check

with your Microchip Sales Office for package

availability with the Tape and Reel option.

[X](1)

Tape and Reel

Option

PIC16(L)F722/3/4/6/7

DS40001341F-page 280  2007-2015 Microchip Technology Inc.

NOTES:

 2007-2015 Microchip Technology Inc. DS40001341F-page 281

Information contained in this publication regarding device

applications a nd the lik e is provid ed only for your convenien ce

and may be supers ed ed by u pdates. I t is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer ,

LANCheck, MediaLB, MOST, MOST logo, MPLAB,

OptoL yzer , PIC, PICSTART, PIC32 logo, RightTouch, S pyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered

trademarks of Microchip Te chnology Incorporat ed in the

U.S.A. and other countries.

The Embedded Control Solutions Company and mTouch are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,

CodeGuard, dsPICDEM, dsP ICDEM. net, ECA N, In-Circuit

Serial Programming, ICSP, Inter-Chip Connectivity , KleerNet,

KleerNet logo, MiWi, motorBenc h, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,

Total Endurance, TSHARC, USBCheck, VariSense,

ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Te chnology Incorporat ed in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology I nc. in other countries.

GestIC is a registered trademark of Microchip Tec hnolo gy

Germany II GmbH & Co. KG, a subsidiar y of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-0042-4

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Mic rochip Data Sheet.

• Microchip believes that its f amily of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS40001341F-page 282  2007-2015 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Techn ical Support:

http://www.microchip.com/

support

Web Address:

www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

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Tel: 512-257-3370

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Tel: 774-760-0087

Fax: 774-760-0088

Chicago

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Tel: 630-285-0071

Fax: 630-285-0075

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Tel: 216-447-0464

Fax: 216-447-0643

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Tel: 972-818-7423

Fax: 972-818-2924

Detroit

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Tel: 248-848-4000

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Tel: 281-894-5983

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Tel: 317-773-8323

Fax: 317-773-5453

Los A n ge les

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

Canada - Toronto

Tel: 905-673-0699

Fax: 905-673-6509

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-67 33

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8569-7 000

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5 511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9 588

Fax: 86-23-8980-9500

China - Dongguan

Tel: 86-769-8702-9880

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2 460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5 533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2 829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5 300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7 252

Fax: 86-29-8833-7256

ASIA/PACIFIC

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-3019-1500

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Taiwan - T aipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Cop e nha gen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53 -63-20

Fax: 33-1-69-30-90-79

Germany - Dusseldorf

Tel: 49-2129-37664 00

Germany - Karlsruhe

Tel: 49-721-625370

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Italy - Venice

Tel: 39-049-762528 6

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Poland - Warsaw

Tel: 48-22-3325737

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

Sweden - Stockholm

Tel: 46-8-5090-4654

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Worldwide Sales and Service

07/14/15