BLOCK DIAGRAM
1
June 1998
PRELIMINARY
ML65F16241
16-Bit Buffer/Line Driver with 3-State Outputs
GENERAL DESCRIPTION
The ML65F16241 is a BiCMOS, 16-bit buffer/line driver
with 3-state outputs. This device was specifically designed
for high speed bus applications. Its 16 channels support
propagation delay of 2ns maximum, and fast output
enable and disable times of 5ns or less to minimize
datapath delay.
This device is designed to minimize undershoot,
overshoot, and ground bounce to decrease noise delays.
These transceivers implement a unique digital and analog
implementation to eliminate the delays and noise
inherent in traditional digital designs. The device offers a
new method for quickly charging up a bus load capacitor
to minimize bus settling times, or FastBus™ Charge.
FastBus Charge is a transition current, (specified as
IDYNAMIC) that injects between 60 to 200mA (depending
on output load) of current during the rise time and fall
time. This current is used to reduce the amount of time it
takes to charge up a heavily-capacitive loaded bus,
effectively reducing the bus settling times, and
improving data/clock margins in tight timing budgets.
Micro Linear’s solution is intended for applications for
critical bus timing designs that include minimizing
device propagation delay, bus settling time, and time
delays due to noise. Applications include; high speed
memory arrays, bus or backplane isolation, bus to bus
bridging, and sub-2ns propagation delay schemes.
The ML65F16241 follows the pinout and functionality of
the industry standard 2.7V to 3.6V-logic families.
FEATURES
■Low propagation delays — 2ns maximum for 3.3V,
2.5ns maximum for 2.7V
■Fast output enable/disable times of 5ns maximum
■FastBus Charge current to minimize the bus settling
time during active capacitive loading
■2.7V to 3.6V VCC supply operation; LV-TTL compatible
input and output levels with 3-state capability
■Industry standard pinout compatible to FCT, ALV, LCX,
LVT, and other low voltage logic families
■ESD protection exceeds 2000V
■Full output swing for increased noise margin
■Undershoot and overshoot protection to 400mV
typically
■Low ground bounce design
VCC
GND
1Ai, 4Ai
1Bi, 4Bi
1OE, 4OE
2Ai, 3Ai
2Bi, 3Bi
i = 0 to 3
2OE, 3OE
ML65F16241
2
PIN CONFIGURATION
FUNCTION TABLE
(Each 4-bit section)
INPUTS OUTPUTS
1OE, 4OE 1Ai, 4Ai 1Bi, 4Bi
LHH
LLL
HXZ
INPUTS OUTPUTS
2OE, 3OE 2Ai, 3Ai 2Bi, 3Bi
HHH
HLL
LXZ
L = Logic Low, H = Logic High, X = Don’t Care, Z = High Impedance
i = 0 to 3
2OE
1A0
1A1
GND
1A2
1A3
VCC
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
VCC
4A0
4A1
GND
4A2
4A3
3OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1OE
1B0
1B1
GND
1B2
1B3
VCC
2B0
2B1
GND
2B2
2B3
3B0
3B1
GND
3B2
3B3
VCC
4B0
4B1
GND
4B2
4B3
4OE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TOP VIEW
ML65F16241
48-Pin SSOP (R48)
48-Pin TSSOP (T48)
ML65F16241
3
PIN DESCRIPTION
PIN NAME FUNCTION
11OE Output Enable Active Low
2 1B0 Data Output
3 1B1 Data Output
4 G ND Signal Ground
5 1B2 Data Output
6 1B3 Data Output
7V
CC 2.7V to 3.6V Supply
8 2B0 Data Output
9 2B1 Data Output
1 0 G ND Signal Ground
11 2B2 Data Output
12 2B3 Data Output
13 3B0 Data Output
14 3B1 Data Output
1 5 G ND Signal Ground
16 3B2 Data Output
17 3B3 Data Output
18 VCC 2.7V to 3.6V Supply
19 4B0 Data Output
20 4B1 Data Output
2 1 G ND Signal Ground
22 4B2 Data Output
23 4B3 Data Output
24 4OE Output Enable Active Low
PIN NAME FUNCTION
25 3OE Output Enable Active High
26 4A3 Data Input
27 4A2 Data Input
2 8 G ND Signal Ground
29 4A1 Data Input
30 4A0 Data Input
31 VCC 2.7V to 3.6V Supply
32 3A3 Data Input
33 3A2 Data Input
3 4 G ND Signal Ground
35 3A1 Data Input
36 3A0 Data Input
37 2A3 Data Input
38 2A2 Data Input
3 9 G ND Signal Ground
40 2A1 Data Input
41 2A0 Data Input
42 VCC 2.7V to 3.6V Supply
43 1A3 Data Input
44 1A2 Data Input
4 5 G ND Signal Ground
46 1A1 Data Input
47 1A0 Data Input
48 2OE Output Enable Active High
ML65F16241
4
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
VCC ..................................................................................................7V
DC Input Voltage............................. –0.3V to VCC + 0.3V
AC Input Voltage (PW < 20ns) ................................ –3.0V
DC Output Voltage...................................–0.3V to 7VDC
Output Current, Source or Sink (AC)..................... 180mA
Storage Temperature Range ..................... –65°C to 150°C
Junction T emperature..............................................150°C
Lead Temperature (Soldering, 10sec) ......................150°C
Thermal Impedance (θJA)..................................... 76°C/W
OPERATING CONDITIONS
Temperature Range .......................................0°C to 70°C
VIN Operating Range ................................... 2.7V to 3.6V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = 3.3V, TA = Operating Temperature Range (Note 1).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF)
tPHL, tPLH Propagation Delay Ai to Bi 3.3V 1.35 1.7 2 ns
2.7V 1.25 1.9 2.5 ns
tOE Output Enable Time OE to Ai/Bi 3.3V 5 ns
2.7V 6 ns
DIR to Ai/Bi 3.3V 5 ns
2.7V 6 ns
tOD Output Disable Time OE to Ai/Bi 3.3V 5 ns
2.7V 6 ns
DIR to Ai/Bi 3.3V 5 ns
2.7V 6 ns
TOS Output-to-Output Skew 300 ps
CIN Input Capacitance 5pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open)
VIH Input High Voltage Logic high 2.0 V
VIL Input Low Voltage Logic low 0.8 V
IIH Input High Current Per pin, VIN = 3V 300 mA
IIL Input Low Current Per pin, VIN = 0V 300 mA
IHI-Z Three-State Output Current VCC = 3.6V, 0 < VIN < VCC 5mA
VIC Input Clamp Voltage VCC = 3.6V, IIN = 18mA –0.7 –0.2 V
IDYNAMIC Dynamic Transition Current Low to high transitions 80 mA
(FastBus Charge) High to low transitions 80 mA
VOH Output High Voltage VCC = 3.6V 2.4 3.4 V
VCC = 2.7V 2.25 2.35 V
VOL Output LowVoltage VCC = 2.7V and 3.6V 0.6 V
ICC Quiescent Power Supply Current VCC = 3.6V, f = 0Hz, 3 µA
Inputs = VCC or 0V
ML65F16241
5
Figure 1a. Typical VOL vs. IOL for 3.3V VCC.
One Buffer Output
Figure 1b. Typical VOH vs. IOH for 3.3V VCC.
One Buffer Output
100
80
60
40
20
0
IOL (mA)
VOL (V)
0 0.8 1.6 2
0.4 1.2
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
–200
IOH (mA)
VOH (V)
1.8 2.2 2.6 3.63.2
2.0 2.4 3.42.8 3.0
Figure 2a. Propagation Delay vs. Load Capacitance:
3.3V, 50MHZ
Figure 2b. Propagation Delay vs. Load Capacitance:
2.7V, 50MHZ
Figure 3a. ICC vs. Frequency: VCC = VIN = 3.3V.
One Buffer Output
Figure 3b. ICC vs. Frequency: VCC = VIN = 2.7V.
One Buffer Output
tPHL (ns)
LOAD CAPACITANCE (pF)
3.0
2.5
2.0
1.5
1.0
0.5
0050
25 75
VCC = 3.3V
VCC = 2.7V
tPLH (ns)
LOAD CAPACITANCE (pF)
3.0
2.5
2.0
1.5
1.0
0.5
0050
25 75
VCC = 3.3V
VCC = 2.7V
60
50
40
30
20
10
0
ICC (mA)
FREQUENCY (MHz)
0 40 60 100
8020
30pF
50pF
75pF
60
50
40
30
20
10
0
ICC (mA)
FREQUENCY (MHz)
04060100
8020
30pF
50pF
75pF
ML65F16241
6
FUNCTIONAL DESCRIPTION
Figure 4. Logic Diagram
Figure 5. Logic Symbol
1A0
1OE
1B1
1B0
1A1
1B2
1A2
1B3
1A3
2A0
2OE
2B1
2B0
2A1
2B2
2A2
2B3
2A3
3A0
3OE
3B1
3B0
3A1
3B2
3A2
3B3
3A3
4A0
4OE
4B1
4B0
4A1
4B2
4A2
4B3
4A3
1A0
1B0
1A1
1B1
1A2
1B2
1A3
1B3
2A0 2A1 2A2 2A3 3A0 3A1 3A2 3A3 4A0 4A1 4A2 4A3
2B0 2B1 2B2 2B3 3B0 3B1 3B2 3B3 4B0 4B1 4B2 4B3
3OE
4OE
2OE
1OE
ML65F16241
7
ARCHITECTURAL DESCRIPTION
The ML65F16241 is a 16-bit buffer/line driver with 3-state
outputs designed for 2.7V to 3.6V VCC operation. This
device is designed for Quad-Nibble, Dual-Byte memory
interleaving operations. Each bank has an independently
controlled 3-state output enable pin with output enable/
disable access times of less than 7ns. Each bank is
configured to have four independent buffer/line drivers.
Two banks are active high enabled and the other two
banks are active low enabled. Thus making this device
ideal for nibble or byte swapping operations in cache or
main memory designs by toggling between the active low
and active high output enable pins.
Until now, these transceivers were typically implemented
in CMOS logic and made to be TTL compatible by sizing
the input devices appropriately. In order to buffer large
capacitances with CMOS logic, it is necessary to cascade
an even number of inverters, each successive inverter
larger than the preceding, eventually leading to an
inverter that will drive the required load capacitance at
the required frequency. Each inverter stage represents an
additional delay in the gating process because in order for
a single gate to switch, the input must slew more than
half of the supply voltage. The best of these 16-bit CMOS
buffers has managed to drive 50pF load capacitance with
a delay of 3ns.
Micro Linear has produced a 16-bit buffer/line driver with
a delay less than 2ns (3.3V) by using a unique circuit
architecture that does not require cascade logic gates.
The basic architecture of the ML65F16241 is shown in
Figure 6. In this circuit, there are two paths to the output.
One path sources current to the load capacitance where
the signal is asserted, and the other path sinks current
from the output when the signal is negated.
The assertion path is the Darlington pair consisting of
transistors Q1 and Q2. The effect of transistor Q1 is to
increase the current gain through the stage from input to
output, to increase the input resistance and to reduce
input capacitance. During an input low-to-high transition,
the output transistor Q2 sources large amount of current to
quickly charge up a highly capacitive load which in
effect reduces the bus settling time. This current is
specified as IDYNAMIC.
The negation path is also the Darlington pair consisting of
transistor Q3 and transistor Q4. With M1 connecting to
the input of the Darlington pair, Transistor Q4 then sinks a
large amount of current during the input transition from
high-to-low.
Inverter X2 is a helpful buffer that not only drives the
output toward the upper rail but also pulls the output to
the lower rail.
Figure 6. One Buffer Cell of the ML65F16241
OUT
OE
V
CC
M1
IN
X1 X2
Q3
Q4
Q2
Q1
ML65F16241
8
Figure 7. Test Circuits for All Outputs Figure 8. Propagation Delay
V
CC
= 3V
1.5V
0V
3V
1.5V
t
PHL
t
PLH
t
RISE
AND t
FALL
INPUT = 2ns
INPUT
OUTPUT 0V
DISABLEENABLE
CONTROL
INPUT
OUTPUT
LOW
OUTPUT
HIGH
V
CC
= 3V
1.5V
3V
0V
VOL + 0.3V
VOL
VOH
VOH – 0.3V
t
OE
t
OD
t
OD
t
OE
1.5V
1.5V
1.5V
t
OS
INPUT
OUTPUT1
OUTPUTi
i = 1 to 16
Figure 9. Enable and Disable Times Figure 10. Output Skew
50pF
V
OUT
I
OUT
V
IN
ML65F16241
DUT
CIRCUITS AND WAVE FORMS
ML65F16241
9
ML65F16241
10
ML65F16241
11
PHYSICAL DIMENSIONS inches (millimeters)
SEATING PLANE
0.291 - 0.301
(7.39 - 7.65)
0.402 - 0.410
(10.21 - 10.41)
0.620 - 0.630
(15.75 - 16.00)
0.006 - 0.014
(0.15 - 0.36) 0.024 - 0.040
(0.61 - 1.02)
0.094 - 0.110
(2.39 - 2.79)
0.008 - 0.016
(0.20 - 0.41)
0.088 - 0.092
(2.24 - 2.34)
0.005 - 0.010
(0.13 - 0.26)
0º - 8º
48
PIN 1 ID
0.025 BSC
(0.63 BSC)
0.015 - 0.025
(0.38 - 0.64)
(4 PLACES)
1
Package: R48
48-Pin SSOP
Package: T48
48-Pin TSSOP
SEATING PLANE
0.236 - 0.244
(6.00 - 6.20)
0.319 BSC
(8.1 BSC)
0.487 - 0.497
(12.37 - 12.63)
0.007 - 0.011
(0.17 - 0.27)
0.020 BSC
(0.50 BSC)
0.020 - 0.028
(0.50 - 0.70)
0.047 MAX
(1.20 MAX)
0.002 - 0.006
(0.05 - 0.15)
0.031 - 0.039
(0.80 - 1.00)
0.004 - 0.008
(0.10 - 0.20)
0º - 8º
PIN 1 ID
ML65F16241
12
© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653;. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML65F16241CR 0°C to 70°C 48-Pin SSOP (R48)
ML65F16241CT 0°C to 70°C 48-Pin TSSOP (T48)
6/23/98 Printed in U.S.A.
2092 Concourse Driv e
San Jose, CA 95131
Tel: (408) 433-5200
F ax: (408) 432-0295
www.microlinear.com
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