June 1998 PRELIMINARY ML65F16241 16-Bit Buffer/Line Driver with 3-State Outputs GENERAL DESCRIPTION FEATURES The ML65F16241 is a BiCMOS, 16-bit buffer/line driver with 3-state outputs. This device was specifically designed for high speed bus applications. Its 16 channels support propagation delay of 2ns maximum, and fast output enable and disable times of 5ns or less to minimize datapath delay. Low propagation delays -- 2ns maximum for 3.3V, 2.5ns maximum for 2.7V Fast output enable/disable times of 5ns maximum FastBus Charge current to minimize the bus settling time during active capacitive loading 2.7V to 3.6V VCC supply operation; LV-TTL compatible input and output levels with 3-state capability Industry standard pinout compatible to FCT, ALV, LCX, LVT, and other low voltage logic families ESD protection exceeds 2000V Full output swing for increased noise margin Undershoot and overshoot protection to 400mV typically Low ground bounce design This device is designed to minimize undershoot, overshoot, and ground bounce to decrease noise delays. These transceivers implement a unique digital and analog implementation to eliminate the delays and noise inherent in traditional digital designs. The device offers a new method for quickly charging up a bus load capacitor to minimize bus settling times, or FastBusTM Charge. FastBus Charge is a transition current, (specified as IDYNAMIC) that injects between 60 to 200mA (depending on output load) of current during the rise time and fall time. This current is used to reduce the amount of time it takes to charge up a heavily-capacitive loaded bus, effectively reducing the bus settling times, and improving data/clock margins in tight timing budgets. Micro Linear's solution is intended for applications for critical bus timing designs that include minimizing device propagation delay, bus settling time, and time delays due to noise. Applications include; high speed memory arrays, bus or backplane isolation, bus to bus bridging, and sub-2ns propagation delay schemes. The ML65F16241 follows the pinout and functionality of the industry standard 2.7V to 3.6V-logic families. BLOCK DIAGRAM VCC 1OE, 4OE 1Bi, 4Bi 1Ai, 4Ai 2OE, 3OE 2Bi, 3Bi 2Ai, 3Ai GND i = 0 to 3 1 ML65F16241 PIN CONFIGURATION ML65F16241 48-Pin SSOP (R48) 48-Pin TSSOP (T48) 1OE 1 48 2OE 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC 7 42 VCC 2B0 8 41 2A0 2B1 9 40 2A1 GND 10 39 GND 2B2 11 38 2A2 2B3 12 37 2A3 3B0 13 36 3A0 3B1 14 35 3A1 GND 15 34 GND 3B2 16 33 3A2 3B3 17 32 3A3 VCC 18 31 VCC 4B0 19 30 4A0 4B1 20 29 4A1 GND 21 28 GND 4B2 22 27 4A2 4B3 23 26 4A3 4OE 24 25 3OE TOP VIEW FUNCTION TABLE (Each 4-bit section) INPUTS OUTPUTS 1OE, 4OE 1Ai, 4Ai 1Bi, 4Bi L L H H L X H L Z INPUTS OUTPUTS 2OE, 3OE 2Ai, 3Ai 2Bi, 3Bi H H L H L X H L Z L = Logic Low, H = Logic High, X = Don't Care, Z = High Impedance i = 0 to 3 2 ML65F16241 PIN DESCRIPTION PIN NAME FUNCTION 1 1OE Output Enable Active Low 2 1B0 Data Output 3 1B1 Data Output 4 GND Signal Ground 5 1B2 Data Output 6 1B3 Data Output 7 VCC 2.7V to 3.6V Supply 8 2B0 Data Output 9 2B1 Data Output 10 GND Signal Ground 11 2B2 Data Output 12 2B3 Data Output 13 3B0 Data Output 14 3B1 Data Output 15 GND Signal Ground 16 3B2 Data Output 17 3B3 Data Output 18 VCC 2.7V to 3.6V Supply 19 4B0 Data Output 20 4B1 Data Output 21 GND Signal Ground 22 4B2 Data Output 23 4B3 Data Output 24 4OE Output Enable Active Low PIN NAME FUNCTION 25 3OE Output Enable Active High 26 4A3 Data Input 27 4A2 Data Input 28 GND Signal Ground 29 4A1 Data Input 30 4A0 Data Input 31 VCC 2.7V to 3.6V Supply 32 3A3 Data Input 33 3A2 Data Input 34 GND Signal Ground 35 3A1 Data Input 36 3A0 Data Input 37 2A3 Data Input 38 2A2 Data Input 39 GND Signal Ground 40 2A1 Data Input 41 2A0 Data Input 42 VCC 2.7V to 3.6V Supply 43 1A3 Data Input 44 1A2 Data Input 45 GND Signal Ground 46 1A1 Data Input 47 1A0 Data Input 48 2OE Output Enable Active High 3 ML65F16241 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Storage Temperature Range ..................... -65C to 150C Junction Temperature .............................................. 150C Lead Temperature (Soldering, 10sec) ...................... 150C Thermal Impedance (JA) ..................................... 76C/W VCC .................................................................................................. 7V DC Input Voltage ............................. -0.3V to VCC + 0.3V AC Input Voltage (PW < 20ns) ................................ -3.0V DC Output Voltage ...................................-0.3V to 7VDC Output Current, Source or Sink (AC) ..................... 180mA OPERATING CONDITIONS Temperature Range ....................................... 0C to 70C VIN Operating Range ...................................2.7V to 3.6V ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = 3.3V, TA = Operating Temperature Range (Note 1). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 3.3V 1.35 1.7 2 ns 2.7V 1.25 1.9 2.5 ns 3.3V 5 ns 2.7V 6 ns 3.3V 5 ns 2.7V 6 ns 3.3V 5 ns 2.7V 6 ns 3.3V 5 ns 2.7V 6 ns 300 ps 5 pF AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF) tPHL, tPLH tOE Propagation Delay Output Enable Time Ai to Bi OE to Ai/Bi DIR to Ai/Bi tOD Output Disable Time OE to Ai/Bi DIR to Ai/Bi TOS Output-to-Output Skew CIN Input Capacitance DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = Open) VIH Input High Voltage Logic high VIL Input Low Voltage Logic low 0.8 V IIH Input High Current Per pin, VIN = 3V 300 mA IIL Input Low Current Per pin, VIN = 0V 300 mA IHI-Z Three-State Output Current VCC = 3.6V, 0 < VIN < VCC 5 mA V IC Input Clamp Voltage VCC = 3.6V, IIN = 18mA -0.2 V I DYNAMIC Dynamic Transition Current (FastBus Charge) VOH 2.0 -0.7 Low to high transitions 80 mA High to low transitions 80 mA Output High Voltage VCC = 3.6V 2.4 3.4 V VCC = 2.7V 2.25 2.35 V VOL Output LowVoltage VCC = 2.7V and 3.6V 0.6 V I CC Quiescent Power Supply Current VCC = 3.6V, f = 0Hz, Inputs = VCC or 0V 3 A Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 4 V ML65F16241 0 100 -20 -40 80 60 IOH (mA) IOL (mA) -60 40 -80 -100 -120 -140 -160 20 -180 0 0 0.4 0.8 1.2 1.6 2 -200 1.8 2.0 2.2 2.4 Figure 1a. Typical VOL vs. IOL for 3.3V VCC. One Buffer Output 3.0 3.0 2.5 2.5 3.2 3.4 3.6 VCC = 2.7V VCC = 2.7V 2.0 tPLH (ns) tPHL (ns) 3.0 Figure 1b. Typical VOH vs. IOH for 3.3V VCC. One Buffer Output 2.0 VCC = 3.3V 1.5 1.0 1.0 0.5 0.5 25 0 0 75 50 VCC = 3.3V 1.5 25 0 LOAD CAPACITANCE (pF) 75 50 LOAD CAPACITANCE (pF) Figure 2a. Propagation Delay vs. Load Capacitance: 3.3V, 50MHZ Figure 2b. Propagation Delay vs. Load Capacitance: 2.7V, 50MHZ 60 60 50 50 75pF 30 50pF 20 75pF 40 ICC (mA) 40 ICC (mA) 2.8 VOH (V) VOL (V) 0 2.6 30 50pF 20 30pF 30pF 10 0 10 0 20 40 60 80 100 FREQUENCY (MHz) Figure 3a. ICC vs. Frequency: VCC = VIN = 3.3V. One Buffer Output 0 0 20 40 60 80 100 FREQUENCY (MHz) Figure 3b. ICC vs. Frequency: VCC = VIN = 2.7V. One Buffer Output 5 ML65F16241 FUNCTIONAL DESCRIPTION 1OE 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 2OE 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 3OE 3A0 3B0 3A1 3B1 3A2 3B2 3A3 3B3 4OE 4A0 4B0 4A1 4B1 4A2 4B2 4A3 4B3 Figure 4. Logic Diagram 1A0 1A1 1A2 1A3 2A0 2A1 2A2 2A3 3A0 3A1 3A2 4A0 4A1 4A2 4A3 2OE 3OE 1OE 4OE 1B0 1B1 1B2 1B3 2B0 2B1 2B2 2B3 3B0 3B1 3B2 Figure 5. Logic Symbol 6 3A3 3B3 4B0 4B1 4B2 4B3 ML65F16241 ARCHITECTURAL DESCRIPTION The basic architecture of the ML65F16241 is shown in Figure 6. In this circuit, there are two paths to the output. One path sources current to the load capacitance where the signal is asserted, and the other path sinks current from the output when the signal is negated. The ML65F16241 is a 16-bit buffer/line driver with 3-state outputs designed for 2.7V to 3.6V VCC operation. This device is designed for Quad-Nibble, Dual-Byte memory interleaving operations. Each bank has an independently controlled 3-state output enable pin with output enable/ disable access times of less than 7ns. Each bank is configured to have four independent buffer/line drivers. Two banks are active high enabled and the other two banks are active low enabled. Thus making this device ideal for nibble or byte swapping operations in cache or main memory designs by toggling between the active low and active high output enable pins. The assertion path is the Darlington pair consisting of transistors Q1 and Q2. The effect of transistor Q1 is to increase the current gain through the stage from input to output, to increase the input resistance and to reduce input capacitance. During an input low-to-high transition, the output transistor Q2 sources large amount of current to quickly charge up a highly capacitive load which in effect reduces the bus settling time. This current is specified as IDYNAMIC. Until now, these transceivers were typically implemented in CMOS logic and made to be TTL compatible by sizing the input devices appropriately. In order to buffer large capacitances with CMOS logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. Each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. The best of these 16-bit CMOS buffers has managed to drive 50pF load capacitance with a delay of 3ns. The negation path is also the Darlington pair consisting of transistor Q3 and transistor Q4. With M1 connecting to the input of the Darlington pair, Transistor Q4 then sinks a large amount of current during the input transition from high-to-low. Inverter X2 is a helpful buffer that not only drives the output toward the upper rail but also pulls the output to the lower rail. Micro Linear has produced a 16-bit buffer/line driver with a delay less than 2ns (3.3V) by using a unique circuit architecture that does not require cascade logic gates. VCC OE Q1 Q2 X1 X2 OUT IN M1 Q3 Q4 Figure 6. One Buffer Cell of the ML65F16241 7 ML65F16241 CIRCUITS AND WAVE FORMS VCC = 3V 1.5V ML65F16241 DUT INPUT 0V 3V tPLH VIN VOUT 50pF IOUT 1.5V OUTPUT 0V tRISE AND tFALL INPUT = 2ns Figure 7. Test Circuits for All Outputs ENABLE Figure 8. Propagation Delay DISABLE VCC = 3V CONTROL INPUT tPHL INPUT 1.5V 1.5V tOE tOD 3V OUTPUT1 OUTPUT LOW 1.5V VOL + 0.3V VOL tOE VOH VOH - 0.3V OUTPUT HIGH OUTPUTi i = 1 to 16 1.5V 0V tOD Figure 9. Enable and Disable Times 8 tOS Figure 10. Output Skew ML65F16241 9 ML65F16241 10 ML65F16241 PHYSICAL DIMENSIONS inches (millimeters) Package: R48 48-Pin SSOP 0.620 - 0.630 (15.75 - 16.00) 48 0.291 - 0.301 0.402 - 0.410 (7.39 - 7.65) (10.21 - 10.41) PIN 1 ID 1 0.015 - 0.025 (0.38 - 0.64) (4 PLACES) 0.025 BSC (0.63 BSC) 0.094 - 0.110 (2.39 - 2.79) 0 - 8 0.088 - 0.092 (2.24 - 2.34) 0.006 - 0.014 (0.15 - 0.36) SEATING PLANE 0.024 - 0.040 (0.61 - 1.02) 0.008 - 0.016 (0.20 - 0.41) 0.005 - 0.010 (0.13 - 0.26) Package: T48 48-Pin TSSOP 0.487 - 0.497 (12.37 - 12.63) 0.236 - 0.244 (6.00 - 6.20) 0.319 BSC (8.1 BSC) PIN 1 ID 0.020 BSC (0.50 BSC) 0.047 MAX (1.20 MAX) 0 - 8 0.031 - 0.039 (0.80 - 1.00) 0.007 - 0.011 (0.17 - 0.27) SEATING PLANE 0.002 - 0.006 (0.05 - 0.15) 0.020 - 0.028 (0.50 - 0.70) 0.004 - 0.008 (0.10 - 0.20) 11 ML65F16241 ORDERING INFORMATION (c) Micro Linear 1998. PART NUMBER TEMPERATURE RANGE PACKAGE ML65F16241CR 0C to 70C 48-Pin SSOP (R48) ML65F16241CT 0C to 70C 48-Pin TSSOP (T48) is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653;. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com 6/23/98 Printed in U.S.A. To receive a price quote or to request a product sample, call or send e-mail to your local representative. When sending e-mail, be sure to include the Micro Linear part number and whether you want a price quote or a sample in the subject line. (i.e. subject: Sample request - ML part#xxxx) Click here to find your local representative