CD74HC14M96G4 - Texas Instruments

Data sheet acquired from Harris Semiconductor

SCHS129F

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Description

The ’HC14 and ’HCT14 each contain six inverting Schmitt

triggers in one package.

Pinout

CD54HC14, CD54HCT14

(CERDIP)

CD74HC14, CD74HCT14

(PDIP, SOIC, TSSOP)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC14F3A -55 to 125 14 Ld CERDIP

CD54HCT14F3A -55 to 125 14 Ld CERDIP

CD74HC14E -55 to 125 14 Ld PDIP

CD74HC14M -55 to 125 14 Ld SOIC

CD74HC14MT -55 to 125 14 Ld SOIC

CD74HC14M96 -55 to 125 14 Ld SOIC

CD74HC14PW -55 to 125 14 Ld TSSOP

CD74HC14PWR -55 to 125 14 Ld TSSOP

CD74HCT14E -55 to 125 14 Ld PDIP

CD74HCT14M -55 to 125 14 Ld SOIC

CD74HCT14MT -55 to 125 14 Ld SOIC

CD74HCT14M96 -55 to 125 14 Ld SOIC

CD74HCT14PW -55 to 125 14 Ld TSSOP

CD74HCT14PWR -55 to 125 14 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

GND

VCC

January 1998 - Revised May 2005

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC14, CD74HC14,

CD54HCT14, CD74HCT14

High-Speed CMOS Logic

Hex Inverting Schmitt Trigger

[

/Title

(

CD74H

14,

D74H

T14)

Subject

(

High

peed

MOS

ogic

nvert-

Functional Diagram

Logic Diagram

TRUTH TABLE

INPUT (A) OUTPUT (Y)

H= High Level

L= Low Level

12 6Y

GND = 7

VCC = 14

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

nA nY

VOVH

VT-V

T+

VH = VT+ - VT-

VCC

GND

VCC

GND

VT+V

T-

CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

113

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

HC TYPES

Input Switch Points VT+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V

4.5 1.7 3.15 1.7 3.15 1.7 3.15 V

6 2.1 4.2 2.1 4.2 2.1 4.2 V

VT- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V

4.5 0.9 2.2 0.9 2.2 0.9 2.2 V

6 1.2 3.0 1.2 3.0 1.2 3.0 V

VH- - 2 0.2 1.0 0.2 1.0 0.2 1.0 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

6 0.6 1.6 0.6 1.6 0.6 1.6 V

High Level Output

Voltage CMOS Loads VOH VT- -0.02 2 1.9 - 1.9 - 1.9 - V

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-0.02 6 5.9 - 5.9 - 5.9 - V

High Level Output

Voltage TTL Loads --------V

-4 4.5 3.98 - 3.84 - 3.7 - V

-5.2 6 5.48 - 5.34 - 5.2 - V

LowLevelOutputVoltage

CMOS Loads VOL VT+ 0.02 2 - 0.1 - 0.1 - 0.1 V

0.02 4.5 - 0.1 - 0.1 - 0.1 V

0.02 6 - 0.1 - 0.1 - 0.1 V

LowLevel Output Voltage

TTL Loads --------V

4 4.5 - 0.26 - 0.33 - 0.4 V

5.2 6 - 0.26 - 0.33 - 0.4 V

CD54HC14, CD74HC14, CD54HCT, CD74HCT14

Input Leakage Current IIVCC or

GND -6-±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 06-2-20-40µA

HCT TYPES

Input Switch Points VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V

5.5 1.4 2.1 1.4 2.1 1.4 2.1 V

VT- 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V

5.5 0.6 1.4 0.6 1.4 0.6 1.4 V

VH4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 1.5 0.4 1.5 0.4 1.5 V

High Level Output

Voltage CMOS Loads VOH VT- -0.02 4.5 4.4 - 4.4 - 4.4 - V

High Level Output

Voltage TTL Loads -4 4.5 3.98 - 3.84 - 3.7 - V

LowLevelOutputVoltage

CMOS Loads VOL VT+ 0.02 4.5 - 0.1 - 0.1 - 0.1 V

LowLevel Output Voltage

TTL Loads 4 4.5 - 0.26 - 0.33 - 0.4 V

Input Leakage Current IIVCC

and

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - 2 - 20 - 40 µA

Additional Quiescent

Device Current Per Input

Pin: 1 Unit Load

∆ICC

(Note 2) VCC

- 2.1 - 4.5 to

5.5 - 360 - 450 - 490 µA

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nA 0.6

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical Speciﬁca-

tions table, e.g., 360µA max at 25oC.

CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay,

A to Y tPLH, tPHL CL= 50pF 2 - - 135 - 170 - 205 ns

CL= 50pF 4.5 - - 27 - 34 - 41 ns

CL= 15pF 5 - 11 - ----ns

CL= 50pF 6 - - 23 - 29 - 35 ns

Output Transition Times tTLH, tTHL CL= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 3, 4) CPD - 5-20-----pF

HCT TYPES

Propagation Delay,

A to Y tPLH, tPHL CL= 50pF 4.5 - - 38 - 48 - 57 ns

CL= 15pF 5 - 16 - ----ns

Output Transition Times tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 3, 4) CPD - 5-20-----pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per inverter.

4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Test Circuits and Waveforms

FIGURE 4. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD54HC14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type

CD54HC14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type

CD54HCT14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type

CD54HCT14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type

CD74HC14E ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC14EE4 ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HC14M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14MT ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PW ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HC14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14E ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT14EE4 ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type

CD74HCT14M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

no Sb/Br)

CD74HCT14ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14MT ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PW ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

CD74HCT14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com 15-Oct-2009

Addendum-Page 3

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC14MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HCT14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HCT14MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HCT14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC14M96 SOIC D 14 2500 367.0 367.0 38.0

CD74HC14M96 SOIC D 14 2500 333.2 345.9 28.6

CD74HC14MT SOIC D 14 250 367.0 367.0 38.0

CD74HC14PWR TSSOP PW 14 2000 367.0 367.0 35.0

CD74HCT14M96 SOIC D 14 2500 367.0 367.0 38.0

CD74HCT14MT SOIC D 14 250 367.0 367.0 38.0

CD74HCT14PWR TSSOP PW 14 2000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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