COP8CDR9HVA8/NOPB - NATIONAL SEMICONDUCTOR

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

COP8CBR9/COP8CCR9/COP8CDR9 8-Bit CMOS Flash Microcontroller with 32k Memory,

Virtual EEPROM, 10-Bit A/D and Brownout

Check for Samples: COP8CBR9,COP8CCR9,COP8CDR9

1 Introduction

1.1 FEATURES

123 • 6.67 MHz Operation from 3.33 MHz

• 32 kbytes Flash Program Memory with Security Oscillator, with 1.5 μs Instruction Cycle

Feature (COP8CBR9)

• Virtual EEPROM using Flash Program Memory – Thirteen Multi-Source Vectored Interrupts

• 1 kbyte Volatile RAM Servicing:

• 10-bit Successive Approximation Analog to • External Interrupt

Digital Converter (up to 16 Channels) • USART (2)

• 100% Precise Analog Emulation • Idle Timer T0

• USART with Onchip Baud Generator • Three Timers (Each with 2 Interrupts)

• 2.7V – 5.5V In-System Programmability of Flash • MICROWIRE/PLUS Serial Peripheral

• High Endurance -100k Read/Write Cycles Interface

• Superior Data Retention - 100 years • Multi-Input Wake-up

• Dual Clock Operation with HALT/IDLE Power • Software Trap

Save Modes – Idle Timer with Programmable Interrupt

• Three 16-bit Timers: Interval

– Timers T2 and T3 can Operate at High Speed – 8-bit Stack Pointer SP (Stack in RAM)

(50 ns Resolution) – Two 8-bit Register Indirect Data Memory

– Processor Independent PWM Mode Pointers

– External Event Counter Mode – True Bit Manipulation

– Input Capture Mode – WATCHDOG and Clock Monitor Logic

• Brown-Out Reset (COP8CBR9/CCR9) – Software Selectable I/O Options

• OTHER FEATURES • TRI-STATE Output/High Impedance Input

– Single Supply Operation: • Push-Pull Output

• 2.7V–5.5V (−40°C to +85°C) • Weak Pull Up Input

• 4.5V–5.5V (−40°C to +125°C) – Schmitt Trigger Inputs on I/O ports

– Quiet Design (Low Radiated Emissions) – High Current I/Os

– Multi-Input Wake-Up with Optional Interrupts – Temperature Range: –40°C to +85°C and

– MICROWIRE/PLUS (Serial Peripheral –40°C to +125°C (COP8CCR9/CDR9)

Interface Compatible) – Packaging: 44 and 68 PLCC, 44 WQFN, 48

– Clock Doubler for and 56 TSSOP

• 20 MHz Operation from 10 MHz Oscillator – True In-System, Real Time Emulation and

(COP8CCR9/CDR9) with 0.5 µs Instruction Debug Tools Available

Cycle

1.2 DESCRIPTION

The COP8CBR/CCR/CDR9 Flash microcontrollers are highly integrated COP8™ Feature core devices,

with 32k Flash memory and advanced features including Virtual EEPROM, A/D, High Speed Timers,

USART, and Brownout Reset. This single-chip CMOS device is suited for applica tions requiring a full

featured, in-system reprogrammable controller with large memory and low EMI. The same device is used

for development, pre-production and volume production with a range of COP8 software and hardware

development tools.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2COP8 is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Table 1-1. Device included in this datasheet:

Flash Program RAM Brownout I/O

Device Memory Packages Temperature

(bytes) Voltage Pins

(bytes)

44 WQFN,

COP8CBR9 32k 1k 2.7V to 2.9V 37,39,49, 59 44/68 PLCC, −40°C to +85°C

48/56 TSSOP

44 WQFN, −40°C to +85°C

COP8CCR9 32k 1k 4.17V to 4.5V 37,39,49, 59 44/68 PLCC, −40°C to +125°C

48/56 TSSOP

44 WQFN, −40°C to +85°C

COP8CDR9 32k 1k No Brownout 37,39,49, 59 44/68 PLCC, −40°C to +125°C

48/56 TSSOP

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

1 Introduction .............................................. 15 Functional Description ............................... 22

1.1 FEATURES .......................................... 15.1 CPU REGISTERS .................................. 22

1.2 DESCRIPTION ...................................... 15.2 PROGRAM MEMORY .............................. 22

2 Device Information ...................................... 45.3 DATA MEMORY .................................... 22

2.1 Block Diagram ....................................... 45.4 DATA MEMORY SEGMENT RAM EXTENSION ... 23

2.2 Connection Diagram ................................. 45.5 OPTION REGISTER ............................... 24

2.3 Architectural Overview ............................... 75.6 SECURITY ......................................... 25

3 Electrical Specifications ............................. 11 5.7 RESET .............................................. 26

3.1 Absolute Maximum Ratings ........................ 11 5.8 OSCILLATOR CIRCUITS .......................... 29

3.2 Electrical Characteristics DC Electrical 5.9 CONTROL REGISTERS ........................... 31

Characteristics (−40°C ≤TA≤+85°C) .............. 11 5.10 In-System Programming ............................ 34

3.3 Electrical Characteristics AC Electrical 5.11 Timers .............................................. 42

Characteristics (−40°C ≤TA≤+85°C) .............. 13 5.12 Power Saving Features ............................. 48

3.4 A/D Converter Electrical Characteristics (−40°C ≤5.13 USART .............................................. 58

TA≤+85°C unless otherwise noted) (Single-ended

mode only) .......................................... 13 5.14 A/D Converter ...................................... 68

3.5 DC Electrical Characteristics (−40°C ≤TA≤5.15 Interrupts ............................................ 73

+125°C) ............................................. 14 5.16 WATCHDOG/Clock Monitor ........................ 81

3.6 AC Electrical Characteristics (−40°C ≤TA≤+125°C) 5.17 MICROWIRE/PLUS ................................ 84

...................................................... 15 5.18 Memory Map ....................................... 88

3.7 A/D Converter Electrical Characteristics (−40°C ≤5.19 Instruction Set ...................................... 90

TA≤+125°C) (Single-ended mode only) ........... 16 5.20 Development Support ............................. 100

4 Pin Descriptions ....................................... 17 Revision History ........................................... 104

4.1 EMULATION CONNECTION ....................... 21

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

2 Device Information

2.1 Block Diagram

2.2 Connection Diagram

Figure 2-1. Plastic Chip Package (Top View) Figure 2-2. Plastic Chip Package (Top View)

See Package Number FN0068A See Package Number FN0044A

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Figure 2-3. WQFN Package (Top View) Figure 2-4. TSSOP Package (Top View)

See Package Number NJN0044A See Package Number DGG0048A

Figure 2-5. TSSOP Package (Top View)

See Package Number DGG0056A

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Table 2-1. Pinouts for All Packages

In System 44-Pin 48-Pin 56-Pin 68-Pin

Port Type Alt. Fun Emulation 44-Pin WQFN PLCC TSSOP TSSOP PLCC

Mode

L0 I/O MIWU or Low Speed OSC In 16 11 11 15 22

L1 I/O MIWU or CKX or Low Speed 17 12 12 16 23

OSC Out

L2 I/O MIWU or TDX 18 13 13 17 24

L3 I/O MIWU or RDX 19 14 14 18 25

L4 I/O MIWU or T2A 20 15 15 19 26

L5 I/O MIWU or T2B 21 16 16 20 27

L6 I/O MIWU or T3A 22 17 17 21 28

L7 I/O MIWU or T3B 23 18 18 22 29

G0 I/O INT Input 7 2 2 2 3

G1 I/O WDOUT(1) POUT 8 3 3 3 4

G2 I/O T1B Output 9 4 4 4 5

G3 I/O T1A Clock 10 5 5 5 6

G4 I/O SO 11 6 6 6 11

G5 I/O SK 12 7 7 7 12

G6 I SI 13 8 8 8 13

G7 I CKO 14 9 9 9 14

D0 O 42 37 41 49 58

D1 O 43 38 42 50 59

D2 O 44 39 43 51 60

D3 O 1 40 44 52 61

D4 O 2 41 45 53 62

D5 O 3 42 46 54 63

D6 O 4 43 47 55 64

D7 O 5 44 48 56 65

E0 I/O 47 54

E1 I/O 48 55

E2 I/O 56

E3 I/O 57

E4 I/O 67

E5 I/O 68

E6 I/O 1

E7 I/O 2

C0 I/O 11 18

C1 I/O 12 19

C2 I/O 13 20

C3 I/O 14 21

C4 I/O 23 30

C5 I/O 24 31

C6 I/O 25 32

C7 I/O 26 33

(1) G1 operation as WDOUT is controlled by Option Register bit 2.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Table 2-1. Pinouts for All Packages (continued)

In System 44-Pin 48-Pin 56-Pin 68-Pin

Port Type Alt. Fun Emulation 44-Pin WQFN PLCC TSSOP TSSOP PLCC

Mode

A0 I/O ADCH0 33 39 46

A1 I/O ADCH1 34 40 47

A2 I/O ADCH2 36 31 35 41 48

A3 I/O ADCH3 37 32 36 42 49

A4 I/O ADCH4 38 33 37 43 50

A5 I/O ADCH5 39 34 38 44 51

A6 I/O ADCH6 40 35 39 45 52

A7 I/O ADCH7 41 36 40 46 53

B0 I/O ADCH8 24 19 19 27 34

B1 I/O ADCH9 25 20 20 28 35

B2 I/O ADCH10 26 21 21 29 36

B3 I/O ADCH11 27 22 22 30 37

B4 I/O ADCH12 28 23 23 31 38

B5 I/O ADCH13 or A/D MUX OUT 29 24 24 32 39

B6 I/O ADCH14 or A/D MUX OUT 30 25 25 33 40

B7 I/O ADCH15 or A/DIN 31 26 26 34 41

F0 I/O 7

F1 I/O 8

F2 I/O 9

F3 I/O 10

DVCC VCC 35 30 32 38 17, 45

DGND GND 32 27 27 35 16, 42

AVCC 34 29 31 37 44

AGND 33 28 28 36 43

CKI I 15 10 10 10 15

RESET I RESET 6 1 1 1 66

2.3 Architectural Overview

This table assumes that the control flag MSEL is set.

2.3.1 EMI REDUCTION

This table assumes that the control flag MSEL is set.

The COP8CBR/CCR/CDR devices incorporate circuitry that guards against electromagnetic interference -

an increasing problem in today's microcontroller board designs. TI's patented EMI reduction technology

offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) and internal Icc smoothing filters, to

help circumvent many of the EMI issues influencing embedded control designs. TI has achieved 15 dB–20

dB reduction in EMI transmissions when designs have incorporated its patented EMI reducing circuitry.

2.3.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM

The device includes a program in a boot ROM that provides the capability, through the

MICROWIRE/PLUS serial interface, to erase, program and read the contents of the Flash memory.

Additional routines are included in the boot ROM, which can be called by the user program, to enable the

user to customize in system software update capability if MICROWIRE/PLUS is not desired.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Additional functions will copy blocks of data between the RAM and the Flash Memory. These functions

provide a virtual EEPROM capability by allowing the user to emulate a variable amount of EEPROM by

initializing nonvolatile variables from the Flash Memory and occasionally restoring these variables to the

Flash Memory.

The contents of the boot ROM have been defined by TI. Execution of code from the boot ROM is

dependent on the state of the FLEX bit in the Option Register on exit from RESET. If the FLEX bit is a

zero, the Flash Memory is assumed to be empty and execution from the boot ROM begins. For further

information on the FLEX bit, refer to Section Option Register.

2.3.3 DUAL CLOCK AND CLOCK DOUBLER

The device includes a versatile clocking system and two oscillator circuits designed to drive a crystal or

ceramic resonator. The primary oscillator operates at high speed up to 10 MHz. The secondary oscillator

is optimized for operation at 32.768 kHz.

The user can, through specified transition sequences (please refer to Power Saving Features), switch

execution between the high speed and low speed oscillators. The unused oscillator can then be turned off

to minimize power dissipation. If the low speed oscillator is not used, the pins are available as general

purpose bidirectional ports.

The operation of the CPU will use a clock at twice the frequency of the selected oscillator (up to 20 MHz

for high speed operation and 65.536 kHz for low speed operation). This doubled clock will be referred to in

this document as ‘MCLK'. The frequency of the selected oscillator will be referred to as CKI. Instruction

execution occurs at one tenth the selected MCLK rate.

2.3.4 TRUE IN-SYSTEM EMULATION

On-chip emulation capability has been added which allows the user to perform true in-system emulation

using final production boards and devices. This simplifies testing and evaluation of software in real

environmental conditions. The user, merely by providing for a standard connector which can be bypassed

by jumpers on the final application board, can provide for software and hardware debugging using actual

production units.

2.3.5 ARCHITECTURE

The COP8 family is based on a modified Harvard architecture, which allows data tables to be accessed

directly from program memory. This is very important with modern microcontroller-based applications,

since program memory is usually ROM or EPROM, while data memory is usually RAM. Consequently

constant data tables need to be contained in non-volatile memory, so they are not lost when the

microcontroller is powered down. In a modified Harvard architecture, instruction fetch and memory data

transfers can be overlapped with a two stage pipeline, which allows the next instruction to be fetched from

program memory while the current instruction is being executed using data memory. This is not possible

with a Von Neumann single-address bus architecture.

The COP8 family supports a software stack scheme that allows the user to incorporate many subroutine

calls. This capability is important when using High Level Languages. With a hardware stack, the user is

limited to a small fixed number of stack levels.

2.3.6 INSTRUCTION SET

In today's 8-bit microcontroller application arena cost/performance, flexibility and time to market are

several of the key issues that system designers face in attempting to build well-engineered products that

compete in the marketplace. Many of these issues can be addressed through the manner in which a

microcontroller's instruction set handles processing tasks. And that's why the COP8 family offers a unique

and code-efficient instruction set - one that provides the flexibility, functionality, reduced costs and faster

time to market that today's microcontroller based products require.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Code efficiency is important because it enables designers to pack more on-chip functionality into less

program memory space (ROM, OTP or Flash). Selecting a microcontroller with less program memory size

translates into lower system costs, and the added security of knowing that more code can be packed into

the available program memory space.

2.3.6.1 Key Instruction Set Features

The COP8 family incorporates a unique combination of instruction set features, which provide designers

with optimum code efficiency and program memory utilization.

2.3.6.2 Single Byte/Single Cycle Code Execution

The efficiency is due to the fact that the majority of instructions are of the single byte variety, resulting in

minimum program space. Because compact code does not occupy a substantial amount of program

memory space, designers can integrate additional features and functionality into the microcontroller

program memory space. Also, the majority instructions executed by the device are single cycle, resulting

in minimum program execution time. In fact, 77% of the instructions are single byte single cycle, providing

greater code and I/O efficiency, and faster code execution.

2.3.6.3 Many Single-Byte, Multi-Function Instructions

The COP8 instruction set utilizes many single-byte, multifunction instructions. This enables a single

instruction to accomplish multiple functions, such as DRSZ, DCOR, JID, LD (Load) and X (Exchange)

instructions with post-incrementing and post-decrementing, to name just a few examples. In many cases,

the instruction set can simultaneously execute as many as three functions with the same single-byte

instruction.

JID: (Jump Indirect); Single byte instruction decodes external events and jumps to corresponding service

routines (analogous to “DO CASE” statements in higher level languages).

LAID: (Load Accumulator-Indirect); Single byte look up table instruction provides efficient data path from

the program memory to the CPU. This instruction can be used for table lookup and to read the entire

program memory for checksum calculations.

RETSK: (Return Skip); Single byte instruction allows return from subroutine and skips next instruction.

Decision to branch can be made in the subroutine itself, saving code.

AUTOINC/DEC: (Auto-Increment/Auto-Decrement); These instructions use the two memory pointers B

and X to efficiently process a block of data (simplifying “FOR NEXT” or other loop structures in higher

level languages).

2.3.6.4 Bit-Level Control

Bit-level control over many of the microcontroller's I/O ports provides a flexible means to ease layout

concerns and save board space. All members of the COP8 family provide the ability to set, reset and test

any individual bit in the data memory address space, including memory-mapped I/O ports and associated

registers.

2.3.6.5 Register Set

Three memory-mapped pointers handle register indirect addressing and software stack pointer functions.

The memory data pointers allow the option of post-incrementing or post- decrementing with the data

movement instructions (LOAD/EXCHANGE). And 15 memory-mapped registers allow designers to

optimize the precise implementation of certain specific instructions.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

2.3.7 PACKAGING/PIN EFFICIENCY

Real estate and board configuration considerations demand maximum space and pin efficiency,

particularly given today's high integration and small product form factors. Microcontroller users try to avoid

using large packages to get the I/O needed. Large packages take valuable board space and increase

device cost, two trade-offs that microcontroller designs can ill afford.

The COP8 family offers a wide range of packages and does not waste pins.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

3 Electrical Specifications

3.1 Absolute Maximum Ratings(1)(2)

Supply Voltage (VCC) 7V

Voltage at Any Pin −0.3V to VCC +0.3V

Total Current into VCC Pin (Source) 200 mA

Total Current out of GND Pin (Sink) 200 mA

Storage Temperature Range −65°C to +140°C

ESD Protection Level 2 kV (Human Body Model)

(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not

ensured when operating the device at absolute maximum ratings.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.

3.2 Electrical Characteristics DC Electrical Characteristics (−40°C ≤TA≤+85°C)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Operating Voltage 2.7 5.5 V

Power Supply Rise Time 10 50 x 106ns

Power Supply Ripple(1) Peak-to-Peak 0.1 VCC V

Supply Current(2)

High Speed Mode

CKI = 10 MHz VCC = 5.5V, tC= 0.5 μs 13.2 mA

CKI = 3.33 MHz VCC = 4.5V, tC= 1.5 μs 6 mA

Dual Clock Mode

CKI = 10 MHz, Low Speed OSC = 32 kHz VCC = 5.5V, tC= 0.5 μs 13.2 mA

CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC= 1.5 μs 6 mA

Low Speed Mode

Low Speed OSC = 32 kHz VCC = 5.5V 60 103 μA

HALT Current with BOR Disabled(3)

High Speed Mode VCC = 5.5V, CKI = 0 MHz <2 10 μA

Dual Clock Mode VCC = 5.5V, CKI = 0 MHz, Low <5 17 μA

Speed OSC = 32 kHz

Low Speed Mode VCC = 5.5V, CKI = 0 MHz, Low <5 17 μA

Speed OSC = 32 kHz

Idle Current(2)

High Speed Mode

CKI = 10 MHz VCC = 5.5V, tC= 0.5 μs 2.5 mA

CKI = 3.33 MHz VCC = 4.5V, tC= 1.5 μs 1.2 mA

Dual Clock Mode

CKI = 10 MHz, Low Speed OSC = 32 kHz VCC = 5.5V, tC= 0.5 μs 2.5 mA

CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC= 1.5 μs 1.2 mA

Low Speed Mode

Low Speed OSC = 32 kHz VCC = 5.5V 15 30 μA

(1) Maximum rate of voltage change must be < 0.5 V/ms.

(2) Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180° out of phase with CKI, inputs

connected to VCC and outputs driven low but not connected to a load.

(3) The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with

L. A. B, C, E, F, G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a

load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7

of the G Port data register.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Electrical Characteristics DC Electrical Characteristics (−40°C ≤TA≤+85°C) (continued)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Supply Current for BOR Feature VCC = 5.5V 45 μA

4.28

High Brownout Trip Level (BOR Enabled) 4.17 4.5 V

Low Brownout Trip Level (BOR Enabled) 2.7 2.78 2.9 V

Input Levels (VIH, VIL)

Logic High 0.8 VCC V

Logic Low 0.16 VCC V

Internal Bias Resistor for the CKI 0.3 1.0 2.5 MΩ

Crystal/Resonator Oscillator

Hi-Z Input Leakage VCC = 5.5V −0.5 +0.5 μA

Input Pullup Current VCC = 5.5V, VIN = 0V −50 −210 μA

Port Input Hysteresis 0.25 VCC V

Output Current Levels

D Outputs

Source VCC = 4.5V, VOH = 3.8V −7 mA

VCC = 2.7V, VOH = 1.8V −4 mA

Sink(4) VCC = 4.5V, VOL = 1.0V 10 mA

VCC = 2.7V, VOL = 0.4V 3.5 mA

All Others

Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 3.8V −10 μA

VCC = 2.7V, VOH = 1.8V −5μA

Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −7 mA

VCC = 2.7V, VOH = 1.8V −4 mA

Sink (Push-Pull Mode)(4) VCC = 4.5V, VOL = 1.0V 10 mA

VCC = 2.7V, VOL = 0.4V 3.5 mA

TRI-STATE Leakage VCC = 5.5V −0.5 +0.5 μA

Allowable Sink Current per Pin 15 mA

Maximum Input Current without Latchup(5) ±200 mA

RAM Retention Voltage, VR(in HALT Mode) 2.0 V

Input Capacitance 7 pF

Load Capacitance on D2 1000 pF

Voltage on G6 to Force Execution from Boot ROM(6) G6 rise time must be slower than 2 x VCC VCC + 7 V

100 ns

G6 Rise Time to Force Execution from Boot ROM 100 nS

Input Current on G6 when Input > VCC VIN = 11V, VCC = 5.5V 500 μA

Flash Memory Data Retention 25°C 100 yrs

Flash Memory Number of Erase/Write Cycles SeeTable 5-12,Typical Flash 105cycles

Memory Endurance

(4) Absolute Maximum Ratings should not be exceeded.

(5) Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink

current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two

pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the

pins. This warning excludes ESD transients.

(6) Vcc must be valid and stable before G6 is raised to a high voltage.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

3.3 Electrical Characteristics AC Electrical Characteristics (−40°C ≤TA≤+85°C)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (tC)(1)

Crystal/Resonator 4.5V ≤VCC ≤5.5V 0.5 DC μs

2.7V ≤VCC < 4.5V 1.5 DC μs

Flash Memory Page Erase Time See Table 5-12,Typical Flash 1 ms

Memory Endurance

Flash Memory Mass Erase Time 8 ms

Frequency of MICROWIRE/PLUS in Slave Mode 2 MHz

MICROWIRE/PLUS Setup Time (tUWS) 20 ns

MICROWIRE/PLUS Hold Time (tUWH) 20 ns

MICROWIRE/PLUS Output Propagation Delay (tUPD) 150 ns

Input Pulse Width

Interrupt Input High Time 1 tC

Interrupt Input Low Time 1 tC

Timer 1 Input High Time 1 tC

Timer 1 Input Low Time 1 tC

Timer 2, 3 Input High Time(2) 1 MCLK or tC

Timer 2, 3 Input Low Time(2) 1 MCLK or tC

Output Pulse Width

Timer 2, 3 Output High Time 150 ns

Timer 2, 3 Output Low Time 150 ns

USART Bit Time when using External CKX 6 CKI

periods

USART CKX Frequency when being 2 MHz

Driven by Internal Baud Rate Generator

Reset Pulse Width 1 tC

(1) tC= instruction cycle time.

(2) If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

3.4 A/D Converter Electrical Characteristics (−40°C ≤TA≤+85°C unless otherwise noted)

(Single-ended mode only)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Resolution 10 Bits

DNL VCC = 5V ±1 LSB

DNL VCC = 3V,−20°C ≤TA≤±1 LSB

+85°C

INL VCC = 5V ±3 LSB

INL VCC = 3V,−20°C ≤TA≤±4 LSB

+85°C

Offset Error VCC = 5V +2.5, −1 LSB

Offset Error VCC = 3V,−20°C ≤TA≤±2.5 LSB

+85°C

Gain Error VCC = 5V +0.5, −2.5 LSB

Gain Error VCC = 3V,−20°C ≤TA≤±2.5 LSB

+85°C

Input Voltage Range 2.7V ≤VCC < 5.5V 0 VCC V

Analog Input Leakage Current 0.5 µA

Analog Input Resistance(1) 6k Ω

(1) Resistance between the device input and the internal sample and hold capacitance.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

A/D Converter Electrical Characteristics (−40°C ≤TA≤+85°C unless otherwise noted) (Single-ended mode

only) (continued)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Analog Input Capacitance 7 pF

Conversion Clock Period 4.5V ≤VCC < 5.5V 0.8 30 µs

2.7V ≤VCC < 4.5V 1.2 30 µs

Conversion Time (including S/H Time) 15 A/D

Conversion

Clock

Cycles

Operating Current on AVCC AVCC = 5.5V 0.2 0.6 mA

3.5 DC Electrical Characteristics (−40°C ≤TA≤+125°C)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Operating Voltage 4.5 5.5 V

Power Supply Rise Time 10 50 x 106ns

Power Supply Ripple(1) Peak-to-Peak 0.1 VCC V

Supply Current(2)

High Speed Mode

CKI = 10 MHz VCC = 5.5V, tC= 0.5 μs 14.5 mA

CKI = 3.33 MHz VCC = 4.5V, tC= 1.5 μs 7 mA

Dual Clock Mode 14.5

CKI = 10 MHz, Low Speed OSC = 32 kHz VCC = 5.5V, tC= 0.5 μs mA

CKI = 3.33 MHz, Low Speed OSC = 32 kHz VCC = 4.5V, tC= 1.5 μs 7 mA

Low Speed Mode 110

Low Speed OSC = 32 kHz VCC = 5.5V 65 μA

HALT Current with BOR Disabled(3)

High Speed Mode VCC = 5.5V, CKI = 0 MHz <4 40 μA

Dual Clock Mode VCC = 5.5V, CKI = 0 MHz, Low <9 50 μA

Speed OSC = 32 kHz

Low Speed Mode VCC = 5.5V, CKI = 0 MHz, Low <9 50 μA

Speed OSC = 32 kHz

Idle Current (2)

High Speed Mode

CKI = 10 MHz VCC = 5.5V, tC= 0.5 μs 2.7 mA

Dual Clock Mode

CKI = 10 MHz, Low Speed OSC = 32 kHz VCC = 5.5V, tC= 0.5 μs 2.7 mA

Low Speed Mode

Low Speed OSC = 32 kHz VCC = 5.5V 30 70 μA

Supply Current for BOR Feature VCC = 5.5V 45 μA

High Brownout Trip Level (BOR Enabled) 4.17 4.28 4.5 V

Input Levels (VIH, VIL)

Logic High 0.8 VCC V

Logic Low 0.16 VCC V

(1) Maximum rate of voltage change must be < 0.5 V/ms.

(2) Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180° out of phase with CKI, inputs

connected to VCC and outputs driven low but not connected to a load.

(3) The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with

L. A. B, C, E, F, G0, and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a

load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7

of the G Port data register.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

DC Electrical Characteristics (−40°C ≤TA≤+125°C) (continued)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Internal Bias Resistor for the CKI 0.3 1.0 2.5 MΩ

Crystal/Resonator Oscillator

Hi-Z Input Leakage VCC = 5.5V −3 +3 μA

Input Pullup Current VCC = 5.5V, VIN = 0V −40 −250 μA

Port Input Hysteresis 0.25 VCC V

Output Current Levels

D Outputs

Source VCC = 4.5V, VOH = 3.8V −6.3 mA

Sink(4) VCC = 4.5V, VOL = 1.0V 9 mA

All Others

Source (Weak Pull-Up Mode) VCC = 4.5V, VOH = 3.8V −9μA

Source (Push-Pull Mode) VCC = 4.5V, VOH = 3.8V −6.3 mA

Sink (Push-Pull Mode)(4) VCC = 4.5V, VOL = 1.0V 9 mA

TRI-STATE Leakage VCC = 5.5V −3 +3 μA

Allowable Sink Current per Pin 1 mA

Maximum Input Current without Latchup(5) ±200 mA

RAM Retention Voltage, VR(in HALT Mode) 2.0 V

Input Capacitance 7 pF

Load Capacitance on D2 1000 pF

Voltage on G6 to Force Execution from Boot ROM(6) G6 rise time must be slower than 2 x VCC VCC + 7 V

100 ns

G6 Rise Time to Force Execution from Boot ROM 100 nS

Input Current on G6 when Input > VCC VIN = 11V, VCC = 5.5V 500 μA

(4) Absolute Maximum Ratings should not be exceeded.

(5) Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink

current to VCC when biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two

pins will not latch up. The voltage at the pins must be limited to < (VCC + 7V. WARNING: Voltages in excess of 14V will cause

damage to the pins. This warning excludes ESD transients.

(6) Vcc must be valid and stable before G6 is raised to a high voltage.

3.6 AC Electrical Characteristics (−40°C ≤TA≤+125°C)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Instruction Cycle Time (tC)

Crystal/Resonator(1) 4.5V ≤VCC ≤5.5V 0.5 DC μs

Output Propagation Delay RL=2.2k, CL= 100 pF

Frequency of MICROWIRE/PLUS in Slave Mode 2 MHz

MICROWIRE/PLUS Setup Time (tUWS) 20 ns

MICROWIRE/PLUS Hold Time (tUWH) 20 ns

MICROWIRE/PLUS Output Propagation Delay (tUPD) 150 ns

Input Pulse Width

Interrupt Input High Time 1 tC

Interrupt Input Low Time 1 tC

Timer 1 Input High Time 1 tC

Timer 1 Input Low Time 1 tC

Timer 2, 3 Input High Time(2) 1 MCLK or tC

Timer 2, 3 Input Low Time(2) 1 MCLK or tC

(1) tC= instruction cycle time.

(2) If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

AC Electrical Characteristics (−40°C ≤TA≤+125°C) (continued)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Output Pulse Width

Timer 2, 3 Output High Time 150 ns

Timer 2, 3 Output Low Time 150 ns

USART Bit Time when using External CKX 6 CKI

periods

USART CKX Frequency when being Driven by Internal

Baud Rate Generator 2 MHz

Reset Pulse Width 0.5 tC

3.7 A/D Converter Electrical Characteristics (−40°C ≤TA≤+125°C) (Single-ended mode

only)

Datasheet min/max specification limits are ensured by design, test, or statistical analysis.

Parameter Conditions Min Typ Max Units

Resolution 10 Bits

DNL VCC = 5V ±1 LSB

INL VCC = 5V ±3 LSB

Offset Error VCC = 5V +2.5, −1 LSB

Gain Error VCC = 5V +0.5, −2.5 LSB

Input Voltage Range 4.5V ≤VCC < 5.5V 0 VCC V

Analog Input Leakage Current 0.5 µA

Analog Input Resistance(1) 6k Ω

Analog Input Capacitance 7 pF

Conversion Clock Period 4.5V ≤VCC < 5.5V 0.8 30 µs

Conversion Time (including S/H Time) 15 A/D

Conversion

Clock

Cycles

Operating Current on AVCC AVCC = 5.5V 0.2 0.6 mA

(1) Resistance between the device input and the internal sample and hold capacitance.

Figure 3-1. MICROWIRE/PLUS Timing

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

4 Pin Descriptions

The COP8CBR/CCR/CDR I/O structure enables designers to reconfigure the microcontroller's I/O

functions with a single instruction. Each individual I/O pin can be independently configured as output pin

low, output high, input with high impedance or input with weak pull-up device. A typical example is the use

of I/O pins as the keyboard matrix input lines. The input lines can be programmed with internal weak pull-

ups so that the input lines read logic high when the keys are all open. With a key closure, the

corresponding input line will read a logic zero since the weak pull-up can easily be overdriven. When the

key is released, the internal weak pull-up will pull the input line back to logic high. This eliminates the need

for external pull-up resistors. The high current options are available for driving LEDs, motors and

speakers. This flexibility helps to ensure a cleaner design, with less external components and lower costs.

Below is the general description of all available pins.

VCC and GND are the power supply pins. All VCC and GND pins must be connected.

Users of the WQFN package are cautioned to be aware that the central metal area and the pin 1 index

mark on the bottom of the package may be connected to GND. See figure below:

Figure 4-1. WQFN Package Bottom View

CKI is the clock input. This can be connected (in conjunction with CKO) to an external crystal circuit to

form a crystal oscillator. See Oscillator Description section.

RESET is the master reset input. See Reset description section.

AVCC is the Analog Supply for A/D converter. It should be connected to VCC externally. This is also the top

of the resistor ladder D/A converter used within the A/D converter.

AGND is the ground pin for the A/D converter. It should be connected to GND externally. This is also the

bottom of the resistor ladder D/A converter used within the A/D converter.

The device contains up to six bidirectional 8-bit I/O ports (A, B, C, E, G and L) and one 4-bit I/O port (F),

where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L

and G), output or TRI-STATE under program control. Three data memory address locations are allocated

for each of these I/O ports. Each I/O port has three associated 8-bit memory mapped registers, the

CONFIGURATION register, the output DATA register and the Pin input register. (See the memory map for

the various addresses associated with the I/O ports.) Figure 4-2 shows the I/O port configurations. The

DATA and CONFIGURATION registers allow for each port bit to be individually configured under software

control as shown below:

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

DATA

CONFIGURATION Register Port Set-Up

0 0 Hi-Z Input

(TRI-STATE Output)

0 1 Input with Weak Pull-Up

1 0 Push-Pull Zero Output

1 1 Push-Pull One Output

Port A is an 8-bit I/O port. All A pins have Schmitt triggers on the inputs. The 44-pin package does not

have a full 8-bit port and contains some unbonded, floating pads internally on the chip. The binary value

read from these bits is undetermined. The application software should mask out these unknown bits when

reading the Port A register, or use only bit-access program instructions when accessing Port A. These

unconnected bits draw power only when they are addressed (i.e., in brief spikes). Additionally, if Port A is

being used with some combination of digital inputs and analog inputs, the analog inputs will read as

undetermined values and should be masked out by software.

Port A supports the analog inputs for the A/D converter. Port A has the following alternate pin functions:

A7 Analog Channel 7

A6 Analog Channel 6

A5 Analog Channel 5

A4 Analog Channel 4

A3 Analog Channel 3

A2 Analog Channel 2

A1 Analog Channel 1

A0 Analog Channel 0

Port B is an 8-bit I/O port. All B pins have Schmitt triggers on the inputs. If Port B is being used with some

combination of digital inputs and analog inputs, the analog inputs will read as undetermined values. The

application software should mask out these unknown bits when reading the Port B register, or use only bit-

access program instructions when accessing Port B.

Port B supports the analog inputs for the A/D converter. Port B has the following alternate pin functions:

B7 Analog Channel 15 or A/D Input

B6 Analog Channel 14 or Analog Multiplexor Output

B5 Analog Channel 13 or Analog Multiplexor Output

B4 Analog Channel 12

B3 Analog Channel 11

B2 Analog Channel 10

B1 Analog Channel 9

B0 Analog Channel 8

Port C is an 8-bit I/O port. The 44-pin device does not offer Port C. The unavailable pins are not

terminated. A read operation on these unterminated pins will return unpredictable values. On this device,

the associated Port C Data and Configuration registers should not be used. All C pins have Schmitt

triggers on the inputs. Port C draws no power when unbonded.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Port E is an 8-bit I/O Port. The 44-pin device does not offer Port E. The unavailable pins are not

terminated. A read operation on these unterminated pins will return unpredictable values. On this device,

the associated Port E Data and Configuration registers should not be used. All E pins have Schmitt

triggers on the inputs. Port E draws no power when unbonded.

Port F is a 4-bit I/O Port. All F pins have Schmitt triggers on the inputs.

The 68-pin package has fewer than eight Port F pins, and contains unbonded, floating pads internally on

the chip. The binary values read from these bits are undetermined. The application software should mask

out these unknown bits when reading the Port F register, or use only bit-access program instructions when

accessing Port F. The unconnected bits draw power only when they are addressed (i.e., in brief spikes).

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-

Z input. All pins have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WATCHDOG

output with weak pull-up if the WATCHDOG feature is selected by the Option register. The pin is a

general purpose I/O if WATCHDOG feature is not selected. If WATCHDOG feature is selected, bit 1 of

the Port G configuration and data register does not have any effect on Pin G1 setup. G7 serves as the

dedicated output pin for the CKO clock output.

Since G6 is an input only pin and G7 is the dedicated CKO clock output pin, the associated bits in the

data and configuration registers for G6 and G7 are used for special purpose functions as outlined below.

Reading the G6 and G7 data bits will return zeros.

The device will be placed in the HALT mode by writing a “1” to bit 7 of the Port G Data Register. Similarly

the device will be placed in the IDLE mode by writing a “1” to bit 6 of the Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with

the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay

after HALT when the R/C clock configuration is used.

Config. Reg. Data Reg.

G7 CLKDLY HALT

G6 Alternate SK IDLE

Port G has the following alternate features:

G7 CKO Oscillator dedicated output

G6 SI (MICROWIRE/PLUS Serial Data Input)

G5 SK (MICROWIRE/PLUS Serial Clock)

G4 SO (MICROWIRE/PLUS Serial Data Output)

G3 T1A (Timer T1 I/O)

G2 T1B (Timer T1 Capture Input)

G1 WDOUT WATCHDOG and/or Clock Monitor if WATCHDOG enabled, otherwise it is a

general purpose I/O

G0 INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.

Port L supports the Multi-Input Wake-up feature on all eight pins. Port L has the following alternate pin

functions:

L7 Multi-Input Wake-up or T3B (Timer T3B Input)

L6 Multi-Input Wake-up or T3A (Timer T3A Input/Output)

L5 Multi-Input Wake-up or T2B (Timer T2B Input)

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

L4 Multi-input Wake-up or T2A (Timer T2A Input/Output)

L3 Multi-Input Wake-up and/or RDX (USART Receive)

L2 Multi-Input Wake-up or TDX (USART Transmit)

L1 Multi-Input Wake-up and/or CKX (USART Clock) (Low Speed Oscillator Output)

L0 Multi-Input Wake-up (Low Speed Oscillator Input)

Port D is an 8-bit output port that is preset high when RESET goes low. The user can tie two or more D

port outputs (except D2) together in order to get a higher drive.

NOTE

Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin

must ensure that the output voltages stay above 0.7 VCC to prevent the chip from entering

special modes. Also keep the external loading on D2 to less than 1000 pF.

Figure 4-2. I/O Port Configurations

Figure 4-3. I/O Port Configurations—Output Mode

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Figure 4-4. I/O Port Configurations—Input Mode

4.1 EMULATION CONNECTION

Connection to the emulation system is made via a 2 x 7 connector which interrupts the continuity of the

RESET, G0, G1, G2 and G3 signals between the COP8 device and the rest of the target system (as

shown in Figure 4-5). This connector can be designed into the production pc board and can be replaced

by jumpers or signal traces when emulation is no longer necessary. The emulator will replicate all

functions of G0 - G3 and RESET. For proper operation, no connection should be made on the device side

of the emulator connector.

Figure 4-5. Emulation Connection

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

5 Functional Description

This table assumes that the control flag MSEL is set.

The architecture of the device is a modified Harvard architecture. With the Harvard architecture, the

program memory (Flash) is separate from the data store memory (RAM). Both Program Memory and Data

Memory have their own separate addressing space with separate address buses. The architecture, though

based on the Harvard architecture, permits transfer of data from Flash Memory to RAM.

5.1 CPU REGISTERS

The CPU can do an 8-bit addition, subtraction, logical or shift operation in one instruction (tC) cycle time.

There are six CPU registers:

A is the 8-bit Accumulator Register

PC is the 15-bit Program Counter Register

PU is the upper 7 bits of the program counter (PC)

PL is the lower 8 bits of the program counter (PC)

B is an 8-bit RAM address pointer, which can be optionally post auto incremented or decremented.

X is an 8-bit alternate RAM address pointer, which can be optionally post auto incremented or

decremented.

S is the 8-bit Data Segment Address Register used to extend the lower half of the address range (00 to

7F) into 256 data segments of 128 bytes each.

SP is the 8-bit stack pointer, which points to the subroutine/interrupt stack (in RAM). With reset the SP is

initialized to RAM address 06F Hex. The SP is decremented as items are pushed onto the stack. SP

points to the next available location on the stack.

All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program

Counter (PC).

5.2 PROGRAM MEMORY

The program memory consists of 32,768 bytes of Flash Memory. These bytes may hold program

instructions or constant data (data tables for the LAID instruction, jump vectors for the JID instruction, and

interrupt vectors for the VIS instruction). The program memory is addressed by the 15-bit program counter

(PC). All interrupts in the device vector to program memory location 00FF Hex. The program memory

reads 00 Hex in the erased state. Program execution starts at location 0 after RESET.

If a Return instruction is executed when the SP contains 6F (hex), instruction execution will continue from

Program Memory location 7FFF (hex). If location 7FFF is accessed by an instruction fetch, the Flash

Memory will return a value of 00. This is the opcode for the INTR instruction and will cause a Software

Trap.

For the purpose of erasing and rewriting the Flash Memory, it is organized in pages of 128 bytes.

5.3 DATA MEMORY

The data memory address space includes the on-chip RAM and data registers, the I/O registers

(Configuration, Data and Pin), the control registers, the MICROWIRE/PLUS SIO shift register, and the

various registers, and counters associated with the timers and the USART (with the exception of the IDLE

timer). Data memory is addressed directly by the instruction or indirectly by the B, X and SP pointers.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

The data memory consists of 1024 bytes of RAM. Sixteen bytes of RAM are mapped as “registers” at

addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested

with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B

and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the

other registers being available for general usage.

The instruction set permits any bit in memory to be set, reset or tested. All I/O and registers (except A and

PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset

and tested. The accumulator (A) bits can also be directly and individually tested.

Note: RAM contents are undefined upon power-up.

5.4 DATA MEMORY SEGMENT RAM EXTENSION

Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register

(S).

The data store memory is either addressed directly by a single byte address within the instruction, or

indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This

single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this

single-byte address divides the data store memory into two separate sections as outlined previously. With

the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is

memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper

bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is

extended. If this upper bit equals one (representing address range 0080 to 00FF), then address extension

does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S

is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F, where XX represents

the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses

0100 to 017F for data segment 1, 0200 to 027F for data segment 2, etc., up to FF00 to FF7F for data

segment 255. The base address range from 0000 to 007F represents data segment 0.

Figure 5-1 illustrates how the S register data memory extension is used in extending the lower half of the

base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing

range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128 bytes

each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are

available for all data segments. The S register must be changed under program control to move from one

data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory

registers, I/O registers, control registers, etc.) is always available regardless of the contents of the S

extension.

The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment

(Segment 0), regardless of the contents of the S register. The S register is not changed by these

instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always located in the

base segment. The stack pointer will be initialized to point at data memory location 006F as a result of

reset.

The 128 bytes of RAM contained in the base segment are split between the lower and upper base

segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the lower base segment,

while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0

to 00FF of the upper base segment. No RAM is located at the upper sixteen addresses (0070 to 007F) of

the lower base segment.

Additional RAM beyond these initial 128 bytes, however, will always be memory mapped in groups of 128

bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment. The

additional 892 bytes of RAM in this device are memory mapped at address locations 0100 to 017F

through 0700 to 077F hex.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Figure 5-1. RAM Organization

5.4.1 Virtual EEPROM

The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to

use the flash program memory to back up user defined sections of RAM. This effectively provides the user

with the same nonvolatile data storage as EEPROM. Management, and even the amount of memory

used, are the responsibility of the user, however the flash memory read and write functions have been

provided in the boot ROM.

One typical method of using the Virtual EEPROM feature would be for the user to copy the data to RAM

during system initialization, periodically, and if necessary, erase the page of Flash and copy the contents

of the RAM back to the Flash.

5.5 OPTION REGISTER

The Option register, located at address 0x7FFF in the Flash Program Memory, is used to configure the

user selectable security, WATCHDOG, and HALT options. The register can be programmed only in

external Flash Memory programming or ISP Programming modes. Therefore, the register must be

programmed at the same time as the program memory. The contents of the Option register shipped from

the factory read 00 Hex.

The format of the Option register is as follows:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WATCH

Reserved SECURITY Reserved HALT FLEX

DOG

Bits 7, 6 These bits are reserved and must be 0.

Bit 5

= 1 Security enabled. Flash Memory read and write are not allowed except in User ISP/Virtual E2

commands. Mass Erase is allowed.

= 0 Security disabled. Flash Memory read and write are allowed.

Bits 4, 3 These bits are reserved and must be 0.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Bit 2

= 1 WATCHDOG feature disabled. G1 is a general purpose I/O.

= 0 WATCHDOG feature enabled. G1 pin is WATCHDOG output with weak pullup.

Bit 1

= 1 HALT mode disabled.

= 0 HALT mode enabled.

Bit 0

= 1 Execution following RESET will be from Flash Memory.

= 0 Flash Memory is erased. Execution following RESET will be from Boot ROM with the

MICROWIRE/PLUS ISP routines.

The COP8 assembler defines a special ROM section type, CONF, into which the Option Register data

may be coded. The Option Register is programmed automatically by programmers that are certified by TI.

The user needs to ensure that the FLEX bit will be set when the device is programmed.

The following examples illustrate the declaration of the Option Register.

Syntax:

[label:].sect config, conf

.db value ;1 byte,

;configures

;options

.endsect

Example: The following sets a value in the Option Register and User Identification for a COP8CBR9HVA7.

The Option Register bit values shown select options: Security disabled, WATCHDOG enabled HALT

mode enabled and execution will commence from Flash Memory.

.chip 8CBR

.sect option, conf

.db 0x01 ;wd, halt, flex

.endsect

...

.end start

Note: All programmers certified for programming this family of parts will support programming of the

Option Register. Please contact TI or your device programmer supplier for more information.

5.6 SECURITY

The device has a security feature which, when enabled, prevents external reading of the Flash program

memory. The security bit in the Option Register determines, whether security is enabled or disabled. If the

security feature is disabled, the contents of the internal Flash Memory may be read by external

programmers or by the built in MICROWIRE/PLUS serial interface ISP. Security must be enforced by

the user when the contents of the Flash Memory are accessed via the user ISP or Virtual EEPROM

capability.

If the security feature is enabled, then any attempt to externally read the contents of the Flash Memory will

result in the value FF (hex) being read from all program locations (except the Option Register). In addition,

with the security feature enabled, the write operation to the Flash program memory and Option Register is

inhibited. Page Erases are also inhibited when the security feature is enabled. The Option Register is

readable regardless of the state of the security bit by accessing location FFFF (hex). Mass Erase

Operations are possible regardless of the state of the security bit.

The security bit can be erased only by a Mass Erase of the entire contents of the Flash unless Flash

operation is under the control of User ISP functions.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

NOTE

The actual memory address of the Option Register is 7FFF (hex), however the

MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

The entire Option Register must be programmed at one time and cannot be rewritten without first erasing

the entire last page of Flash Memory.

5.7 RESET

The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated.

The Brownout Reset feature is not available on the COP8CDR9.

Figure 5-2. Reset Logic

The following occurs upon initialization:

Port A: TRI-STATE (High Impedance Input)

Port B: TRI-STATE (High Impedance Input)

Port C: TRI-STATE (High Impedance Input)

Port D: HIGH

Port E: TRI-STATE (High Impedance Input)

Port F: TRI-STATE (High Impedance Input)

Port G: TRI-STATE (High Impedance Input). Exceptions: If Watchdog is enabled, then G1 is

Watchdog output. G0 and G2 have their weak pull-up enabled during RESET.

Port L: TRI-STATE (High Impedance Input)

PC: CLEARED to 0000

PSW, CNTRL and ICNTRL registers: CLEARED

SIOR:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

T2CNTRL: CLEARED

T3CNTRL: CLEARED

HSTCR: CLEARED

ITMR: Cleared except Bit 6 (HSON) = 1

Accumulator, Timer 1, Timer 2 and Timer 3:

RANDOM after RESET

WKEN, WKEDG: CLEARED

WKPND: RANDOM

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

SP (Stack Pointer):

Initialized to RAM address 06F Hex

B and X Pointers:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

S Register: CLEARED

RAM:

UNAFFECTED after RESET with power already applied

RANDOM after RESET at power-on

USART:

PSR, ENU, ENUR, ENUI: Cleared except the TBMT bit

which is set to one.

ANALOG TO DIGITAL CONVERTER:

ENAD: CLEARED

ADRSTH: RANDOM

ADRSTL: RANDOM

ISP CONTROL:

ISPADLO: CLEARED

ISPADHI: CLEARED

PGMTIM: PRESET TO VALUE FOR 10 MHz CKI

WATCHDOG (if enabled):

The device comes out of reset with both the WATCHDOG logic and the Clock Monitor

detector armed, with the WATCHDOG service window bits set and the Clock Monitor bit set.

The WATCHDOG and Clock Monitor circuits are inhibited during reset. The WATCHDOG

service window bits being initialized high default to the maximum WATCHDOG service

window of 64k T0 clock cycles. The Clock Monitor bit being initialized high will cause a Clock

Monitor error following reset if the clock has not reached the minimum specified frequency at

the termination of reset. A Clock Monitor error will cause an active low error output on pin

G1. This error output will continue until 16–32 T0 clock cycles following the clock frequency

reaching the minimum specified value, at which time the G1 output will go high.

5.7.1 External Reset

The RESET input when pulled low initializes the device. The RESET pin must be held low for a minimum

of one instruction cycle to ensure a valid reset. During Power-Up initialization, the user must ensure that

the RESET pin of a device without the Brownout Reset feature is held low until the device is within the

specified VCC voltage. Any rising edge on the RESET pin while VCC is below the specified operating range

may cause unpredictable results. An R/C circuit on the RESET pin with a delay 5 times (5x) greater than

the power supply rise time is recommended. Reset should also be wide enough to ensure crystal start-up

upon Power-Up.

RESET may also be used to cause an exit from the HALT mode.

A recommended reset circuit for this device is shown in Figure 5-3.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Figure 5-3. Reset Circuit Using External Reset

5.7.2 On-Chip Brownout Reset

When enabled, the device generates an internal reset as VCC rises. While VCC is less than the specified

brownout voltage (Vbor), the device is held in the reset condition and the Idle Timer is preset with 00Fx

(240–256 tC). When VCC reaches a value greater than Vbor, the Idle Timer starts counting down. Upon

underflow of the Idle Timer, the internal reset is released and the device will start executing instructions.

This internal reset will perform the same functions as external reset. Once VCC is above the Vbor and this

initial Idle Timer time-out takes place, instruction execution begins and the Idle Timer can be used

normally. If, however, VCC drops below the selected Vbor, an internal reset is generated, and the Idle Timer

is preset with 00Fx. The device now waits until VCC is greater than Vbor and the countdown starts over.

When enabled, the functional operation of the device, at frequency, is ensured down to the Vbor level.

Figure 5-4. Brownout Reset Operation

One exception to the above is that the brownout circuit will insert a delay of approximately 3 ms on power

up or any time the VCC drops below a voltage of about 1.8V. The device will be held in Reset for the

duration of this delay before the Idle Timer starts counting the 240 to 256 tC. This delay starts as soon as

the VCC rises above the trigger voltage (approximately 1.8V). This behavior is shown in Figure 5-4.

In Case 1, VCC rises from 0V and the on-chip RESET is undefined until the supply is greater than

approximately 1.0V. At this time the brownout circuit becomes active and holds the device in RESET. As

the supply passes a level of about 1.8V, a delay of about 3 ms (td) is started and the Idle Timer is preset

to a value between 00F0 and 00FF (hex). Once VCC is greater than Vbor and tdhas expired, the Idle Timer

is allowed to count down (tid).

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Case 2 shows a subsequent dip in the supply voltage which goes below the approximate 1.8V level. As

VCC drops below Vbor, the internal RESET signal is asserted. When VCC rises back above the 1.8V level, td

is started. Since the power supply rise time is longer for this case, tdhas expired before VCC rises above

Vbor and tid starts immediately when VCC is greater than Vbor.

Case 3 shows a dip in the supply where VCC drops below Vbor, but not below 1.8V. On-chip RESET is

asserted when VCC goes below Vbor and tid starts as soon as the supply goes back above Vbor.

If the Brownout Reset feature is enabled, the internal reset will not be turned off until the Idle Timer

underflows. The internal reset will perform the same functions as external reset. The device is ensured to

operate at the specified frequency down to the specified brownout voltage. After the underflow, the logic is

designed such that no additional internal resets occur as long as VCC remains above the brownout

voltage.

The device is relatively immune to short duration negative-going VCC transients (glitches). It is essential

that good filtering of VCC be done to ensure that the brownout feature works correctly. Power supply

decoupling is vital even in battery powered systems.

There are two optional brownout voltages. The part numbers for the three versions of this device are:

COP8CBR, Vbor = low voltage range

COP8CCR, Vbor = high voltage range

COP8CDR, BOR is disabled.

Refer to the device specifications for the actual Vbor voltages.

High brownout voltage devices are ensured to operate at 10MHz down to the brownout voltage. Low

brownout voltage devices are ensured to operate at 3.33MHz down to the brownout voltage. Devices are

not ensured to operate at 10MHz down to the low brownout voltage.

Under no circumstances should the RESET pin be allowed to float. If the on-chip Brownout Reset feature

is being used, the RESET pin should be connected directly to VCC. The RESET input may also be

connected to an external pull-up resistor or to other external circuitry. Any rising edge on the RESET pin

while VCC is below the specified operating range may cause unpredictable results. The output of the

brownout reset detector will always preset the Idle Timer to a value between 00F0 and 00FF (240 to 256

tC). At this time, the internal reset will be generated.

If the BOR feature is disabled, then no internal resets are generated and the Idle Timer will power-up with

an unknown value. In this case, the external RESET must be used. When BOR is disabled, this on-chip

circuitry is disabled and draws no DC current.

The contents of data registers and RAM are unknown following the on-chip reset.

Figure 5-5. Reset Circuit Using Power-On Reset

5.8 OSCILLATOR CIRCUITS

The device has two crystal oscillators to facilitate low power operation while maintaining throughput when

required. Further information on the use of the two oscillators is found in Power Saving Features. The low

speed oscillator utilizes the L0 and L1 port pins. References in the following text to CKI will also apply to

L0 and references to G7/CKO will also apply to L1.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

5.8.1 Oscillator

CKI is the clock input while G7/CKO is the clock generator output to the crystal. An on-chip bias resistor

connected between CKI and CKO is provided to reduce system part count. The value of the resistor is in

the range of 0.5M to 2M (typically 1.0M). Table 5-1 shows the component values required for various

standard crystal values. Resistor R2 is on-chip, for the high speed oscillator, and is shown for reference.

Figure 5-6 and Figure 5-6 shows the crystal oscillator connection diagrams. A ceramic resonator of the

required frequency may be used in place of a crystal if the accuracy requirements are not quite as strict.

High Speed Oscillator Low Speed Oscillator

Figure 5-6. Crystal Oscillator

Table 5-1. Crystal Oscillator Configuration, TA= 25°C, VCC = 5V(1)

CKI Freq.

R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF) (MHz)

0 On Chip 18 18 10

0 On Chip 18 18 5

0 On Chip 18–36 18–36 1

5.6 On Chip 100 100–156 0.455

0 20 ** ** 32.768 kHz*

(1) *Applies to connection to low speed oscillator on port pins L0 and L1 only.

**See Note below.

The crystal and other oscillator components should be placed in close proximity to the CKI and CKO pins

to minimize printed circuit trace length.

The values for the external capacitors should be chosen to obtain the manufacturer's specified load

capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and

package (which can vary from 0 to 8 pF). The guideline in choosing these capacitors is:

Manufacturer's specified load cap = (C1* C2) / (C1+ C2)+Cparasitic

C2can be trimmed to obtain the desired frequency. C2should be less than or equal to C1.

NOTE

The low power design of the low speed oscillator makes it extremely sensitive to board

layout and load capacitance. The user should place the crystal and load capacitors within

1cm. of the device and must ensure that the above equation for load capacitance is strictly

followed. If these conditions are not met, the application may have problems with startup of

the low speed oscillator.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Table 5-2. Startup Times

CKI Frequency Startup Time

10 MHz 1–10 ms

3.33 MHz 3–10 ms

1 MHz 3–20 ms

455 kHz 10–30 ms

32 kHz (low speed oscillator) 2–5 sec

5.8.2 Clock Doubler

This device contains a frequency doubler that doubles the frequency of the oscillator selected to operate

the main microcontroller core. The details of how to select either the high speed oscillator or low speed

oscillator are described in, Power Saving Features. When the high speed oscillator connected to CKI

operates at 10 MHz, the internal clock frequency is 20 MHz, resulting in an instruction cycle time of 0.5 µs.

When the 32 kHz oscillator connected to L0 and L1 is selected, the internal clock frequency is 64 kHz,

resulting in an instruction cycle of 152.6 µs. The output of the clock doubler is called MCLK and is

referenced in many places within this document.

5.9 CONTROL REGISTERS

5.9.1 CNTRL Register (Address X′00EE)

T1C3 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0

Bit 7 Bit 0

The Timer1 (T1) and MICROWIRE/PLUS control register contains the following bits:

T1C3 Timer T1 mode control bit

T1C2 Timer T1 mode control bit

T1C1 Timer T1 mode control bit

T1C0 Timer T1 Start/Stop control in timer modes 1 and 2. T1 Underflow Interrupt Pending Flag in

timer mode 3

MSEL Selects G5 and G4 as MICROWIRE/PLUS signals SK and SO respectively

IEDG External interrupt edge polarity select (0 = Rising edge, 1 = Falling edge)

SL1 & SL0 Select the MICROWIRE/PLUS clock divide by (00 = 2, 01 = 4, 1x = 8)

5.9.2 PSW Register (Address X′00EF)

HC C T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 7 Bit 0

The PSW register contains the following select bits:

HC Half Carry Flag

CCarry Flag

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA in mode 1, T1 Underflow in Mode 2, T1A

capture edge in mode 3)

T1ENA Timer T1 Interrupt Enable for Timer Underflow or T1A Input capture edge

EXPND External interrupt pending

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

BUSY MICROWIRE/PLUS busy shifting flag

EXEN Enable external interrupt

GIE Global interrupt enable (enables interrupts)

The Half-Carry flag is also affected by all the instructions that affect the Carry flag. The SC (Set Carry)

and R/C (Reset Carry) instructions will respectively set or clear both the carry flags. In addition to the SC

and R/C instructions, ADC, SUBC, RRC and RLC instructions affect the Carry and Half Carry flags.

5.9.3 ICNTRL Register (Address X′00E8)

Unused LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB

Bit 7 Bit 0

The ICNTRL register contains the following bits:

LPEN L Port Interrupt Enable (Multi-Input Wake-up/Interrupt)

T0PND Timer T0 Interrupt pending

T0EN Timer T0 Interrupt Enable (Bit 12 toggle)

μWPND MICROWIRE/PLUS interrupt pending

μWEN Enable MICROWIRE/PLUS interrupt

T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge

T1ENB Timer T1 Interrupt Enable for T1B Input capture edge

5.9.4 T2CNTRL Register (Address X′00C6)

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB

Bit 7 Bit 0

The T2CNTRL register contains the following bits:

T2C3 Timer T2 mode control bit

T2C2 Timer T2 mode control bit

T2C1 Timer T2 mode control bit

T2C0 Timer T2 Start/Stop control in timer modes 1 and 2, Timer T2 Underflow Interrupt Pending

Flag in timer mode 3

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA in mode 1, T2 Underflow in mode 2, T2A

capture edge in mode 3)

T2ENA Timer T2 Interrupt Enable for Timer Underflow or T2A Input capture edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge

T2ENB Timer T2 Interrupt Enable for T2B Input capture edge

5.9.5 T3CNTRL Register (Address X′00B6)

T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB

Bit 7 Bit 0

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

The T3CNTRL register contains the following bits:

T3C3 Timer T3 mode control bit

T3C2 Timer T3 mode control bit

T3C1 Timer T3 mode control bit

T3C0 Timer T3 Start/Stop control in timer modes 1 and 2, Timer T3 Underflow Interrupt Pending

Flag in timer mode 3

T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A

capture edge in mode 3)

T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge

T3PNDB Timer T3 Interrupt Pending Flag for T3B capture edge

T3ENB Timer T3 Interrupt Enable for T3B Input capture edge

5.9.6 HSTCR Register (Address X′00AF)

Reserved T3HS T2HS

Bit 7 Bit 0

The HSTCR register contains the following bits:

T3HS Places Timer T3 in High Speed Mode.

T2HS Places Timer T2 in High Speed Mode.

5.9.7 ITMR Register (Address X′00CF)

CCKS

LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0

Bit 7 Bit 0

The ITMR register contains the following bits:

LSON Turns the low speed oscillator on or off.

HSON Turns the high speed oscillator on or off.

DCEN Selects the high speed oscillator or the low speed oscillator as the Idle Timer Clock.

CCKSEL Selects the high speed oscillator or the low speed oscillator as the primary CPU clock.

RSVD This bit is reserved and must be 0.

ITSEL2 Idle Timer period select bit.

ITSEL1 Idle Timer period select bit.

ITSEL0 Idle Timer period select bit.

5.9.8 ENAD Register (Address X′00CB)

ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX PSC ADBSY

Channel Select Mode Select Mux Out Prescale Busy

Bit 7 Bit 0

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

The ENAD register contains the following bits:

ADCH3 ADC channel select bit

ADCH2 ADC channel select bit

ADCH1 ADC channel select bit

ADCH0 ADC channel select bit

ADMOD Places the ADC in single-ended or differential mode.

MUX Enables the ADC multiplexor output.

PSC Switches the ADC clock between a divide by one or a divide by sixteen of MCLK.

ADBSY Signifies that the ADC is currently busy performing a conversion. When set by the user,

starts a conversion.

5.10 In-System Programming

5.10.1 INTRODUCTION

This device provides the capability to program the program memory while installed in an application board.

This feature is called In System Programming (ISP). It provides a means of ISP by using the

MICROWIRE/PLUS, or the user can provide his own, customized ISP routine. The factory installed ISP

uses the MICROWIRE/PLUS port. The user can provide his own ISP routine that uses any of the

capabilities of the device, such as USART, parallel port, etc.

5.10.2 FUNCTIONAL DESCRIPTION

The organization of the ISP feature consists of the user flash program memory, the factory boot ROM, and

some registers dedicated to performing the ISP function. See Figure 5-7 for a simplified block diagram.

The factory installed ISP that uses MICROWIRE/PLUS is located in the Boot ROM. The size of the Boot

ROM is 1K bytes and also contains code to facilitate in system emulation capability. If a user chooses to

write his own ISP routine, it must be located in the flash program memory.

Figure 5-7. Block Diagram of ISP

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

As described in Option Register, there is a bit, FLEX, that controls whether the device exits RESET

executing from the flash memory or the Boot ROM. The user must program the FLEX bit as appropriate

for the application. In the erased state, the FLEX bit = 0 and the device will power-up executing from Boot

ROM. When FLEX = 0, this assumes that either the MICROWIRE/PLUS ISP routine or external

programming is being used to program the device. If using the MICROWIRE/PLUS ISP routine, the

software in the boot ROM will monitor the MICROWIRE/PLUS for commands to program the flash

memory. When programming the flash program memory is complete, the FLEX bit will have to be

programmed to a 1 and the device will have to be reset, either by pulling external Reset to ground or by a

MICROWIRE/PLUS ISP EXIT command, before execution from flash program memory will occur.

If FLEX = 1, upon exiting Reset, the device will begin executing from location 0000 in the flash program

memory. The assumption, here, is that either the application is not using ISP, is using MICROWIRE/PLUS

ISP by jumping to it within the application code, or is using a customized ISP routine. If a customized ISP

routine is being used, then it must be programmed into the flash memory by means of the

MICROWIRE/PLUS ISP or external programming as described in the preceding paragraph.

5.10.3 REGISTERS

There are six registers required to support ISP: Address Register Hi byte (ISPADHI), Address Register

Low byte (ISPADLO), Read Data Register (ISPRD), Write Data Register (ISPWR), Write Timing Register

(PGMTIM), and the Control Register (ISPCNTRL). The ISPCNTRL Register is not available to the user.

5.10.3.1 ISP Address Registers

The address registers (ISPADHI & ISPADLO) are used to specify the address of the byte of data being

written or read. For page erase operations, the address of the beginning of the page should be loaded.

For mass erase operations, 0000 must be placed into the address registers. When reading the Option

cleared to 00 on Reset. These registers can be loaded from either flash program memory or Boot ROM

and must be maintained for the entire duration of the operation.

NOTE

The actual memory address of the Option Register is 7FFF (hex), however the

MICROWIRE/PLUS ISP routines require the address FFFF (hex) to be used to read the

Option Register when the Flash Memory is secured.

Table 5-3. High Byte of ISP Address

ISPADHi

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr 15 Addr 14 Addr 13 Addr 12 Addr 11 Addr 10 Addr 9 Addr 8

Table 5-4. Low Byte of ISP AddressThis table assumes that the control flag

MSEL is set.

ISPADLO

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr 7 Addr 6 Addr 5 Addr 4 Addr 3 Addr 2 Addr 1 Addr 0

5.10.3.2 ISP Read Data Register

The Read Data Register (ISPRD) contains the value read back from a read operation. This register can be

accessed from either flash program memory or Boot ROM. This register is undefined on Reset.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Table 5-5. ISP Read Data Register

ISPRD

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

5.10.3.3 ISP Write Data RegisterThis table assumes that the control flag MSEL is set.

The Write Data Register (ISPWR) contains the data to be written into the specified address. This register

is undetermined on Reset. This register can be accessed from either flash program memory or Boot ROM.

The Write Data register must be maintained for the entire duration of the operation.

Table 5-6. ISP Write Data Register

ISPWR

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

5.10.3.4 ISP Write Timing Register

The Write Timing Register (PGMTIM) is used to control the width of the timing pulses for write and erase

operations. The value to be written into this register is dependent on the frequency of CKI and is shown in

Table 5-7. This register must be written before any write or erase operation can take place. It only needs

to be loaded once, for each value of CKI frequency. This register can be loaded from either flash program

memory or Boot ROM and must be maintained for the entire duration of the operation. The

MICROWIRE/PLUS ISP routine that is resident in the boot ROM requires that this Register be defined

prior to any access to the Flash memory. Refer to Microwire for more information on available ISP

commands. On Reset, the PGMTIM register is loaded with the value that corresponds to 10 MHz

frequency for CKI.

Table 5-7. PGMTIM Register Format

PGMTIM

76543210

0 0 0 0 0 0 0 1 25 kHz–33.3 kHz

0 0 0 0 0 0 1 0 37.5 kHz–50 kHz

0 0 0 0 0 0 1 1 50 kHz–66.67 kHz

0 0 0 0 0 1 0 0 62.5 kHz–83.3 kHz

0 0 0 0 0 1 0 1 75 kHz–100 kHz

0 0 0 0 0 1 1 1 100 kHz–133 kHz

0 0 0 0 1 0 0 0 112.5 kHz–150 kHz

0 0 0 0 1 0 1 1 150 kHz–200 kHz

0 0 0 0 1 1 1 1 200 kHz–266.67 kHz

0 0 0 1 0 0 0 1 225 kHz–300 kHz

0 0 0 1 0 1 1 1 300 kHz–400 kHz

0 0 0 1 1 1 0 1 375 kHz–500 kHz

0 0 1 0 0 1 1 1 500 kHz–666.67 kHz

0 0 1 0 1 1 1 1 600 kHz–800 kHz

0 0 1 1 1 1 1 1 800 kHz–1.067 MHz

0 1 0 0 0 1 1 1 1 MHz–1.33 MHz

0 1 0 0 1 0 0 0 1.125 MHz–1.5 MHz

0 1 0 0 1 0 1 1 1.5 MHz–2 MHz

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Table 5-7. PGMTIM Register Format (continued)

PGMTIM

76543210

0 1 0 0 1 1 1 1 2 MHz–2.67 MHz

0 1 0 1 0 1 0 0 2.625 MHz–3.5 MHz

0 1 0 1 1 0 1 1 3.5 MHz–4.67 MHz

0 1 1 0 0 0 1 1 4.5 MHz–6 MHz

0 1 1 0 1 1 1 1 6 MHz–8 MHz

0 1 1 1 1 0 1 1 7.5 MHz–10 MHz

R R/W R/W R/W R/W R/W R/W R/W

5.10.4 MANEUVERING BACK AND FORTH BETWEEN FLASH MEMORY AND BOOT ROM

When using ISP, at some point, it will be necessary to maneuver between the flash program memory and

the Boot ROM, even when using customized ISP routines. This is because it's not possible to execute

from the flash program memory while it's being programmed.

Two instructions are available to perform the jumping back and forth: Jump to Boot (JSRB) and Return to

Flash (RETF). The JSRB instruction is used to jump from flash memory to Boot ROM, and the RETF is

used to return from the Boot ROM back to the flash program memory. See Instruction Set for specific

details on the operation of these instructions.

The JSRB instruction must be used in conjunction with the Key register. This is to prevent jumping to the

Boot ROM in the event of run-away software. For the JSRB instruction to actually jump to the Boot ROM,

the Key bit must be set. This is done by writing the value shown in Table 5-8 to the Key register. The Key

is a 6 bit key and if the key matches, the KEY bit will be set for 8 instruction cycles. The JSRB instruction

must be executed while the KEY bit is set. If the KEY does not match, then the KEY bit will not be set and

the JSRB will jump to the specified location in the flash memory. In emulation mode, if a breakpoint is

encountered while the KEY is set, the counter that counts the instruction cycles will be frozen until the

breakpoint condition is cleared. If an interrupt occurs while the key is set, the key will expire before

interrupt service is complete. It is recommended that the software globally disable interrupts before setting

the key. The Key register is a memory mapped register. Its format when writing is shown in Table 5-8. In

normal operation, it is not necessary to test the KEY bit before using the JSRB instruction. The additional

instructions required to test the key may cause the key to time-out before the JSRB can be executed.

Table 5-8. KEY Register Write Format

KEY When Writing

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 0 0 1 1 0 X X

Bits 7–2: Key value that must be written to set the KEY bit.

Bits 1–0: Don't care.

5.10.5 FORCED EXECUTION FROM BOOT ROM

When the user is developing a customized ISP routine, code lockups due to software errors may be

encountered. The normal, and preferred, method to recover from these conditions is to reprogram the

device with the corrected code by either an external parallel programmer or the emulation tools. As a last

resort, when this equipment is not available, there is a hardware method to get out of these lockups and

force execution from the Boot ROM MICROWIRE/PLUS routine. The customer will then be able to erase

the Flash Memory code and start over.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

The method to force this condition is to drive the G6 pin to high voltage (2 x VCC) and activate Reset. The

high voltage condition on G6 must not be applied before VCC is valid and stable, and must be held for at

least 3 instruction cycles longer than Reset is active. This special condition will bypass checking the state

of the Flex bit in the Option Register and will start execution from location 0000 in the Boot ROM. In this

state, the user can input the appropriate commands, using MICROWIRE/PLUS, to erase the flash

program memory and reprogram it. If the device is subsequently reset before the Flex bit has been erased

by specific Page Erase or Mass Erase ISP commands, execution will start from location 0000 in the Flash

program memory. The high voltage (2 x VCC) on G6 will not erase either the Flex or the Security bit in the

Option Register. The Security bit, if set, can only be erased by a Mass Erase of the entire contents of the

Flash Memory unless under the control of User ISP routines in the Application Program.

While the G6 pin is at high voltage, the Load Clock will be output onto G5, which will look like an SK clock

to the MICROWIRE/PLUS routine executing in slave mode. However, when G6 is at high voltage, the G6

input will also look like a logic 1. The MICROWIRE/PLUS routine in Boot ROM monitors the G6 input,

waits for it to go low, debounces it, and then enables the ISP routine. CAUTION: The Load clock on G5

could be in conflict with the user's external SK. It is up to the user to resolve this conflict, as this condition

is considered a minor issue that's only encountered during software development. The user should also

be cautious of the high voltage applied to the G6 pin. This high voltage could damage other

circuitry connected to the G6 pin (e.g. the parallel port of a PC). The user may wish to disconnect

other circuitry while G6 is connected to the high voltage.

VCC must be valid and stable before high voltage is applied to G6.

The correct sequence to be used to force execution from Boot ROM is :

1. Disconnect G6 from the source of data for MICROWIRE/PLUS ISP.

2. Apply VCC to the device.

3. Pull RESET Low.

4. After VCC is valid and stable, connect a voltage between 2 x VCC and VCC+7V to the G6 pin. Ensure

that the rise time of the high voltage on G6 is slower than the minimum in the Electrical Specifications.

Figure 5-8 shows a possible circuit dliagram for implementing the 2 x VCC. Be aware of the typical input

current on the G6 pin when the high voltage is applied. The resistor used in the RC network, and the

high voltage used, should be chosen to keep the high voltage at the G6 pin between 2 x VCC and

VCC+7V.

5. Pull RESET High.

6. After a delay of at least three instruction cycles, remove the high voltage from G6.

Figure 5-8. Circuit Diagram for Implementing the 2 x VCC

5.10.6 RETURN TO FLASH MEMORY WITHOUT HARDWARE RESET

After programming the entire program memory, including options, it is necessary to exit the Boot ROM and

return to the flash program memory for program execution. Upon receipt and completion of the EXIT

command through the MICROWIRE/PLUS ISP, the ISP code will reset the part and begin execution from

the flash program memory as described in the Reset section. This assumes that the FLEX bit in the

Option register was programmed to 1.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

5.10.7 MICROWIRE/PLUS ISP

TI Semiconductor provides a program, which is available from our web site at www.ti.com, that is capable

of programming a device from the parallel port of a PC. The software accepts manually input commands

and is capable of downloading standard Intel HEX Format files.

Users who wish to write their own MICROWIRE/PLUS ISP host software should refer to the COP8 FLASH

ISP User Manual, available from the same web site. This document includes details of command format

and delays necessary between command bytes.

The MICROWIRE/PLUS ISP supports the following features and commands:

• Write a value to the ISP Write Timing Register. NOTE: This must be the first command after entering

MICROWIRE/PLUS ISP mode.

• Erase the entire flash program memory (mass erase).

• Erase a page at a specified address.

• Read Option register.

• Read a byte from a specified address.

• Write a byte to a specified address.

• Read multiple bytes starting at a specified address.

• Write multiple bytes starting at a specified address.

• Exit ISP and return execution to flash program memory.

The following table lists the MICROWIRE/PLUS ISP commands and provides information on required

parameters and return values.

Table 5-9. MICROWIRE/PLUS ISP Commands

Command

Command Function Parameters Return Data

Value (Hex)

PGMTIM_SET Write Pulse Timing 0x3B Value N/A

PAGE_ERASE Page Erase 0xB3 Starting Address of Page N/A

MASS_ERASE Mass Erase 0xBF Confirmation Code N/A (The entire Flash

Memory will be erased)

READ_BYTE Read Byte 0x1D Address High, Address Data Byte if Security not

Low set. 0xFF if Security set.

Option Register if address

= 0xFFFF, regardless of

Security

BLOCKR Block Read 0xA3 Address High, Address n Data Bytes if Security

Low, Byte Count (n) High, not set.

Byte Count (n) Low n Bytes of 0xFF if Security

0≤n≤32767 set.

WRITE_BYTE Write Byte 0x71 Address High, Address N/A

Low, Data Byte

BLOCKW Block Write 0x8F Address High, Address N/A

Low, Byte Count (0 ≤n≤

16), n Data Bytes

EXIT EXIT 0xD3 N/A N/A (Device will Reset)

INVALID N/A Any other invalid N/A

command will be ignored

5.10.8 USER ISP AND VIRTUAL E2

The following commands will support transferring blocks of data from RAM to flash program memory, and

vice-versa. The user is expected to enforce application security in this case.

• Erase the entire flash program memory (mass erase). NOTE: Execution of this command will force the

device into the MICROWIRE/PLUS ISP mode.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

• Erase a page of flash memory at a specified address.

• Read a byte from a specified address.

• Write a byte to a specified address.

• Copy a block of data from RAM into flash program memory.

• Copy a block of data from program flash memory to RAM.

The following table lists the User ISP/Virtual E2commands, required parameters and return data, if

applicable. The command entry point is used as an argument to the JSRB instruction. Table 5-11 lists the

Ram locations and Peripheral Registers, used for User ISP and Virtual E2, and their expected contents.

Please refer to the COP8 FLASH ISP User Manual for additional information and programming examples

on the use of User ISP and Virtual E2.

Table 5-10. User ISP/Virtual E2Entry Points

Command/ Command

Function Parameters Return Data

Label Entry Point

cpgerase Page Erase 0x17 Register ISPADHI is loaded by the user with N/A (A page of memory beginning at

the high byte of the address. ISPADHI, ISPADLO will be erased)

with the low byte of the address.

cmserase Mass Erase 0x1A Accumulator A contains the confirmation N/A (The entire Flash Memory will be

key 0x55. erased)

creadbf Read Byte 0x11 Register ISPADHI is loaded by the user with Data Byte in Register ISPRD.

the high byte of the address.

with the low byte of the address.

cblockr Block Read 0x26 Register ISPADHI is loaded by the user with n Data Bytes, Data will be returned

the high byte of the address. beginning at a location pointed to by the

with the low byte of the address.

X pointer contains the beginning RAM

address where the result(s) will be returned.

number of n bytes to read (0 ≤n≤255). It is

up to the user to setup the segment register.

cwritebf Write Byte 0x14 Register ISPADHI is loaded by the user with N/A

the high byte of the address.

with the low byte of the address.

be written.

cblockw Block Write 0x23 Register ISPADHI is loaded by the user with N/A

the high byte of the address.

with the low byte of the address.

number of n bytes to write (0 ≤n≤16).

The combination of the BYTECOUNTLO

and the ISPADLO registers must be set

such that the operation will not cross a 64

byte boundary.

X pointer contains the beginning RAM

address of the data to be written.

It is up to the user to setup the segment

exit EXIT 0x62 N/A N/A (Device will Reset)

uwisp MICROWIRE/ 0x00 N/A N/A (Device will be in MICROWIRE/PLUS

PLUS ISP Mode. Must be terminated by

ISP Start MICROWIRE/PLUS ISP EXIT command

which will Reset the device)

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Table 5-11. Register and Bit Name Definitions

Purpose

Name Location

ISPADHI High byte of Flash Memory Address 0xA9

ISPADLO Low byte of Flash Memory Address 0xA8

ISPWR The user must store the byte to be written into this register before jumping into the write byte 0xAB

routine.

ISPRD Data will be returned to this register after the read byte routine execution. 0xAA

ISPKEY The ISPKEY Register is required to validate the JSRB instruction and must be loaded within 6 0xE2

instruction cycles before the JSRB.

BYTECOUNTLO Holds the count of the number of bytes to be read or written in block operations. 0xF1

PGMTIM Write Timing Register. This register must be loaded, by the user, with the proper value before 0xE1

execution of any USER ISP Write or Erase operation. Refer to Table 5-7 for the correct value.

Confirmation Code The user must place this code in the accumulator before execution of a Flash Memory Mass Erase A

command.

KEY Must be transferred to the ISPKEY register before execution of a JSRB instruction. 0x98

5.10.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM

1. The hardware will disable interrupts from occurring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when execution is returned to Flash Memory.

Subsequent interrupts, during ISP operation, from the same interrupt source will be lost. Interrupts

may occur between setting the KEY and executing the JSRB instruction. In this case, the KEY

will expire before the JSRB is executed. It is, therefore, recommended that the software globally

disable interrupts before setting the Key.

2. The security feature in the MICROWIRE/PLUS ISP is ensured by software and not hardware. When

executing the MICROWIRE/PLUS ISP routine, the security bit is checked prior to performing all

instructions. Only the mass erase command, write PGMTIM register, and reading the Option register is

permitted within the MICROWIRE/PLUS ISP routine. When the user is performing his own ISP, all

commands are permitted. The entry points from the user's ISP code do not check for security. It is the

burden of the user to ensure his own security. See the Security bit description in Option Register for

more details on security.

3. When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG

within the selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the

lower window is enabled, and the user can service the WATCHDOG anytime following exit from Boot

ROM, but must service it within the selected upper window to avoid a WATCHDOG error.

4. Block Writes can start anywhere in the page of Flash memory, but cannot cross half page or full page

boundaries.

5. The user must ensure that a page erase or a mass erase is executed between two consecutive

writes to the same location in Flash memory. Two writes to the same location without an

intervening erase will produce unpredicatable results including possible disturbance of

unassociated locations.

5.10.10 FLASH MEMORY DURABILITY CONSIDERATIONS

The endurance of the Flash Memory (number of possible Erase/Write cycles) is a function of the erase

time and the lowest temperature at which the erasure occurs. If the device is to be used at low

temperature, additional erase operations can be used to extend the erase time. The user can determine

how many times to erase a page based on what endurance is desired for the application (e.g. four page

erase cycles, each time a page erase is done, may be required to achieve the typical 100k Erase/Write

cycles in an application which may be operating down to 0°C). Also, the customer can verify that the entire

page is erased, with software, and request additional erase operations if desired.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Table 5-12. Typical Flash Memory Endurance

Low End of Operating Temp Range

Erase Time −40°C −20°C 0°C 25°C >25°C

1 ms 60k 60k 60k 100k 100k

2 ms 60k 60k 60k 100k 100k

3 ms 60k 60k 60k 100k 100k

4 ms 60k 60k 100k 100k 100k

5 ms 70k 70k 100k 100k 100k

6 ms 80k 80k 100k 100k 100k

7 ms 90k 90k 100k 100k 100k

8 ms 100k 100k 100k 100k 100k

5.11 Timers

The device contains a very versatile set of timers (T0, T1, T2 and T3). Timers T1, T2 and T3 and

associated autoreload/capture registers power up containing random data.

5.11.1 TIMER T0 (IDLE TIMER)

The device supports applications that require maintaining real time and low power with the IDLE mode.

This IDLE mode support is furnished by the IDLE Timer T0, which is a 16-bit timer. The user cannot read

or write to the IDLE Timer T0, which is a count down timer.

As described in Power Saving Features, the clock to the IDLE Timer depends on which mode the device

is in. If the device is in High Speed mode, the clock to the IDLE Timer is the instruction cycle clock (one-

fifth of the CKI frequency). If the device is in Dual Clock mode or Low Speed mode, the clock to the IDLE

Timer is the 32 kHz clock. For the remainder of this section, the term “selected clock” will refer to the clock

selected by the Power Save mode of the device. During Dual Clock and Low Speed modes, the divide by

10 that creates the instruction cycle clock is disabled, to minimize power consumption.

In addition to its time base function, the Timer T0 supports the following functions:

• Exit out of the Idle Mode (See Idle Mode description)

• WATCHDOG logic (See WATCHDOG description)

• Start up delay out of the HALT mode

• Start up delay from BOR

Figure 5-9 is a functional block diagram showing the structure of the IDLE Timer and its associated

interrupt logic.

Bits 11 through 15 of the ITMR register can be selected for triggering the IDLE Timer interrupt. Each time

the selected bit underflows (every 4k, 8k, 16k, 32k or 64k selected clocks), the IDLE Timer interrupt

pending bit T0PND is set, thus generating an interrupt (if enabled), and bit 6 of the Port G data register is

reset, thus causing an exit from the IDLE mode if the device is in that mode.

In order for an interrupt to be generated, the IDLE Timer interrupt enable bit T0EN must be set, and the

GIE (Global Interrupt Enable) bit must also be set. The T0PND flag and T0EN bit are bits 5 and 4 of the

ICNTRL register, respectively. The interrupt can be used for any purpose. Typically, it is used to perform a

task upon exit from the IDLE mode. For more information on the IDLE mode, refer to Power Saving

Features.

The Idle Timer period is selected by bits 0–2 of the ITMR register Bit 3 of the ITMR Register is reserved

and should not be used as a software flag. Bits 4 through 7 of the ITMR Register are used by the dual

clock and are described in Power Saving Features.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Figure 5-9. Functional Block Diagram for Idle Timer T0

Table 5-13. Idle Timer Window Length

Idle Timer Period

ITSEL2 ITSEL1 ITSEL0 High Speed Dual Clock or

Mode Low Speed Mode

0 0 0 4,096 inst. cycles 0.125 seconds

0 0 1 8,192 inst. cycles 0.25 seconds

0 1 0 16,384 inst. cycles 0.5 seconds

0 1 1 32,768 inst. cycles 1 second

1 0 0 65,536 inst. cycles 2 seconds

1 0 1 Reserved - Undefined

1 1 0 Reserved - Undefined

1 1 1 Reserved - Undefined

The ITSEL bits of the ITMR register are cleared on Reset and the Idle Timer period is reset to 4,096

instruction cycles.

5.11.1.1 ITMR Register

CCK

LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0

SEL

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bits 7–4: Described in Power Saving Features.

NOTE

Documentation for previous COP8 devices, which included the Programmable Idle Timer,

recommended the user write zero to the high order bits of the ITMR Register. If existing

programs are updated to use this device, writing zero to these bits will cause the device to

reset (see Power Saving Features).

RSVD: This bit is reserved and must be set to 0.

ITSEL2:0: Selects the Idle Timer period as described in Table 5-13, Idle Timer Window Length.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer

interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing

the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to

synchronize operation to the IDLE Timer.

5.11.2 TIMER T1, TIMER T2, AND TIMER T3

The device has a set of three powerful timer/counter blocks, T1, T2, and T3. Since T1, T2 and T3 are

identical, except for the high speed operation of T2 and T3, all comments are equally applicable to any of

the three timer blocks which will be referred to as Tx. Differences between the timers will be specifically

noted.

Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers,

RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O

required by the timer block, while the pin TxB is an input to the timer block. The timer block has three

operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture

mode.

The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.

5.11.2.1 Timer Operating Speeds

Each of the Tx timers, except T1, have the ability to operate at either the instruction cycle frequency (low

speed) or the internal clock frequency (MCLK). For 10 MHz CKI, the instruction cycle frequency is 2 MHz

and the internal clock frequency is 20 MHz. This feature is controlled by the High Speed Timer Control

appropriate TxHS bit to 1. For low speed operation, clear the appropriate TxHS bit to 0. This register is

cleared to 00 on Reset.

HSTCR

Bit Bit

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 1 0

0 0 0 0 0 0 T3HS T2HS

5.11.2.2 Mode 1. Processor Independent PWM Mode

One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timers

generate a “Processor Independent” PWM signal because once the timer is set up, no more action is

required from the CPU which translates to less software overhead and greater throughput. The user

software services the timer block only when the PWM parameters require updating. This capability is

provided by the fact that the timer has two separate 16-bit reload registers. One of the reload registers

contains the “ON” time while the other holds the “OFF” time. By contrast, a microcontroller that has only a

single reload register requires an additional software to update the reload value (alternate between the on-

time/off-time).

The timer can generate the PWM output with the width and duty cycle controlled by the values stored in

the reload registers. The reload registers control the countdown values and the reload values are

automatically written into the timer when it counts down through 0, generating interrupt on each reload.

Under software control and with minimal overhead, the PWM outputs are useful in controlling motors,

triacs, the intensity of displays, and in providing inputs for data acquisition and sine wave generators.

In this mode, the timer Tx counts down at a fixed rate of tC(T2 and T3 may be selected to operate from

MCLK). Upon every underflow the timer is alternately reloaded with the contents of supporting registers,

RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA.

Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the

Figure 5-10 shows a block diagram of the timer in PWM mode.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

The underflows can be programmed to toggle the TxA output pin. The underflows can also be

programmed to generate interrupts.

Underflows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user

must reset these pending flags under software control. Two control enable flags, TxENA and TxENB,

allow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag

TxENA will cause an interrupt when a timer underflow causes the RxA register to be reloaded into the

timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB

interrupts.

Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of

interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the

user may choose to interrupt on both edges of the PWM output.

Figure 5-10. Timer in PWM Mode

5.11.2.3 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent PWM mode described above. The main difference

is that the timer, Tx, is clocked by the input signal from the TxA pin after synchronization to the

appropriate internal clock (tCor MCLK). The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to

be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are latched

into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer

underflows.

In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the

TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the

TxPNDB flag.

Figure 5-11 shows a block diagram of the timer in External Event Counter mode.

NOTE

The PWM output is not available in this mode since the TxA pin is being used as the counter

input clock.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Figure 5-11. Timer in External Event Counter Mode

5.11.2.4 Mode 3. Input Capture Mode

The device can precisely measure external frequencies or time external events by placing the timer block,

Tx, in the input capture mode. In this mode, the reload registers serve as independent capture registers,

capturing the contents of the timer when an external event occurs (transition on the timer input pin). The

capture registers can be read while maintaining count, a feature that lets the user measure elapsed time

and time between events. By saving the timer value when the external event occurs, the time of the

external event is recorded. Most microcontrollers have a latency time because they cannot determine the

timer value when the external event occurs. The capture register eliminates the latency time, thereby

allowing the applications program to retrieve the timer value stored in the capture register.

In this mode, the timer Tx is constantly running at the fixed tCor MCLK rate. The two registers, RxA and

RxB, act as capture registers. Each register also acts in conjunction with a pin. The register RxA acts in

conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin.

The timer value gets copied over into the register when a trigger event occurs on its corresponding pin

after synchronization to the appropriate internal clock (tCor MCLK). Control bits, TxC3, TxC2 and TxC1,

allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for

each input pin can be specified independently.

The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified

trigger condition on the TxA and TxB pins will be respectively latched into the pending flags, TxPNDA and

TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the

TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin.

Similarly, the flag TxENB controls the interrupts from the TxB pin.

Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the

timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the

Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture

mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs

in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to

determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.

Figure 5-12 shows a block diagram of the timer T1 in Input Capture mode. T2 and T3 are identical to T1.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Figure 5-12. Timer in Input Capture Mode

5.11.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3 Timer mode control

TxC2 Timer mode control

TxC1 Timer mode control

TxC0 Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture)

TxPNDA Timer Interrupt Pending Flag

TxENA Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB Timer Interrupt Pending Flag

TxENB Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed in Table 5-14, Timer Operating Modes.

When the high speed timers are counting in high speed mode, directly altering the contents of the timer

upper or lower registers, the PWM outputs or the reload registers is not recommended. Bit operations can

be particularly problematic. Since any of these six registers or the PWM outputs can change as many as

ten times in a single instruction cycle, performing an SBIT or RBIT operation with the timer running can

produce unpredictable results. The recommended procedure is to stop the timer, perform any changes to

the timer, the PWM outputs or reload register values, and then re-start the timer. This warning does not

apply to the timer control register. Any type of read/write operation, including SBIT and RBIT may be

performed on this register in any operating mode.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Table 5-14. Timer Operating Modes

Interrupt A Source Interrupt B Source Timer Counts

Mode TxC3 TxC2 TxC1 Description On

1 0 1 PWM: TxA Toggle Autoreload RA Autoreload RB tCor MCLK

11 0 0 PWM: No TxA Toggle Autoreload RA Autoreload RB tCor MCLK

0 0 0 External Event Counter Timer Underflow Pos. TxB Edge TxA Pos. Edge

20 0 1 External Event Counter Timer Underflow Pos. TxB Edge TxA Neg. Edge

0 1 0 Captures: Pos. TxA Edge Pos. TxB Edge tCor MCLK

TxA Pos. Edge or Timer

TxB Pos. Edge Underflow

1 1 0 Captures: Pos. TxA Neg. TxB tCor MCLK

TxA Pos. Edge Edge or Timer Edge

TxB Neg. Edge Underflow

30 1 1 Captures: Neg. TxA Pos. TxB tCor MCLK

TxA Neg. Edge Edge or Timer Edge

TxB Pos. Edge Underflow

1 1 1 Captures: Neg. TxA Neg. TxB tCor MCLK

TxA Neg. Edge Edge or Timer Edge

TxB Neg. Edge Underflow

5.12 Power Saving Features

Today, the proliferation of battery-operated applications has placed new demands on designers to drive

power consumption down. Battery operated systems are not the only type of applications demanding low

power. The power budget constraints are also imposed on those consumer/industrial applications where

well regulated and expensive power supply costs cannot be tolerated. Such applications rely on low cost

and low power supply voltage derived directly from the “mains” by using voltage rectifier and passive

components. Low power is demanded even in automotive applications, due to increased vehicle

electronics content. This is required to ease the burden from the car battery. Low power 8-bit

microcontrollers supply the smarts to control battery-operated, consumer/industrial, and automotive

applications.

The device offers system designers a variety of low-power consumption features that enable them to meet

the demanding requirements of today's increasing range of low-power applications. These features include

low voltage operation, low current drain, and power saving features such as HALT, IDLE, and Multi-Input

Wake-Up (MIWU).

This device supports three operating modes, each of which have two power save modes of operation. The

three operating modes are: High Speed, Dual Clock, and Low Speed. Within each operating mode, the

two power save modes are: HALT and IDLE. In the HALT mode of operation, all microcontroller activities

are stopped and power consumption is reduced to a very low level. In this device, the HALT mode is

enabled and disabled by a bit in the Option register. The IDLE mode is similar to the HALT mode, except

that certain sections of the device continue to operate, such as: the on-board oscillator, the IDLE Timer

(Timer T0), and the Clock Monitor. This allows real time to be maintained. During power save modes of

operation, all on board RAM, registers, I/O states and timers (with the exception of T0) are unaltered.

Two oscillators are used to support the three different operating modes. The high speed oscillator refers to

the oscillator connected to CKI and the low speed oscillator refers to the 32 kHz oscillator connected to

pins L0 & L1. When using L0 and L1 for the low speed oscillator, the user must ensure that the L0 and L1

pins are configured for hi-Z input, L1 is not using CKX on the USART, and Multi-Input Wake-up for these

pins is disabled.

A diagram of the three modes is shown in Figure 5-13.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

Figure 5-13. Diagram of Power Save Modes

5.12.1 POWER SAVE MODE CONTROL REGISTER

The ITMR control register allows for navigation between the three different modes of operation. It is also

used for the Idle Timer. The register bit assignments are shown below. This register is cleared to 40 (hex)

by Reset as shown below.

LSON HSON DCEN CCK RSVD ITSEL2 ITSEL1 ITSEL0

SEL

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LSON: This bit is used to turn-on the low-speed oscillator. When LSON = 0, the low speed oscillator

is off. When LSON = 1, the low speed oscillator is on. There is a startup time associated with

this oscillator. See the Control Registers section.

HSON: This bit is used to turn-on the high speed oscillator. When HSON = 0, the high speed

oscillator is off. When HSON = 1, the high speed oscillator is on. There is a startup time

associated with this oscillator. See the startup time table in the Control Registers section.

DCEN: This bit selects the clock source for the Idle Timer. If this bit = 0, then the high speed clock is

the clock source for the Idle Timer. If this bit = 1, then the low speed clock is the clock

source for the Idle Timer. The low speed oscillator must be started and stabilized before

setting this bit to a 1.

CCKSEL: This bit selects whether the high speed clock or low speed clock is gated to the

microcontroller core. When this bit = 0, the Core clock will be the high speed clock. When

this bit = 1, then the Core clock will be the low speed clock. Before switching this bit to either

state, the appropriate clock should be turned on and stabilized.

DCEN CCKSEL

0 0 High Speed Mode. Core and Idle Timer Clock = High Speed

1 0 Dual Clock Mode. Core clock = High Speed; Idle Timer = Low Speed

1 1 Low Speed Mode. Core and Idle Timer Clock = Low Speed

0 1 Invalid. If this is detected, the Low Speed Mode will be forced.

RSVD: This bit is reserved and must be 0.

Bits 2–0: These are bits used to control the Idle Timer. See TIMER T0 (IDLE TIMER) for the

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

description of these bits.

Table 5-15 lists the valid contents of the four most significant bits of the ITMR Register. Any other value is

illegal. States are presented in the only valid sequence. Any attempt to make a transition to any state

other than an adjacent valid state will be ignored by the logic and the ITMR Register will not be changed.

Table 5-15. Valid Contents of Dual Clock Control Bits

LSON HSON DCEN CCKSEL Mode

0 1 0 0 High Speed

1 1 0 0 High Speed/Dual Clock Transition

1 1 1 0 Dual Clock

1 1 1 1 Dual Clock/Low Speed Transition

1 0 1 1 Low Speed

5.12.2 OSCILLATOR STABILIZATION

Both the high speed oscillator and low speed oscillator have a startup delay associated with them. When

switching between the modes, the software must ensure that the appropriate oscillator is started up and

stabilized before switching to the new mode. See Table 5-2, Startup Times for approximate startup times

for both oscillators.

5.12.3 HIGH SPEED MODE OPERATION

This mode of operation allows high speed operation for both the main Core clock and also for the Idle

Timer. This is the default mode of the device and will always be entered upon any of the Reset conditions

described in the Reset section. It can also be entered from Dual Clock mode. It cannot be directly entered

from the Low Speed mode without passing through the Dual Clock mode first.

To enter from the Dual Clock mode, the following sequence must be followed using two separate

instructions:

1. Software clears DCEN to 0.

2. Software clears LSON to 0.

5.12.3.1 High Speed Halt Mode

The fully static architecture of this device allows the state of the microcontroller to be frozen. This is

accomplished by stopping the internal clock of the device during the HALT mode. The controller also stops

the CKI pin from oscillating during the HALT mode. The processor can be forced to exit the HALT mode

and resume normal operation at any time.

During normal operation, the actual power consumption depends heavily on the clock speed and operating

voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device

only draws a small leakage current, plus current for the BOR feature (if enabled), plus any current

necessary for driving the outputs. Since total power consumption is affected by the amount of current

required to drive the outputs, all I/Os should be configured to draw minimal current prior to entering the

HALT mode, if possible. In order to reduce power consumption even further, the power supply (VCC) can

be reduced to a very low level during the HALT mode, just high enough to ensure retention of data stored

in RAM. The allowed lower voltage level (VR) is specified in the Electrical Specs section.

5.12.3.1.1 Entering The High Speed Halt Mode

The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.

All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to

a very low level.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

5.12.3.1.2 Exiting The High Speed Halt Mode

There is a choice of methods for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-

Input Wake-up.

5.12.3.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the

HALT mode and starts execution from address 0000H. The initialization software should determine what

special action is needed, if any, upon start-up of the device from HALT. The initialization of all registers

following a RESET exit from HALT is described in the Reset section of this manual.

5.12.3.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a transition received on one of the available Wake-

up pins. The pins used and the types of transitions sensed on the Multi-input pins are software

programmable. For information on programming and using the Multi-Input Wake-up feature, refer to the

Multi-Input Wake-up section.

A start-up delay is required between the device wake-up and the execution of program instructions,

depending on the type of chip clock. The start-up delay is mandatory, and is implemented whether or not

the CLKDLY bit is set. This is because all crystal oscillators and resonators require some time to reach a

stable frequency and full operating amplitude.

The IDLE Timer (Timer T0) provides a fixed delay from the time the clock is enabled to the time the

program execution begins. Upon exit from the HALT mode, the IDLE Timer is enabled with a starting

value of 256 and is decremented with each instruction cycle. (The instruction clock runs at one-fifth the

frequency of the high speed oscillator.) An internal Schmitt trigger connected to the on-chip CKI inverter

ensures that the IDLE Timer is clocked only when the oscillator has a large enough amplitude. (The

Schmitt trigger is not part of the oscillator closed loop.) When the IDLE Timer underflows, the clock signals

are enabled on the chip, allowing program execution to proceed. Thus, the delay is equal to 256

instruction cycles.

NOTE

To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the

instruction in the application program used for entering the HALT mode should be followed

by two consecutive NOP (no-operation) instructions.

5.12.3.1.5 Options

This device has two options associated with the HALT mode. The first option enables the HALT mode

feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option

will cause the microcontroller to ignore any attempts to HALT the device under software control. Note that

this device can still be placed in the HALT mode by stopping the clock input to the microcontroller, if the

program memory is masked ROM. See the Option section for more details on this option bit.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

Figure 5-14. Wake-up from HALT

5.12.3.2 High Speed Idle Mode

In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with

the HALT mode. However, the high speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue

to operate, allowing real time to be maintained. The device remains idle for a selected amount of time up

to 65,536 instruction cycles, or 32.768 milliseconds with a 2 MHz instruction clock frequency, and then

automatically exits the IDLE mode and returns to normal program execution.

The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G

data register).

The IDLE Timer window is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles.

Selection of this value is made through the ITMR register.

The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.

The IDLE Timer runs continuously at the instruction clock rate, whether or not the device is in the IDLE

mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an

interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer

interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,

the instruction which was started as the part entered the IDLE mode is completed before the interrupt is

serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must

reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.

As with the HALT mode, this device can also be returned to normal operation with a reset, or with a Multi-

Input Wake-up input. Upon reset the ITMR register is cleared and the ITMR register selects the 4,096

instruction cycle tap of the Idle Timer.

The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it

cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put

into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the

selected number of instruction cycles.

In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be synchronized to

the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on

every underflow of the bit of the IDLE Timer which is associated with the selected window. Another

method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence.

The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register.

Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE

Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to

changing the value of the ITSEL bits of the ITMR Register and then clear the TOPND bit before

attempting to synchronize operation to the IDLE Timer.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

NOTE

As with the HALT mode, it is necessary to program two NOP's to allow clock

resynchronization upon return from the IDLE mode. The NOP's are placed either at the

beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode”

instruction.

For more information on the IDLE Timer and its associated interrupt, see the description in the Timers

section.

5.12.4 DUAL CLOCK MODE OPERATION

This mode of operation allows for high speed operation of the Core clock and low speed operation of the

Idle Timer. This mode can be entered from either the High Speed mode or the Low Speed mode.

To enter from the High Speed mode, the following sequence must be followed:

1. Software sets the LSON bit to 1.

2. Software waits until the low speed oscillator has stabilized. See Table 5-2.

3. Software sets the DCEN bit to 1.

To enter from the Low Speed mode, the following sequence must be followed:

1. Software sets the HSON bit to 1.

2. Software waits until the high speed oscillator has stabilized. See Table 5-2, Startup Times.

3. Software clears the CCKSEL bit to 0.

5.12.4.1 Dual Clock HALT Mode

The fully static architecture of this device allows the state of the microcontroller to be frozen. This is

accomplished by stopping the high speed clock of the device during the HALT mode. The processor can

be forced to exit the HALT mode and resume normal operation at any time. The low speed clock remains

on during HALT in the Dual Clock mode.

During normal operation, the actual power consumption depends heavily on the clock speed and operating

voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device

only draws a small leakage current, plus current for the BOR feature (if enabled), plus the 32 kHz

oscillator current, plus any current necessary for driving the outputs. Since total power consumption is

affected by the amount of current required to drive the outputs, all I/Os should be configured to draw

minimal current prior to entering the HALT mode, if possible.

5.12.4.1.1 Entering The Dual Clock Halt Mode

The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.

All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to

a very low level. In order to expedite exit from HALT, the low speed oscillator is left running when the

device is Halted in the Dual Clock mode. However, the Idle Timer will not be clocked.

5.12.4.1.2 Exiting The Dual Clock Halt Mode

When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods

for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset

method and Multi-Input Wake-up method can be used with any clock option.

5.12.4.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the

Dual Clock mode and puts it into the High Speed mode.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

5.12.4.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a transition received on one of the available Wake-

up pins. The pins used and the types of transitions sensed on the Multi-input pins are software

programmable. For information on programming and using the Multi-Input Wake-up feature, refer to Multi-

Input Wake-up.

A start-up delay is required between the device wake-up and the execution of program instructions. The

start-up delay is mandatory, and is implemented whether or not the CLKDLY bit is set. This is because all

crystal oscillators and resonators require some time to reach a stable frequency and full operating

amplitude.

If the start-up delay is used, the IDLE Timer (Timer T0) provides a fixed delay from the time the clock is

enabled to the time the program execution begins. Upon exit from the HALT mode, the IDLE Timer is

enabled with a starting value of 256 and is decremented with each instruction cycle using the high speed

clock. (The instruction clock runs at one-fifth the frequency of the high speed oscillatory.) An internal

Schmitt trigger connected to the on-chip CKI inverter ensures that the IDLE Timer is clocked only when

the high speed oscillator has a large enough amplitude. (The Schmitt trigger is not part of the oscillator

closed loop.) When the IDLE Timer underflows, the clock signals are enabled on the chip, allowing

program execution to proceed. Thus, the delay is equal to 256 instruction cycles. After exiting HALT, the

Idle Timer will return to being clocked by the low speed clock.

NOTE

To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the

instruction in the application program used for entering the HALT mode should be followed

by two consecutive NOP (no-operation) instructions.

5.12.4.1.5 Options

This device has two options associated with the HALT mode. The first option enables the HALT mode

feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option

will cause the microcontroller to ignore any attempts to HALT the device under software control. See

Option Register for more details on this option bit.

5.12.4.2 Dual Clock Idle Mode

In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with

the HALT mode. However, both oscillators, IDLE Timer (Timer T0), and Clock Monitor continue to operate,

allowing real time to be maintained. The Idle Timer is clocked by the low speed clock. The device remains

idle for a selected amount of time up to 1 second, and then automatically exits the IDLE mode and returns

to normal program execution using the high speed clock.

The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G

data register).

The IDLE Timer window is selectable from one of five values, 0.125 seconds, 0.25 seconds, 0.5 seconds,

1 second and 2 seconds. Selection of this value is made through the ITMR register.

The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.

The IDLE Timer runs continuously at the low speed clock rate, whether or not the device is in the IDLE

mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an

interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer

interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,

the instruction which was started as the part entered the IDLE mode is completed before the interrupt is

serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must

reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.

As with the HALT mode, this device can also be returned to normal operation with a Multi-Input Wake-up

input.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it

cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put

into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 30 µs and

the selected time period.

In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be ”synchronized

to the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on

every underflow of the bit of the IDLE Timer which is associated with the selected window. Another

method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence.

The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register.

Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE

Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to

changing the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting

to synchronize operation to the IDLE Timer.

NOTE

As with the HALT mode, it is necessary to program two NOP's to allow clock

resynchronization upon return from the IDLE mode. The NOP's are placed either at the

beginning of the IDLE Timer interrupt routine or immediately following the “enter IDLE mode”

instruction.

For more information on the IDLE Timer and its associated interrupt, see the description in the Timers

section.

5.12.5 LOW SPEED MODE OPERATION

This mode of operation allows for low speed operation of the core clock and low speed operation of the

Idle Timer. Because the low speed oscillator draws very little operating current, and also to expedite

restarting from HALT mode, the low speed oscillator is left on at all times in this mode, including HALT

mode. This is the lowest power mode of operation on the device. This mode can only be entered from the

Dual Clock mode.

To enter the Low Speed mode, the following sequence must be followed using two separate instructions:

1. Software sets the CCKSEL bit to 1.

2. Software clears the HSON bit to 0.

Since the low speed oscillator is already running, there is no clock startup delay.

5.12.5.1 Low Speed HALT Mode

The fully static architecture of this device allows the state of the microcontroller to be frozen. Because the

low speed oscillator draws very minimal operating current, it will be left running in the low speed halt

mode. However, the Idle Timer will not be running. This also allows for a faster exit from HALT. The

processor can be forced to exit the HALT mode and resume normal operation at any time.

During normal operation, the actual power consumption depends heavily on the clock speed and operating

voltage used in an application and is shown in the Electrical Specifications. In the HALT mode, the device

only draws a small leakage current, plus current for the BOR feature (if enabled), plus the 32 kHz

oscillator current, plus any current necessary for driving the outputs. Since total power consumption is

affected by the amount of current required to drive the outputs, all I/Os should be configured to draw

minimal current prior to entering the HALT mode, if possible.

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I –OCTOBER 2000–REVISED MARCH 2013

www.ti.com

5.12.5.1.1 Entering The Low Speed Halt Mode

The device enters the HALT mode under software control when the Port G data register bit 7 is set to 1.

All processor action stops in the middle of the next instruction cycle, and power consumption is reduced to

a very low level. In order to expedite exit from HALT, the low speed oscillator is left running when the

device is Halted in the Low Speed mode. However, the Idle Timer will not be clocked.

5.12.5.1.2 Exiting The Low Speed Halt Mode

When the HALT mode is entered by setting bit 7 of the Port G data register, there is a choice of methods

for exiting the HALT mode: a chip Reset using the RESET pin or a Multi-Input Wake-up. The Reset

method and Multi-Input Wake-up method can be used with any clock option, but the availability of the G7

input is dependent on the clock option.

5.12.5.1.3 HALT Exit Using Reset

A device Reset, which is invoked by a low-level signal on the RESET input pin, takes the device out of the

Low Speed mode and puts it into the High Speed mode.

5.12.5.1.4 HALT Exit Using Multi-Input Wake-up

The device can be brought out of the HALT mode by a transition received on one of the available Wake-

up pins. The pins used and the types of transitions sensed on the Multi-input pins are software

programmable. For information on programming and using the Multi-Input Wake-up feature, refer to the

Multi-Input Wake-up section.

As the low speed oscillator is left running, there is no start up delay when exiting the low speed halt mode,

regardless of the state of the CLKDLY bit.

NOTE

To ensure accurate operation upon start-up of the device using Multi-input Wake-up, the

instruction in the application program used for entering the HALT mode should be followed

by two consecutive NOP (no-operation) instructions.

5.12.5.1.5 Options

This device has two options associated with the HALT mode. The first option enables the HALT mode

feature, while the second option disables HALT mode operation. Selecting the disable HALT mode option

will cause the microcontroller to ignore any attempts to HALT the device under software control. See the

Option section for more details on this option bit.

5.12.5.2 Low Speed Idle Mode

In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with

the HALT mode. However, the low speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue to

operate, allowing real time to be maintained. The device remains idle for a selected amount of time up to 2

seconds, and then automatically exits the IDLE mode and returns to normal program execution using the

low speed clock.

The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G

data register).

The IDLE Timer window is selectable from one of five values, 0.125 seconds, 0.25 seconds, 0.5 seconds,

1 second, and 2 seconds. Selection of this value is made through the ITMR register.