1
®
FN3282.13
DG411, DG412, DG413
Monolithic Quad SPST, CMOS Analog
Switches
The DG411 series monolithic CMOS analog switches are
drop-in replace m ents for the popular DG211 and DG21 2
series devices. They include four independent single pole
throw (SPST) analog switches, and TTL and CMOS
compatible digital inputs.
These switches feature lower analo g ON-resistance (<35Ω)
and faster switch time (tON<175ns) compared to the DG211
or DG212. Charge injection has been reduced, simplifying
sample and hold applications.
The improvements in the DG411 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 40VP-P signals. Power supplies may be
single-ended from +5V to 44V, or split from ±5V to ±20V.
The four switches are bilateral, equal ly matched for AC or
bidirectional signals. The ON-resist ance variation w ith analog
signals is quite low over a ±15V analog in put range. The
switches in the DG411 and DG412 are identical, di ffering only
in the polarity of the selection l ogic. Two of the switches in the
DG413 (#2 and #3) use the logic of th e DG211 and DG411
(i.e., a logic “0” turns the switch ON) and the other two
switches use DG212 and DG412 positive logic. This permit s
independent control of turn-on and turn-of f times fo r SPDT
configurations, permitting “b rea k-before-make” or “make-
before-break” operation with a minimum of exte rnal logi c.
Features
• ON-Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 35Ω
• Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <35µW
• Fast Switching Action
-t
ON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175ns
-t
OFF (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ns
• Low Charge Injection
• Upgrade from DG211, DG212
• TTL, CMOS Compatible
• Single or Sp lit Supply Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Audio Switching
• Battery Operated Systems
• Data Acquisition
• Hi-Rel Systems
• Sample and Hold Circuits
• Communication Systems
• Automatic Test Equipment
Data Sheet June 20, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1993, 1994, 1997, 1999, 2002, 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN3282.13
June 20, 2007
Pinout DG41 1, DG412, DG413
(16 LD PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. #
DG411DJ DG411DJ -40 to +85 16 Ld PDIP E16.3
DG411DJZ (Note) DG411DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG411DY* DG411DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG411DYZ* (Note) DG411DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG411DVZ* (Note) DG411 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG412DJ DG412DJ -40 to +85 16 Ld PDIP E16.3
DG412DJZ (Note) DG412DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG412DY* DG412DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG412DYZ* (Note) DG412DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG412DVZ* (Note) DG412 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
DG413DJ DG413DJ -40 to +85 16 Ld PDIP E16.3
DG413DJZ (Note) DG413DJZ -40 to +85 16 Ld PDIP** (Pb-free) E16.3
DG413DY* DG413DY -40 to +85 16 Ld SOIC (150 mil) M16.15
DG413DYZ* (Note) DG413DYZ -40 to +85 16 Ld SOIC (150 mil) (Pb-free) M16.15
DG413DVZ* (Note) DG413 DVZ -40 to +85 16 Ld TSSOP (4.4mm) (Pb-free) M16.173
*Add “-T” suffix for tape and reel.
**Pb-free PDIPs can be used f or t hr ough ho le w ave so lder p rocessin g o nly. T he y ar e not inte nd ed fo r use in Reflow so lder proce s sing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified a t P b- free pe ak re flo w t em pera tur e s th at me et or e xcee d t he Pb -f re e re quire me nts of IP C/ JE DEC J STD- 02 0.
TRUTH TABLE
LOGIC
DG411 DG412 DG413
SWITCH SWITCH SWITCH
1, 4 SWITCH
2, 3
0OnOff Off On
1 Off On On Off
NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IN1
D1
S1
V-
GND
S4
IN4
D4
IN2
S2
V+
VL
S3
D3
IN3
D2
Pin Descriptions
PIN SYMBOL DESCRIPTION
1IN
1Logic Control for Switch 1.
2D
1Drain (Output) Terminal for Switch 1.
3S
1Source (Input) Terminal for Switch 1.
4 V- Negative Power Supply Terminal.
5 GND Ground Terminal (Logic Common).
6S
4Source (Input) Terminal for Switch 4.
7D
4Drain (Output) Terminal for Switch 4.
8IN
4Logic Control for Switch 4.
9IN
3Logic Control for Switch 3.
10 D3Drain (Output) Terminal for Switch 3.
11 S3Source (Input) Terminal for Switch 3.
12 VLLogic Reference Voltage.
13 V+ Positive Power Supply Terminal (Substrate).
14 S2Source (Input) Terminal for Switch 2.
15 D2Drain (Output) Terminal for Switch 2.
16 IN2Logic Control for Switch 2.
DG411, DG412, DG413
3FN3282.13
June 20, 2007
Functional Diagrams Four SPST Switches per Package Switches Shown for Logic “1” Input
Schematic Diagram (1 Channel)
S1
D1
S2
D2
S3
D3
S4
D4
DG411
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG412
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
IN1
DG413
IN2
IN3
IN4
IN2
IN3
IN4
IN1
S
V+
IN
X
GND
V-
V-
V
L
D
V+
DG411, DG412, DG413
4FN3282.13
June 20, 2007
Absolute Maximum Ratings Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to (V+) +0.3V
Digital Inputs, VS, VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns
Thermal Resistance (Typical, Note 2) θJA (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Maximum Junction Temperature (Plastic Packages). . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(SOIC and TSSOP - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 4) TYP
(Note 5) MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF, VS = ±10V (Figure 1) 25 - 110 175 ns
85 - - 220 ns
Turn-OFF Time, tOFF 25 - 100 145 ns
85 - - 160 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω, CL = 35pF (Figure 2) 25 - 25 - ns
Charge Injection, Q (Figure 3) CL = 10nF, VG = 0V, RG = 0Ω25 - 5 - pC
OFF Isolation (Figure 5) RL = 50Ω, CL = 5pF, f = 1MHz 25 - 68 - dB
Crosstalk (Channel-to-Channel),
(Figure 4) 25 - -85 - dB
Source OFF Capacitance, CS(OFF) f = 1MHz (Figure 6) 25 - 9 - pF
Drain OFF Capacitance, CD(OFF) 25 - 9 - pF
Channel ON Capacitance,
CD(ON) + CS(ON) 25 - 35 - pF
DIGITAL INPUT CHARACT ERISTICS
Input Current VIN Low, IIL VIN Under Test = 0.8V, All Others = 2.4V Full -0.5 0.005 0.5 μA
Input Current VIN High, IIH VIN Under Test = 2.4V, All Others = 0.8V Full -0.5 0.005 0.5 μA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG IS = 10mA Full -15 - 15 V
Drain-Source ON Resistance,
rDS(ON) IS = 10mA, VD = ±8.5V, V+ = 13.5V, V- = -13.5V 25 - 25 35 Ω
Full - - 45 Ω
±
±
DG411, DG412, DG413
5FN3282.13
June 20, 2007
Source OFF Leakage Current,
IS(OFF) V+ = 16.5V, V- = -16.5V, VD = ±15.5V, VS = 15.5V 25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Drain OFF Leakage Current,
ID(OFF) 25 -0.25 ±0.1 0.25 nA
Full -5 - +5 nA
Channel ON Leakage Current,
ID(ON) + IS(ON) V + = 16 .5V, V- = -16 .5V, VS = VD = ±15.5V 25 -0.4 ±0.1 0.4 nA
Full -10 - +10 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V 25 - 0.0 001 1 μA
85 - - 5 μA
Ne g ative S up p l y C urren t , I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified.
PA RAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 4) TYP
(Note 5) MAX
(Note 4) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON RL = 300Ω, CL = 35pF,
VS = 8V, (Figure 1) 25 - 175 250 ns
85 - - 315 ns
Turn-OFF Time, tOFF 25 - 95 125 ns
85 - - 140 ns
Break-Before-Make Time Delay DG413 Only, RL = 300Ω,
CL = 35pF, VS = 8V 25 - 25 - ns
Charge Injection, Q CL = 10nF, VG = 6.0V, RG = 0Ω25 - 25 - pC
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0 - 12 V
Drain-Source ON-Resistance,
rDS(ON) IS = -10mA, VD = 3V, 8V
V+ = 10.8V 25 - 40 80 Ω
Full - - 100 Ω
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PARAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 4) TYP
(Note 5) MAX
(Note 4) UNITS
±
DG411, DG412, DG413
6FN3282.13
June 20, 2007
POWER SUPPLY CHARACTERISTI CS
Positive Supply Current, I+ V+ = 13.2V, V- = 0V
VIN = 0V or 5V 25 - 0.0001 1 μA
85 - - 5 μA
Negative Supply Current, I- 25 -1 -0.0001 - μA
85 -5 - - μA
Logic Supply Current, IL25 - 0.0001 1 μA
85 - - 5 μA
Ground Current, IGND 25 -1 -0.0001 - μA
85 -5 - - μA
NOTES:
3. VIN = input voltage to perform proper function.
4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Test Circuits and Waveforms
VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing
edge of the output waveform.
NOTE: Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENTS POINTS
Repeat test for all IN and S.
For load conditions, see S pecifications. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUITS
FIGURE 2. BREAK-BEFORE-MAKE TIME
Electrical Specifications (Single Supply) Test Conditions: V+ = +12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),
Unless Otherwise Specified. (Continued)
PA RAMETER TEST CONDITIONS TEMP
(°C) MIN
(Note 4) TYP
(Note 5) MAX
(Note 4) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
3V
0V
VS
0V
tON
VO
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOVS
R
L
RLrDS ON()
+
------------------------------------
=
SWITCH
INPUT
LOGIC
INPUT
S1
IN1
V+
D1
RLCL
VO
GND V-
VL
+15V+5V
SWITCH
OUTPUT
-15V
tD
3V
0V
VS1
0V
tD
LOGIC
INPUT
SWITCH
OUTPUT
SWITCH
OUTPUT
90%
0V
VS2
(V01)
VO2
90%
S1
IN1, IN2
V+
D1
RL1 CL1
VO1
GND V-
VL
VS1 = 10V
300Ω
+15V+5V
35pF
S2D2
RL2 CL2
VO2
VS2 = 10V
300Ω35pF
-15V
LOGIC
INPUT CL includes fixture and
stray capacitance.
DG411, DG412, DG413
7FN3282.13
June 20, 2007
FIGURE 3A. TEST CIRCUIT
NOTE: INX dependent on switch configuration, input polarity
determined by sense of switch.
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. CHARGE INJECTION
FIGURE 4. CROSSTALK TEST CIRCUIT FIGURE 5. OFF ISOLATION TEST CIRCUIT
FIGURE 6. SOURCE/DRAIN CAPACITANCES TEST CIRC UIT
Test Circuits and Waveforms (Continued)
V+
D1
CL
VO
GND
V-
VIN = 3V
RG
VG
SWITCH ΔVO
INXOFF ON
INXOFF OFF
OFF
ON
Q = ΔVO x CL
OUTPUT
0V, 2.4V
ANALYZER
+15V
V+
C
VS
0dBm
SIGNAL
GENERATOR
RLGND
IN1
VD
IN2
50Ω
0V, 2.4V
NC
V-
-15V
C
VDANALYZER
RL
+15V
0dBm
SIGNAL
GENERATOR
V+
C
V-
-15V
C
0V, 2.4V
VS
VD
INX
GND
+15V
V+
C
GND
VS
VD
INX
V-
-15V
C
IMPEDANCE
ANALYZER
f = 1MHz
0V, 2.4V
DG411, DG412, DG413
8FN3282.13
June 20, 2007
Application Information
Single Supply Operation
The DG411, DG412, DG413 can be operated with unip olar
supplies from 5V to 44V. These devices are characterized
and tested for single supply operation at 12V to facilitate the
majority of applications. To function properly, 12V is tied to
Pins 13 and 0V is tied to Pin 4.
Pin 12 still requires 5V for TTL compatible switching.
Summing Amplifier
When driving a high impedance, high capacitance load such
as shown in Figure 7, where the inputs to the summing
amplifier have some noise filtering, it is necessary to have
shunt switches for rapid discharge of the filter capacitor , thus
preventing offsets from occurring at the output.
VIN1 R2
R1
VOUT
+
-
C1
VIN2 R4
R3
C2
DG413
R5
R6
FIGURE 7. SUMMING AMPLIFIER
DG411, DG412, DG413
9FN3282.13
June 20, 2007
Typical Performance Curves
FIGURE 8. ON RESISTANCE vs VD AND POWER SUPPLY
VOLTAGE FIGURE 9. SWITCHING TIME vs TEMPERATURE
FIGURE 10. LEAKAGE CURRENTS vs ANALOG VOLTAGE FIGURE 11. SUPPLY CURRENT vs INPUT SWITCHING
FREQUENCY
FIGURE 12. CHARGE INJECTION vs SOURCE VOLTAGE FIGURE 13. CHARGE INJECTION vs DRAIN VOLTAGE
TA = +25°C
50 A: ±5V
B: ±8V
C: ±10V
D: ±12V
E: ±15V
F: ±20V
45
40
35
30
25
20
15
10
5
0-20 -15 -10 -5 0 5 2010 15
A
B
CDEF
DRAIN VOLTAGE (V)
rDS(ON) (Ω)
V+ = 15V, V- = -15V
VL = 5V, VS = 10V
tON
tOFF
-55 -15 5 25 45 65 12585 105
TEMPERATURE (°C)
-35
0
240
210
180
150
120
90
60
30
tON, t OFF (ns)
V+ = 15V, V- = -15V
VL = 5V, TA = +25°C
-15 -5 0 5 10 15
VS, VD (V)
-10
-60
20
10
0
-10
-20
-30
-40
-50
IS, ID (pA)
IS(OFF)
ID(OFF)
30
40
ID(ON) + IS(ON)
ISUPPLY
100mA
1mA
100μA
10μA
1μA
100nA
10nA
10mA
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
IL
I+, I-
1SW 1SW
4SW
4SW
V+ = 15V, V- = -15V
VL = 5V
CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VS (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
80
100 V+ = 15V, V- = -15V
VL = 5V CL = 10nF
CL = 1nF
-15 -5 0 5 10 15
VD (V)
-10
-60
60
40
20
0
-20
-40
Q (pC)
100
140
120
80
V+ = 15V, V- = -15V
VL = 5V
DG411, DG412, DG413
10 FN3282.13
June 20, 2007
Die Characteristics
DIE DIMENSIONS:
2760mm x 1780mm x 485mm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2
Metallization Mask Layout DG411, DG412, DG413
S1(3)
V- (4)
GND (5)
S4(6)
IN2
IN1
D1
(11) S3
(12) VL
(13) V+ SUBSTRATE
(14) S2
(15) D2
(2) (1) (16)
D4IN4IN3D3
(10)(9)(8)(7)
DG411, DG412, DG413
11 FN3282.13
June 20, 2007
DG411, DG412, DG413
Thin Shrink Small Outline Plastic Packages (TSSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
0.05(0.002)
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.043 - 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.033 0.037 0.85 0.95 -
b 0.0075 0.012 0.19 0.30 9
c 0.0035 0.008 0.09 0.20 -
D 0.193 0.201 4.90 5.10 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.020 0.028 0.50 0.70 6
N16 167
a0o8o0o8o-
Rev. 1 2/02
12 FN3282.13
June 20, 2007
DG411, DG412, DG413
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
13
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN3282.13
June 20, 2007
DG411, DG412, DG413
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45°
C
H0.25(0.010) BM M
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167
α0° 8° 0° 8° -
Rev. 1 6/05
