1
2
3
4
8
7
6
5
CLKIN
OE
1Y0
GND
1Y3
1Y2
VDD
1Y1
TSSOP
PW PACKAGE
(TOP VIEW)
3
5
7
8
1Y0
1Y1
1Y2
1Y3
Logic
Control
2
1
OE
CLKIN
CDCV304
www.ti.com
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
200-MHz GENERAL-PURPOSE CLOCK BUFFER, PCI-X COMPLIANT
Check for Samples: CDCV304
1FEATURES PCI-X Compliant
General-Purpose and PCI-X 1:4 Clock Buffer 8-Pin TSSOP Package
Operating Frequency
0 MHz to 200 MHz General-Purpose
Low Output Skew: <100 ps
Distributes One Clock Input to One Bank of
Four Outputs
Output Enable Control that Drives Outputs
Low when OE is Low
Operates from Single 3.3-V Supply or 2.5-V
Supply
DESCRIPTION
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one
input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X
applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X
specifications.
The CDCV304 is characterized for operation from 40°C to 85°C for automotive and industrial applications.
FUNCTIONAL BLOCK DIAGRAM
Table 1. FUNCTION TABLE
INPUTS OUTPUTS
CLKIN OE 1Y[0:3]
L L L
H L L
L H L
H H H
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. ©20002011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCV304
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
1Y[0:3] 3, 5, 7, 8 O Buffered output clocks
CLKIN 1 I Input reference frequency
GND 4 Power Ground
OE 2 I Output enable control
VDD 6 Power Supply
THERMAL INFORMATION(1)
THERMAL AIR FLOW (CFM)
CDCV304PW 8-PIN TSSOP UNIT
0 150 250 500
RθJA High K 149 142 138 132
RθJA Low K 230 185 170 150
RθJB High K 102.0 °C/W
RθJC High K 43.7
ψJT High K 1.8
ψJB High K 100.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range, VDD 0.5 V to 4.3 V
Input voltage range, VI(2) (3) 0.5 V to VDD + 0.5 V
Output voltage range, VO(2) (3) 0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI<0 or VI>VDD)±50 mA
Output clamp current, IOK (VO<0 or VO>VDD)±50 mA
Continuous total output current, IO(VO= 0 to VDD)±50 mA
Package thermal impedance, θJA: PW package 230.5°C/W
Storage temperature range Tstg 65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
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Product Folder Link(s): CDCV304
CDCV304
www.ti.com
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage, VDD 2.3 3.6 V
Low-level input voltage, VIL 0.3 x VDD V
High-level input voltage, VIH 0.7 x VDD V
Input voltage, VI0 VDD V
VDD = 2.5 V 12
High-level output current, IOH mA
VDD = 3.3 V 24
VDD = 2.5 V 12
Low-level output current, IOL mA
VDD = 3.3 V 24
Operating free-air temperature, TA40 85 °C
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fclk Clock frequency 0 200 MHz
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input voltage VDD = 3 V, II=18 mA 1.2 V
VDD = 2.3 V, IOH =8 mA 1.8
VDD = 2.3 V, IOH =16 mA 1.5
VOH High-level output voltage VDD = min to max, IOH =1 mA VDD 0.2 V
VDD = 3 V, IOH =24 mA 2
VDD = 3 V, IOH =12 mA 2.4
VDD = 2.3 V, IOL = 8 mA 0.5
VDD = 2.3 V, IOL = 16 mA 0.7
VOL Low-level output voltage VDD = min to max, IOL = 1 mA 0.2 V
VDD = 3 V, IOL = 24 mA 0.8
VDD = 3 V, IOL = 12 mA 0.55
VDD = 3 V, VO= 1 V 50
IOH High-level output current mA
VDD = 3.3 V, VO= 1.65 V 55
VDD = 3 V, VO= 2 V 60
IOL Low-level output current mA
VDD = 3.3 V, VO= 1.65 V 70
IIInput current VI= VOor VDD ±5μA
f = 67 MHz, VDD = 2.7 V 28
IDD Dynamic current, see Figure 5 mA
f = 67 MHz, VDD = 3.6 V 37
CIInput capacitance VDD = 3.3 V, VI= 0 V or VDD 3 pF
COOutput capacitance VDD = 3.3 V, VI= 0 V or VDD 3.2 pF
(1) All typical values are with respect to nominal VDD and TA= 25°C.
©20002011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CDCV304
CDCV304
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
www.ti.com
SWITCHING CHARACTERISTICS
VDD = 2.5 V ±10%, CL= 10 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Low-to-high propagation delay 2 2.9 4.5
See Figure 1 and Figure 2 ns
tPHL High-to-low propagation delay 2 3 4.5
tsk(o) Output skew(2) See Figure 3 50 150 ps
trOutput rise slew rate 1.5 2.2 4 V/ns
tfOutput fall slew rate 1.5 2.2 4 V/ns
(1) All typical values are with respect to nominal VDD.
(2) The tsk(o) specification is only valid for equal loading of all outputs.
SWITCHING CHARACTERISTICS
VDD = 3.3 V ±10%, CL= 10 pF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tPLH Low-to-high propagation delay 1.8 2.4 3
See Figure 1 and Figure 2 ns
tPHL High-to-low propagation delay 1.8 2.5 3
tsk(o) Output skew(2) 50 100 ps
12 kHz to 5 MHz, fout = 30.72 MHz 63
tjitter Additive phase jitter from input to output 1Y0 fs rms
12 kHz to 20 MHz, fout = 125 MHz 56
tsk(p) Pulse skew VIH = VDD, VIL = 0 V 150 ps
tsk(pr) Process skew 0.2 0.3 ns
tsk(pp) Part-to-part skew 0.25 0.4 ns
66 MHz 6
thigh Clock high time, see Figure 4 ns
140 MHz 3
66 MHz 6
tlow Clock low time, see Figure 4 ns
140 MHz 3
trOutput rise slew rate(3) VO= 0.4 V to 2 V 1.5 2.7 4 V/ns
tfOutput fall slew rate(3) VO= 2 V to 0.4 V 1.5 2.7 4 V/ns
(1) All typical values are with respect to nominal VDD.
(2) The tsk(o) specification is only valid for equal loading of all outputs.
(3) This symbol is according to PCI-X terminology.
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Product Folder Link(s): CDCV304
140
Yn
VDD
10 pF
140
0.6 VDD
1Y0 − 1Y3
50% VDD
0.2 VDD
tf
VOL
VOH
tr
CLKIN 0 V
VDD
tPHL
50% VDD
tPLH
0.6 VDD
50% VDD
0.2 VDD
50% VDD
Any Y
Any Y
tsk(0)
50% VDD
thigh
VIH(Min)
Vtest
VIL(Max)
tlow
tcyc
0.4 VDD
Peak to Peak (Minimum)
0.2 VDD
0.6 VDD
PARAMETER VALUE UNIT
VIH(Min)
VIL(Max)
Vtest
0.5 VDD
0.35 VDD
0.4 VDD
V
V
V
CDCV304
www.ti.com
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Load Circuit
Figure 2. Voltage Waveforms Propagation Delay (tpd) Measurements
Figure 3. Output Skew
A. All parameters in Figure 4 are according to PCI-X 1.0 specifications.
Figure 4. Clock Waveform
©20002011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CDCV304
f − Frequency − MHz
20
30
40
50
60
0 20 40 60 80 100 120 140 160
TA = 85°C
Output Load: as in Figure 1
ICC − Supply Current − mA
VDD = 2.7V
VDD = 3.6V
IOH − High-Level Output Current − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0
VDD = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
CDCV304
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
www.ti.com
SUPPLY CURRENT
vs
FREQUENCY
Figure 5.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
Figure 6.
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Product Folder Link(s): CDCV304
IOL − Low-Level Output Current − mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−20 0 20 40 60 80 100 120
VDD = 3.3 V
TA = 25°C
OL
V− Low-Level Output Voltage − V
CDCV304
www.ti.com
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
Figure 7.
©20002011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CDCV304
CDCV304
SCAS643H SEPTEMBER 2000REVISED FEBRUARY 2011
www.ti.com
REVISION HISTORY
Changes from Revision F (April 2009) to Revision G Page
Added ψJT and ψJB specs to the Thermal Information Table and changed RθJB and RθJC specs from 65 and
69 °C/W respectively. ........................................................................................................................................................... 2
Changes from Revision G (January 2011) to Revision H Page
Added missing characteristics graphs. ................................................................................................................................. 6
8Submit Documentation Feedback ©20002011, Texas Instruments Incorporated
Product Folder Link(s): CDCV304
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CDCV304PWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CDCV304PWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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