The ES DA f amily has been designed t o c lamp fast
spikes like ESD. Generally the PCB designers
need to calculate easily the clamping voltage VCL.
This is why we give the dynamic resistance in
addition to the classical parameters. The voltage
across the protection cell can be calculated with
the following formula:
VCL = VBR + Rd IPP
Where Ipp is the peak current through the ESDA cell.
DYNAM IC RE SISTANCE M EASUREMENT
The short duration of the E SD has led us t o pr efer
a more adapted test wave, as below defined, to the
classical 8/20µs and 10/1000µs surges.
2.5µs duration measurement wave.
As the value of the dynamic resistance remains
stable for a surge duration lower than 20µs, the
2.5µs rectangular surge is well adapted. In addition
both rise and fall time s are optimized to avoid any
parasitic phenomenon during the m easur ement of
Rd.
CALCULATION OF THE CLAMPING VOLTAGE
USE OF T HE DY NAM IC RE SIS TA NCE
2µs
tp = 2.5µs
t
I
Ipp
ESDA25B1
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