5-533
FAST AND LS TTL DATA
OCTAL D FLIP-FLOP WITH ENABLE;
HEX D FLIP-FLOP WITH ENABLE;
4-BIT D FLIP-FLOP WITH ENABLE
The SN54/74LS377 is an 8-bit register built using advanced Low Power
Schottky technology. This register consists of eight D-type flip-flops with a
buffered common clock and a buffered common clock enable.
The SN54/74LS378 is a 6-Bit Register with a buffered common enable.
This device is similar to the SN54/74LS174, but with common Enable rather
than common Master Reset.
The SN54/74LS379 is a 4-Bit Register with buffered common Enable. This
device is similar to the SN54 /74LS175 but features the common Enable
rather then common Master Reset.
•8-Bit High Speed Parallel Registers
•Positive Edge-Triggered D-Type Flip Flops
•Fully Buffered Common Clock and Enable Inputs
•True and Complement Outputs
•Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a)
HIGH LOW
E Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.
D0–D3Data Inputs 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
Q0–Q3True Outputs (Note b) 10 U.L. 5 (2.5) U.L.
Q0–Q3Complemented Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
SN54/74LS377
SN54/74LS378
SN54/74LS379
OCTAL D FLIP-FLOP WITH
ENABLE; HEX D FLIP-FLOP
WITH ENABLE; 4-BIT D FLIP-FLOP
WITH ENABLE
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
D SUFFIX
SOIC
CASE 751B-03
20
1
J SUFFIX
CERAMIC
CASE 732-03
20 1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
5-534
FAST AND LS TTL DATA
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
CONNECTION DIAGRAM DIPS (TOP VIEW)
14 13 12 11 10 9
1234567
16 15
8
VCC
E
Q5D5D4Q4Q3
D3CP
Q0D0D1Q1D2Q2GND
14 13 12 11 10 9
1234567
16 15
8
VCC
E
Q3Q3D3D2Q2
Q2CP
Q0Q0D0D1Q1Q1GND
18 17 16 15 14 13
1 2 3 4 5 6 7
20 19
8
VCC
E
Q7D7D6Q6D5
Q5D4
Q0D0D1Q1Q2D2D3
9 10
Q3GND
12 11
Q4CP
SN54/74LS377
SN54/74LS378
SN54/74LS379
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
5-535
FAST AND LS TTL DATA
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
LOGIC DIAGRAMS
SN54/74LS377
SN54/74LS378
SN54/74LS379
5-536
FAST AND LS TTL DATA
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
VIL
Input LOW Voltage
74 0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V
V
CC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74 0.35 0.5 V IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20 µA VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current LS377
LS378
LS379
28
22
15 mA VCC = MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
fMAX Maximum Clock Frequency 30 40 MHz
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL Propagation Delay,
Clock to Output 17
18 27
27 ns
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min Typ Max
Unit
Test Conditions
tWAny Pulse Width 20 ns
VCC = 5.0 V
tsData Setup Time 20 ns
VCC = 5.0 V
ts
Enable Setup
Inactive — State 10 ns
VCC = 5.0 V
ts
Enable Setup
Time
Active — State 25 ns
CC = 5.0 V
thAny Hold Time 5.0 ns
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
5-537
FAST AND LS TTL DATA
SN54/74LS377 • SN54/74LS378 • SN54/74LS379
TRUTH TABLE
E CP DnQnQn
H X No
Change No
Change
L H H L
L L L H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
AC WAVEFORMS
SN54/74LS377 SN54/74LS378
SN54/74LS379
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
Figure 2. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data
or Enable to Clock
Figure 3. Clock to Output Delays Clock Pulse
Width, Frequency, Setup and Hold Times Data,
Enable to Clock
5-538
FAST AND LS TTL DATA
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5-539
FAST AND LS TTL DATA
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