Figure 1. Application with VIN to ground short protection, using optional P-MOSFET sensing

The A8502 is a multi-output white LED driver for small-size

pin, shorted boost switch or inductor, shorted FSET or ISET

resistor, and IC overtemperature. A dual level cycle-by-cycle

current switch against high current overloads.

switching frequencies to be synchronized in the range of

580 kHz to 2.3 MHz. The high switching frequency allows

the A8502 to operate above the AM radio band.

A8502-DS, Rev. 3

Features and Benefits

frequency up to 2.3 MHz, allowing operation above the

AM band

• Excellent input voltage transient response

• Single resistor primary OVP minimizes VOUT leakage

• Internal secondary OVP for redundant protection

• LED current of 120 mA per channel

• Drives up to 12 series LEDs in 2 parallel strings

• 0.7% to 0.8% LED to LED matching accuracy

• PWM and analog dimming inputs

• 5000:1 PWM dimming at 200 Hz

Package: 16-pin TSSOP with exposed

thermal pad (suffix LP) Applications:

LCD backlighting or LED lighting for:

Absolute Maximum Ratings*

t < 50 ns –1.0 V

A

¯¯¯

U ¯¯

ISET, FSET, APWM, COMP Pins –0.3 to 5.5 V

All Other Pins –0.3 to 7 V

Operating Ambient Temperature TARange K –40 to 125 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

*Stresses beyond those listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical

an exposed pad for enhanced thermal dissipation. It is lead (Pb) free,

with 100% matte tin lead frame plating.

Description (continued)

Characteristic Performance 8

Functional Description 11

characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted

Input Voltage Specifications

UVLO Start Threshold VUVLOrise VIN rising – 4.35 V

UVLO Stop Threshold VUVLOfall VIN falling – 3.90 V

Input Currents

Input Sleep Supply Current IQSLEEP VIN = 16 V, VPWMEN = VFSETSYNC = 0 V 2.0 10.0 A

Error Amplifier

Transconductance gmICOMP = ±10 A 750 990 1220 A/V

Source Current IEA(SRC) VCOMP = 1.5 V –350 A

Sink Current IEA(SINK) VCOMP = 1.5 V 350 A

COMP Pin Pull-down Resistance RCOMP ¯

Overvoltage Protection

Switch Leakage Current ISWLKG VSW = 16 V, PWM/EN = VIL 0.1 1 A

Switch Current Limit ISW(LIM) 3.0 3.5 4.2 A

Secondary Switch Current Limit2ISW(LIM2)

Soft Start Boost Current Limit ISWSS(LIM) Initial soft start current for boost switch 700 mA

Minimum Switch Off-Time tSWOFFTIME 30 47 68 ns

Continued on the next page…

Oscillator Frequency

Synchronization

Synchronized PWM Frequency fSWSYNC 580 2300 kHz

Synchronization Input

Minimum Off-Time tPWSYNCOFF 150 ns

Synchronization Input

Minimum On-Time tPWSYNCON 150 ns

SYNC Input Logic Voltage

LED Current Sinks

Soft Start LEDx Current ILEDSS

Maximum PWM Dimming

Until Off-Time2tPWML

and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted

Continued on the next page…

and characterization over the full operating temperature range with TA = TJ = –40°C to 125°C; unless otherwise noted

GATE Pin

GATE Pin Sink Current IGSINK VGS = VIN 104 A

Gate Fault Shutdown Greater than

2X Current2tGFAULT2 3s

Figure 12. Percentage Error of the LED current versus PWM duty cycle

(at 200 Hz PWM frequency).

Figure 16. Diagram showing the transition of LED current from 120 mA

to 90 mA, when a 25% duty cycle signal is applied to the APWM pin;

PWM = 1; shows ILED (ch1, 50 mA/div.), APWM (ch2, 5 V/div.), and

PWM/EN (ch3, 5 V/div.), time = 500 s/div.

120 mA per LED would deliver 90 mA of current per LED when

an APWM signal is applied with a duty cycle of 25% (figures

Figure 18. Transition of output current level when a 50% duty cycle signal

is applied to the APWM pin, in conjunction with a 50% duty cycle PWM

dimming being applied to the PWM pin; shows IOUT (ch1, 100 mA/div.),

APWM (ch2, 5 V/div.), and PWM/EN (ch3, 5 V/div.), time = 1 ms/div.

IOUT

pin (see figure 19). The limit of this type of dimming depends on

the range of the ISET pin. In the case of the A8502 the limit is

40 to 125 A.

• For a single resistor (panel A of figure 18), the ISET current is

controlled by the following formula:

ISET =

RISET

• For a dual-resistor configuration (panel B of figure 19), the ISET

current is controlled by the following formula:

necting resistor ROVP between the OVP pin and VOUT

teristics table, and

There are several possibilities for why an OVP condition would

be encountered during operation, the two most common being: a

The boost switch is protected with cycle-by-cycle current limiting

set at a minimum of 3.0 A. There is also a secondary current limit

that is sensed on the boost switch. When detected this current

limit immediately shuts down the A8502. The level of this cur-

The primary function of the input disconnect switch is to protect

the system and the device from catastrophic input currents during

a fault condition. The external circuit implementing the discon-

nect is shown in figure 28. If the input disconnect switch is not

used, the VSENSE pin must be tied to VIN and the GATE pin

must be left open.

similar, not at -10 V; derate it for higher temperature

The input disconnect switch has two modes of operation:

• 1X mode When the input current is between one and two times

the preset current limit value, the disconnect switch enters a con-

stant-current mode for a maximum duration of 10,000 cycles or

5 ms at 2 MHz. During this time, the Fault flag is set immediately

and the disconnect switch goes into a linear mode of operation,

in which the input current will be limited to a value approximate

to the 1X current trip point level (figure 29). If the fault corrects

itself before the expiration of the timer, the Fault flag will be

stop sinking current. The A8502 can be powered-down into low

power mode. To do so, disable the IC by keeping the PWM/EN

pin low for a period of 32,750 clock cycles. To keep the discon-

Figure 28. Typical circuit showing the implementation of the input

disconnect feature.

GATE

(3) IIN limited to 3 A

1X trip point

A8502 shuts down at

2X trip point

a 22 nF capacitor for CC and a 20  resistor for RC.

• 2X current limit If the input current level goes above 2X of the

preset current limit threshold, the A8502 will shut down in less

than 3 s regardless of user input (figure 30). This is a latched

when RADJ is 0 . This voltage can be trimmed by the RADJ

which coincides with the cycle-by-cycle current limit minimum

For example, given 3 A of input current, and the calculated maxi-

mum value of the sense resistor, RSC = 0.033 .

The RSC chosen is 0.03 , a standard.

RADJ = (VSENSETRIP – VADJ ) / IADJ (6)

The trip point voltage is calculated as:

to avoid shutting down because of momentary glitches in the

input power supply. When VIN falls below 4.35 V, the IC will

shut down (see figure 31).

VDD

The VDD pin provides regulated bias supply for internal circuits.

Connect the capacitor CVDD with a value of 0.1 F or greater to

this pin. The internal LDO can deliver no more than 2 mA of cur-

rent with a typical VDD of about 3.5 V, enabling this pin to serve

as the pull-up voltage for the ¯

¯

¯

VDD

If the PWM/EN pin is pulled low for more than tPWML (32,750

clock cycles), the device enters shutdown mode and clears all

internal fault registers. As an example, at a 2 MHz clock fre-

quency, it will take approximately 16.3 ms to shut down the IC

into the low power mode (figure 32). When the A8502 is shut

down, the IC will disable all current sources and wait until the

Overtemperature

Protection Auto-restart Always No Fault occurs when the die temperature exceeds the

overtemperature threshold, 165°C. Off Off Off

, 3.90 V

maximum. This fault resets all latched faults. Off Off Off

SEPIC circuit should be:

> 15.9 (V) + 16 (V) = 31.9 V

because the maximum output voltage in this case is VOUT(OVP).

During PWM off-time the boost converter is not switching. This

results in a slow bleeding off of the output voltage, due to leakage

currents. IR can be a large contributor, especially at high tempera-

tures. On the diode that was selected in this design, the current

varies between 1 and 100 A. It is often advantageous to pick a

diode with a much higher breakdown voltage, just to reduce the

reverse current. Therefore for this example, pick a diode rated for

Step 7 Choosing the output capacitors. The output capacitors

must be chosen such that they can provide filtering for both the

is 200 Hz and the minimum duty cycle is 1%. Typically, the volt-

age variation on the output, VCOUT , during PWM dimming must

be less than 250 mV, so that no audible hum can be heard. The

capacitance can be calculated as follows:

COUT =

1 – D(min)

ILK

ICOUTrms =

1 – D(max)

fSW

0.191 (A)

CINrms =

tance of CSW is related to the maximum voltage ripple allowed

across it:

Copyright ©2011-2012, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;