CD4015BMS S E M I C O N D U C T O R CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output November 1994 Features Pinout * High-Voltage Type (20V Rating) CD4015BMS TOP VIEW * Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V 16 VDD CLOCK B 1 * Fully Static Operation Q4B 2 15 DATA B * 8 Master-Slave Flip-Flops Plus Input and Output Buffering Q3A 3 14 RESET B * 100% Tested For Quiescent Current at 20V Q2A 4 13 Q1B * 5V, 10V and 15V Parametric Ratings * Standardized Symmetrical Output Characteristics * Maximum Input Current of 1A at 18V Over Full Package-Temperature Range; 100nA at 18V and 25oC Q1A 5 12 Q2B RESET A 6 11 Q3B DATA A 7 10 Q4A 9 CLOCK A VSS 8 * Noise Margin (Full Package-Temperature Range) = - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" Functional Diagram VDD 16 DATA A Applications CLOCK A * Serial-Input/Parallel-Output Data Queueing RESET A * Serial to Parallel Data Conversion 7 5 9 4 6 4 STAGE 3 10 * General-Purpose Register DATA B Description CLOCK B CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. "Q" outputs are available from each of the four stages on both registers. All register stages are D type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. Register expansion to 8 stages using one CD4015BMS package, or to more than 8 stages using additional CD4015BMS's is possible. 15 13 1 12 14 RESET B Q1A Q2A Q3A Q4A Q1B Q2B 4 STAGE 11 Q3B 2 Q4B 8 VSS The CD4015BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4X Frit Seal DIP H1F Ceramic Flatpack H6W CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures. Copyright (c) Harris Corporation 1992 7-89 File Number 3295 Specifications CD4015BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 GROUP A SUBGROUPS LIMITS TEMPERATURE MIN +25 C - 10 A +125oC - 1000 A 3 -55oC - 10 A o 1 +25 C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA - 100 nA - 50 mV - V 3 Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V UNITS 2 -55oC VDD = 18V MAX 1 o 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA Output Current (Source) Output Current (Source) IOH5A IOH5B VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC N Threshold Voltage P Threshold Voltage Functional VNTH VPTH F VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs 7-90 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4015BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock To Q Propagation Delay Reset To Q Transition Time Maximum Clock Input Frequency SYMBOL TPHL1 TPLH1 TPHL2 CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 320 ns - 432 ns - 400 ns - 540 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 3 - MHz 3/1.35 - MHz 10, 11 +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 A +125oC - 150 A VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 -55 C, +25 C - 10 A +125oC - 300 A -55oC, +25oC - 10 A o o - 600 A Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA oC +125 Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, - 3 V -55oC 7-91 Specifications CD4015BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Input Voltage High VIH CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, +7 - V - 160 ns -55oC +25oC Propagation Delay Clock To Q TPHL1 TPLH1 VDD = 10V VDD = 15V 1, 2, 3 +25 C - 120 ns Propagation Delay Reset To Q TPHL2 VDD = 10V 1, 2, 3 +25oC - 200 ns 1, 2, 3 +25 oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns o 6 - MHz o VDD = 15V Transition Time TTHL TTLH Maximum Clock Input Frequency FCL Minimum Data Setup Time TS Minimum Reset Pulse Width Input Capacitance VDD = 10V TRCL TFCL TWCL CIN +25 C VDD = 15V 1, 2, 3 +25 C 8.5 - MHz VDD = 5V 1, 2, 3 +25oC - 70 ns 1, 2, 3 +25oC - 40 ns o VDD = 15V 1, 2, 3 +25 C - 30 ns VDD = 5V 1, 2, 3 +25oC - 15 s VDD = 10V 1, 2, 3 +25oC - 15 s VDD = 15V 1, 2, 3 +25oC - 15 s VDD = 5V 1, 2, 3 +25oC - 180 ns 1, 2, 3 +25oC - 80 ns VDD = 10V TWR o 1, 2, 3 VDD = 10V Clock Rise and Fall Time Minimum Clock Pulse Width 1, 2, 3 o VDD = 15V 1, 2, 3 +25 C - 50 ns VDD = 5V 2, 3 +25oC - 200 ns VDD = 10V 2, 3 +25oC - 80 ns VDD = 15V 2, 3 +25oC - 60 ns 1, 2 +25oC - 7.5 pF Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta VNTH P Threshold Voltage VPTH P Threshold Voltage Delta VPTH Functional F CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 A 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS= -10A 1, 4 +25oC - 1 V VSS = 0V, IDD = 10A 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - 1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record 7-92 Specifications CD4015BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD 1.0A Output Current (Sink) IOL5 20% x Pre-Test Reading IOH5A 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 2 - 5, 10 - 13 1, 6 - 9, 14, 15 16 Static Burn-In 2 Note 1 2 - 5, 10 - 13 8 1, 6, 7, 9, 14 - 16 Dynamic BurnIn Note 1 - 6, 8, 14 16 2 - 5, 10 - 13 8 1, 6, 7, 9, 14 - 16 Irradiation Note 2 9V -0.5V 50kHz 25kHz 2 - 5, 10 - 13 1, 9 7, 15 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V 7-93 Specifications CD4015BMS Logic Diagram Q1 13 (5) Q2 12 (4) Q3 11 (3) Q4 2 (10) DATA * D 15 (7) Q D Q CL Q D Q CL Q D Q Q CL CLOCK * CL 1 (9) R R R Q R CL RESET * 14 (6) CL CL p p n n Q CL CL D Q VDD CL Q D R CL Q CL CL CL VSS p p n n *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK R CL CL FIGURE 1. CD4015BMS LOGIC DIAGRAM TRUTH TABLE CL X D R Q1 Qn 0 0 0 Qn-1 1 0 1 Qn-1 X 0 Q1 Qn X 1 0 0 X = Don't care Case 7-94 (No Change) CD4015BMS AMBIENT TEMPERATURE (TA) = +25oC 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 12.5 15 10 10V 7.5 5 2.5 5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 -5 -10V -15V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) TRANSITION TIME (tTHL, tTLH) (ns) 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 0 0 15V 20 -10 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 150 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 250 AMBIENT TEMPERATURE (TA) = +25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 10V 100 15V 50 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 20 40 60 80 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE 7-95 100 CD4015BMS Typical Performance Characteristics (Continued) 105 8 POWER DISSIPATION (PD) (W) 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 104 8 6 4 10V 2 10V 103 8 6 4 5V CL = 50pF CL = 15pF 2 102 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC tr, tf = 20ns RL = 200k 2 10 2 1 4 6 8 2 4 68 2 4 6 8 2 4 68 2 4 6 8 10 102 103 104 CLOCK INPUT FREQUENCY (fCL) (kHz) 105 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY Chip Dimensions and Pad Layout 80 1 3 2 16 15 14 4 METALLIZATION: Thickness: 11kA - 14kA, AL. PASSIVATION: 10.4kA - 15.6kA, Silane BOND PADS: 0.004 inches X 0.004 inches MIN 5 DIE THICKNESS: 0.0198 inches - 0.0218 inches 98 DIE SIZE: X = 80 (77 - 85) = (1.956 - 2.159) Y = 98 (95 - 103) = (2.413 - 2.616) 13 12 6 7 8 9 10 11 Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) 7-96