PIC12CE519-04I/SM - Microchip Technology

 1999 Microchip Technology Inc. DS40139E-page 1

Devices included in this Data Sheet:

• PIC12C508 • PIC12C508A • PIC12CE518

• PIC12C509 • PIC12C509A • PIC12CE519

• PIC12CR509A

Note: Throughout this data sheet PIC12C5XX

refers to the PIC12C508, PIC12C509,

PIC12C 508A, PI C1 2C 5 09A ,

PIC12CR509A, PIC12CE518 and

PIC12CE519. PIC12CE5XX refers to

PIC12CE518 and PIC12CE519.

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (1 µs) except for

program branches which are two-cycle

• Operating speed: DC - 4 MHz clock input

DC - 1 µs instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Two-level deep hardware stack

• Direct, indirect an d rel ative addressing modes for

data and instructions

• Internal 4 MHz RC oscillator with programmable

calibration

• In-circuit serial programming

Device

Memory

EPROM

Program ROM

Program RAM

Data EEPROM

Data

PIC12C508 512 x 12 25

PIC12C508A 512 x 12 25

PIC12C509 1024 x 12 41

PIC12C509A 1024 x 12 41

PIC12CE518 512 x 12 25 16

PIC12CE519 1024 x 12 41 16

PIC12CR509A 1024 x 12 41

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit

programmable prescaler

• Power-On Reset (POR)

•Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• 1,000,000 erase/write cycle EEPROM data

memory

• EEPROM data retention > 40 years

• Power saving SLEEP mode

• Wake-up from SLEEP on pin change

• Internal weak pull-ups on I/O pins

• Internal pull-up on MCLR pin

• Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low power, high speed CMOS EPROM/ROM

technology

• Fully static design

• Wide operating voltage range

• Wide temperature range:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 KHz

- < 1 µA typical standby current

PIC12C5XX

8-Pin, 8-Bit CMOS Microcon trollers

PIC12C5XX

DS40139E-page 2  1999 Microchip Technology Inc.

Pin Diagram - PIC12C508/509

Pin Diagram - PIC12C508A/509A,

PIC12CE518/519

Pin Diagram - PIC12CR509A

PDIP, 208 mil SOIC, Windowed Ceramic Side Brazed

VSS

GP0

GP1

GP2/T0CKI

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

VDD

PIC12C508

PIC12C509

PDIP, 150 & 208 mil SOIC, Windowed CERDIP

PIC12CE518

VSS

GP0

GP1

GP2/T0CKI

PIC12CE519

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

VDD

PIC12C508A

PIC12C509A

PDIP, 150 & 208 mil SOIC

VSS

GP0

GP1

GP2/T0CKI

PIC12CR509A

GP5/OSC1/CLKIN

GP4/OSC2

GP3/MCLR/VPP

VDD

Device Differences

Note 1: If you change from the PIC12C50X to the PIC12C50XA or to the PIC12CR50XA, pl ease verify

oscillator characteristics in your application.

Note 2: See Section 7.2.5 for OSCCAL implementation differences.

Device Voltage

Range Oscillator Oscillator

Calibration2

(Bits)

Process

Technology

(Microns)

PIC12C508A 3.0-5.5 See Note 1 6 0.7

PIC12LC508A 2.5-5.5 See Note 1 6 0.7

PIC12C508 2.5-5.5 See Note 1 4 0.9

PIC12C509A 3.0-5.5 See Note 1 6 0.7

PIC12LC509A 2.5-5.5 See Note 1 6 0.7

PIC12C509 2.5-5.5 See Note 1 4 0.9

PIC12CR509A 2.5-5.5 See Note 1 6 0.7

PIC12CE518 3.0-5.5 - 6 0.7

PIC12LCE518 2.5-5.5 - 6 0.7

PIC12CE519 3.0-5.5 - 6 0.7

PIC12LCE519 2.5-5.5 - 6 0.7

 1999 Microchip Technology Inc. DS40139E-page 3
PIC12C5XX
TABLE OF CONTENTS
1.0 General Descr iption...............................................................................................................................................4
2.0 PIC12C5XX Device Varieties................................................................................................................................7
3.0 Architectural Overview........................................................................................................................................... 9
4.0 Memory Organization . ............. .............. ............. .............. ............. .............. ............. ...........................................13
5.0 I/O Port................................................................................................................................................................21
6.0 Timer0 Module and TMR0 Register ....................................................................................................................25
7.0 EEPROM Peripheral Operation........................................................................................................................... 29
8.0 Special Features of the CPU...............................................................................................................................35
9.0 Instruction Set Summary.....................................................................................................................................47
10.0 Development Support.............. .............. ............. .............. ............. .............. ............. ...........................................59
11.0 Electrical Characteristics - PIC12C508/PIC12C509............................................................................................65
12.0 DC and AC Characteristics - PIC12C508/PIC12C509........................................................................................75
13.0 Electrical Characteristics  PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CR509A/
PIC12CE518/PIC12CE519/
PIC12LCE518/PIC12LCE519/PIC12LCR509A...................................................................................................79
14.0 DC and AC Characteristics
PIC12C508A/PIC12C509A/PIC12LC508A/PIC12LC509A/PIC12CE518/PIC12CE519/PIC12CR509A/
PIC12LCE518/PIC12LCE519/ PIC12LCR509A..................................................................................................93
15.0 Packaging Information.........................................................................................................................................99
Index ........................................................................................................................................................................... 105
PIC12C5XX Product Identification System ................................................................................................................ 109
Sales and Support: ..................................................................................................................................................... 109
To Our Valued Customers
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PIC12C5XX

DS40139E-page 4  1999 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

The PIC12C5XX from Microchip Technolog y is a fam-

ily of low-cost, high performance, 8-bit, fully static,

EEPROM/EPROM/ROM-based CMOS microcontrol-

lers. It employs a RISC archi tecture with only 33 sin-

gle word/single cycle instructions. All instructions are

single cycle (1 µs) except for program branches

which take two cycles. The PIC12C5XX delivers per-

formance an order of magnitude higher than its com-

petitors in the same price category. The 12-bit wide

instructions are highly symmetrical resulting in 2:1

code compression over other 8-bit microcontrollers i n

its class. The easy to use and easy to remember

instruction set reduces development time signifi-

cantly.

The PIC12C5XX products are equipped with special

features that reduce system cost and power require-

ments. The Power-On Reset (POR) and Device Reset

Timer (DRT) eliminate the need for external reset cir-

cuitry. There are four oscillator configurations to choose

from, including INTRC internal oscillator mode and the

power-saving LP (Low Power) oscillator mode. Power

saving SLEEP mode, Watchdog Timer and code

protection features also improve system cost, power

and reliability.

The PIC12C5XX are available in the cost-effective

One-Time-Programmable (OTP) versions which are

suitable for production in any volume. The customer

can take full advantage of Microchip’s pr ice leadersh ip

in O TP microcontrollers while benefiting from the OTP’ s

flexibility.

The PIC12C5XX produc ts are suppor ted by a full-fea-

tured macro assembler, a software simulator, an in-cir-

cuit emulator, a ‘C’ co mpiler, fuzzy logic s uppor t tools,

a low-cost development programmer, and a full fea-

tured programmer . Al l the tools are supported on IBM

PC and compat ible machines.

1.1 Applications

The PIC12C5XX series fits perfectly in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The EPROM technology makes customizing applica-

tion programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient, while the EEPROM data memory technology

allows for the changing of calibration factors and secu-

rity codes. The small footprint packages, for through

hole or surface mounting, make this microcontroller

series perfect for applications with space limitations.

Low-cost, low-power, high performance, ease of use

and I/O flexibility make the PIC12C5XX series v ery ver-

satile even in areas where no micro controller use ha s

been conside red before (e.g., timer functions, replace-

ment of “glue” logic and PLD’s in larger systems, copro-

cessor applications).

 1999 Microchip Technology Inc. DS40139E-page 5

PIC12C5XX

TABLE 1-1: PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES

PIC12C508(A) PIC12C509(A) PIC12CR509A PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674

Clock

Maximum

Frequency

of Operation

(MHz)

4444410101010

Memory

EPROM

Program

Memory

512 x 12 1024 x 12 1024 x 12

(ROM) 512 x 12 1024 x 12 1024 x 14 2048 x 14 1024 x 14 2048 x 14

RAM Data

Memory

(bytes)

25 41 41 25 41 128 128 128 128

Peripherals

EEPROM

Data Memory

(bytes)

———1616——1616

Timer

Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0

A/D Con-

verter (8-bit )

Channels

—————4444

Features

Wake-up

from SLEEP

on pin

change

Yes Yes Yes Yes Yes Yes Yes Yes Yes

Interrupt

Sources ——— 4444

I/O P ins 5 5 5 5 5 5 5 5 5

Input Pins111111111

Internal Pull-ups Yes Yes Yes Yes Yes Yes Yes Yes Yes

In-Circuit Serial Programming

Yes Yes — Yes Yes Yes Yes Yes Yes

Number of

Instructions 33 33 33 33 33 35 35 35 35

Packages 8-pin DIP,

JW, SOIC 8-pin DIP,

JW, SOIC 8-pi n D IP,

SOIC 8-pi n DIP,

JW, SOIC 8- p i n D IP,

JW, SOIC 8-pin DIP,

JW 8-pin DIP,

All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O

current capability.

All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.

PIC12C5XX

DS40139E-page 6  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 7

PIC12C5XX

2.0 PIC12C5XX DEVICE VARIETIES

A variety of packaging options are available.

Depending on application and production

requirements, the proper device option can be

selected using the information in this section. When

placing orders, please use the PIC12C5XX Product

Identification System at the back of this data sheet to

specify the correct part number.

2.1 UV Erasable Devices

The UV erasable version, offered in ceramic side

brazed package, is optimal for prototype development

and pilot programs.

The UV erasable version can be erased and

reprogrammed to any of the configuration modes.

Microchip’s PICSTART PLUS and PRO MATE pro-

grammers all support programming of the PIC12C5XX.

Third party progr ammers also are availab le; refer to the

Microchip

Third Party Guide

for a list of sources.

2.2 One-Time-Programmable (OTP)

Devices

The availability of OT P devices is especia lly useful for

customers who need the flexibility for frequent code

updates or small volume applications.

The OTP devices, pac kaged in plastic packages permit

the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be saved prior

to erasing the part.

2.3 Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devi ces but with all EPROM locations and fuse

options already programmed by the factory. Certain

code and prototype verification procedures do apply

before production shipments are av ailab le. Please con-

tact your local Microchip Technology sales office for

more details.

2.4 Serialized Quick-Turnaround

Production (SQTPSM) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

2.5 Read Only Memory (ROM) Device

Microchip offers masked ROM to give the cus tomer a

low cost option for high volume, mature products.

PIC12C5XX

DS40139E-page 8  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 9

PIC12C5XX

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can

be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC12C5XX uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

single word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instructions

(33) execute in a si ngl e cycl e (1µs @ 4MHz) e xcept f or

program branches.

The table below lists program memory (EPROM), data

memory (RAM), ROM memory, and non-volatile

(EEPROM) for each device.

The PIC12C5XX can directly or indirectly address its

registers including the program counter are mapped in

the data memory. The PIC12C5XX has a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make

programming with the PIC12C5XX simple yet efficient.

In addition, the learning curve is reduced significantly.

Device

Memory

EPROM

Program ROM

Program RAM

Data EEPROM

Data

PIC12C508 512 x 12 25

PIC12C509 1024 x 12 41

PIC12C508A 512 x 12 25

PIC12C509A 1024 x 12 41

PIC12CR509A 1024 x 12 41

PIC12CE518 512 x 12 25 x 8 16 x 8

PIC12CE519 1024 x 12 41 x 8 16 x 8

The PIC12C5XX device contains an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is ei ther a file regi ster or an immediate

constant. In single operand instructions, the oper and is

either the W register or a file register.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

PIC12C5XX

DS4013 9E -pag e 1 0  1999 Microchip Technology Inc.

FIGURE 3-1: PIC12C5XX BLOCK DIAGRAM

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

ROM/EPROM

Program

Memory

12 Data Bus 8

Program

Bus

Instruction reg

Program C ounter

RAM

File

Registers

Direct Addr 5

RAM Addr 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2

MCLR VDD, VSS

Timer0

GPIO

GP4/OSC2

GP3/MCLR/VPP

GP2/T0CKI

GP1

GP0

5-7

GP5/OSC1/CLKIN

STACK1

STACK2

512 x 12 or

25 x 8 or

1024 x 12

41 x 8

Internal RC

OSC

16 X 8

EEPROM

Data

Memory

PIC12CE5XX

Only

SDA

SCL

 1999 Microchip Technology Inc. DS40139E-page 11

PIC12C5XX

TABLE 3-1: PIC12C5XX PINOUT DESCRIPTION

Name DIP

Pin # SOIC

Pin # I/O/P

Type Buffer

Type Description

GP0 7 7 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP1 6 6 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can

be software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. This buffer is a

Schmitt Trigger input when used in serial programming

mode.

GP2/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be configured as T0CKI.

GP3/MCLR/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming volt-

age input. When configured as MCLR, this pin is an

active low reset to the device. Voltage on MCLR/VPP

must not exceed VDD during normal device operation

or the device will enter programming mode. Can be

software programmed for internal weak pull-up and

wake-up from SLEEP on pin change. Weak pull-up

always on if configured as MCLR. ST when in MCLR

mode.

GP4/OSC2 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con-

nections to crystal or resonator in crystal oscillator

mode (XT and LP modes only, GPIO in other modes).

GP5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external

clock source input (GPIO in Internal RC mode only,

OSC1 in all other oscillator modes). TTL input when

GPIO, ST input in external RC oscillator mode.

VDD 11P— Positive supply for logic and I/O pins

VSS 8 8 P — Ground reference for logic and I/O pins

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,

ST = Schmitt Trigger input

PIC12C5XX

DS40139E-page 12  1999 Microchip Technology Inc.

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is inter nal ly divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter is incremented every Q1, and the

instruction is fetched from program memory and

latched into instruction register in Q4. It is decoded

and executed during the following Q1 through Q4. The

clocks and instruction execution flow is shown in

Figure 3-2 and Example 3-1.

3.2 Instruction Flow/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the

instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the Instruction Register (IR) in cycle Q1.

This instruction is then decoded and executed during

the Q2, Q3, and Q4 cycles. Data memory is read

during Q2 (operand read) and written during Q4

(destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

PC PC PC+1 PC+2

Fetch INST (PC)

Exe cut e INST (PC-1) Fetch INST (PC+1)

Ex ecute INST (PC) Fetch INST (P C+2)

Ex ecute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “flushed” from the pipe line while the new instruction is being fetched and then executed.

1. MOVLW 03H Fetch 1 Execute 1

2. MOVWF GPIO Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF GPIO, BIT1 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

 1999 Microchip Technology Inc. DS40139E-page 13

PIC12C5XX

4. 0 MEMORY ORG ANIZATION

PIC12C5XX me mory is organized into program mem-

or y and d ata me mory. For dev ices w ith mor e than 512

bytes of program memory, a paging scheme is used.

Program memory pages are accessed using one STA-

TUS register bit. For the PIC12C509, PIC12C509A,

PICCR509A and PIC12CE519 with a data memory

scheme is used. Data memory banks are accessed

using the File Select Register (FSR).

4.1 Program Memory Organization

The PIC12C5XX devices have a 12-bit Program

Counter (PC) capable of addressing a 2K x 12

program memory space.

Only the first 512 x 12 (0000h-01FFh) for the

PIC12C508, PIC12 C508A and PIC12C E518 and 1K x

12 (0000h-03FFh) for the PIC12C509, PIC12C509A,

PIC12CR509A, and PIC12CE519 are physically

implemented. Refer to Figure 4-1. Accessing a

location above these boundaries will cause a wrap-

around within the first 512 x 12 space (PIC12C508,

PIC12C508A and PIC12CE518) or 1K x 12 space

(PIC12C509, PIC12C509A, PIC12CR509A and

PIC12CE519). The effective reset vector is at 000h,

(see Figure 4-1). Location 01FFh (PIC12C508,

PIC12C508A and PIC12CE518) or location 03FFh

(PIC12C509, PIC12C509A, PIC12CR509A and

PIC12CE519) contains the internal clock oscillator

calibration value. This value should never be

overwritten.

FIGURE 4-1: PROGRAM MEMORY MAP

AND ST ACK

CALL, RETLW PC<11:0>

Stack Level 1

Stack Level 2

User Memory

Space

0000h

7FFh

01FFh

0200h

On-chip Program

Memory

Reset Vector (note 1)

Note 1: Address 0000h becomes the

effective reset vector. Location

01FFh (PIC12C508, PIC12C508A,

PIC12CE518) or location 03FFh

(PIC12C509, PIC12C509A,

PIC12CR509A, PIC12CE519) con-

tains the MOVLW XX INTERNAL RC

oscillator calibration value.

512 Word

1024 Word 03FFh

0400h

On-chip Program

Memory

PIC12C5XX

DS4013 9E -pag e 1 4  1999 Microchip Technology Inc.

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of

RAM. Therefore, data memory for a device is specified

by its register file. The register file is divided into two

functional groups: special function registers and

general purpose regist ers.

The special function registers include the TMR0

are used to control the I/O port configuration and

prescaler options.

The general purpose registers are used for data and

control information under command of the instructions.

For the PIC12C508, PIC12C508A and PIC12CE518,

the register file is composed of 7 special function

registers and 25 general purpose registers (Figure 4-

2).

For the PIC12C509, PIC12C509A, PIC12CR509A,

and PIC12CE519 the register file is composed of 7

special function registers, 25 general purpose

registers, and 16 general purpose registers that may

be addressed using a banking scheme (Figure 4-3).

4.2.1 GENERAL PUR POSE REGISTER FILE

The general purpose register file is accessed either

directly or indirectly through the file select register FSR

(Section 4.8).

FIGURE 4-2: PIC12C508, PIC12C508A AND

PIC12CE518 REGISTER FILE

MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.8

FIGURE 4-3: PIC12C509, PIC12C509A, PIC12CR509A AND PIC12CE519 REGISTER FILE MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

1Fh

INDF(1)

TMR0

PCL

STATUS

FSR

OSCCAL

GPIO

0Fh 10h

Bank 0 Bank 1

3Fh

30h

20h

2Fh

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

Addresses map

back to

addresses

in Bank 0.

Note 1: Not a physical register. See Se ction 4. 8

FSR<6:5> 00 01

 1999 Microchip Technology Inc. DS40139E-page 15

PIC12C5XX

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control

the operation of the device (Table 4-1).

The special registers can be classified into two sets.

The special function registers associated with the

“core” functions are described in this section. Those

related to the op eration of the per ipheral features are

described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets(2)

N/A TRIS — — --11 1111 --11 1111

N/A OPTION Contains control bits to configure Timer0, Timer0/W DT

presc al e r, wake-up on chan ge, an d wea k pul l-u ps 1111 1111 1111 1111

00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

02h(1) PCL Low order 8 bits of PC 1111 1111 1111 1111

03h STATUS GPWUF —PA0TO PD ZDCC

0001 1xxx q00q quuu(3)

04h

FSR

(PIC12C508/

PIC12C508A/

PIC12C518) Indirect data memory address pointer 111x xxxx 111u uuuu

04h

FSR

(PIC12C509/

PIC12C509A/

PIC12CR509A/

PIC12CE519) Indirect data memory address pointer 110x xxxx 11uu uuuu

05h

OSCCAL

(PIC12C508/

PIC12C509) CAL3 CAL2 CAL1 CAL0 — — — — 0111 ---- uuuu ----

05h

OSCCAL

(PIC12C508A/

PIC12C509A/

PIC12CE518/

PIC12CE519/

PIC12CR509A) CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — 1000 00-- uuuu uu--

06h

GPIO

(PIC12C508/

PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A) —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

06h

GPIO

(PIC12CE518/

PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

Legend: Shaded boxes = unimplemented or unused, — = unimplemented, read as ’0’ (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 8.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6

for an explanation of how to access these bits.

2: Other (non power-up) resets include external reset through MCLR, watchdog timer and wake-up on pin change reset.

3: If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0.

PIC12C5XX

DS4013 9E -pag e 1 6  1999 Microchip Technology Inc.

4.3 STATUS Register

This register contains the arithme tic status of the ALU,

the RESET status, and the page preselect bit for

program memories larger than 512 words.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to

the device logic. Fur ther m ore, the TO and PD bits are

not writable. Therefore, the result of an instruction with

the STATUS register as destination may be different

than intended.

For example, CLRF STATUS will clear the upper three

bits and s et the Z bit. Th is leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and

MOVWF instructions be used to alter the STATUS

DC or C bits from the STATUS register. For other

instructions, which do affect STATUS bits, see

Instruction Set Summary.

FIGURE 4-4: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

GPWUF —PA0 TO PD Z DC C R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7: GPWUF: GPIO reset bit

1 = Reset due to wake-up from SLEEP on pin change

0 = After power up or other reset

bit 6: Unimplemented

bit 5: PA0: Program page preselect bits

1 = Page 1 (200h - 3FFh) - PIC12C509, PIC12C509A, PIC12CR509A and PIC12CE519

0 = Page 0 (000h - 1FFh) - PIC12C5XX

Each page is 512 bytes.

Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power- down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively

0 = A carry did not occur 0 = A borrow occurred

 1999 Microchip Technology Inc. DS40139E-page 17

PIC12C5XX

4.4 OPTION Reg ister

The OPTION register is a 8-bit wide, write-only

configure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled

for that pin; i.e., note that TRIS overrides

OPTION control of GPPU and GPWU.

Note: If the T0CS bit is set to ‘1’, GP2 is f orced to

be an input even if TRIS GP2 = ‘0’.

FIGURE 4-5: OPTION REGISTER

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

U = Unimplemented bit

- n = Value at POR reset

Reference Table 4-1 for

other resets.

bit7 6 5 4 3 2 1 bit0

bit 7: GPWU: Enable wake-up on pin change (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 6: GPPU: Enable weak pull-ups (GP0, GP1, GP3)

1 = Disabled

0 = Enabled

bit 5: T0CS: Timer0 clock source select bit

1 = Transition on T0CKI pin

0 = Transition on internal instruction cycle clock, Fosc/4

bit 4: T0SE: Timer0 source edge select bit

1 = Increment on high to low transition on the T0CKI pin

0 = Increment on low to high transition on the T0CKI pin

bit 3: PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler rate select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value Timer0 Rate WDT Rate

PIC12C5XX

DS4013 9E -pag e 1 8  1999 Microchip Technology Inc.

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to

calibrate the internal 4 MHz oscillator . It contains four to

six bits for calibration. Increasing the cal value

increases the frequency. See Section 7.2.5 for more

information on the internal oscillator.

FIGURE 4-6: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508 AND PIC12C509

FIGURE 4-7: OSCCAL REGISTER (ADDRESS 05h) FOR PIC12C508A/C509A/CR509A/12CE518/

12CE519

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0

CAL3 CAL2 CAL1 CAL0 ———— R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-4: CAL<3:0>: Calibration

bit 3-0: Unimplemented: Read as ’0’

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —— R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: CAL<5:0>: Calibration

bit 1-0: Unimplemented: Read as ’0’

 1999 Microchip Technology Inc. DS40139E-page 19

PIC12C5XX

4.6 Program Counter

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

For a GOTO instruc tion, bi ts 8:0 of th e PC are provided

by the GOTO instruction word. The PC Latch (PCL) is

mapped to PC<7:0>. Bit 5 of the STATUS register

provides page i nformation to bi t 9 of the PC ( Figur e 4-

8).

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 4-8).

Instructions where the PCL is the destination, or

Modify PCL instr uctions, include MOVWF PC, ADDWF

PC, and BSF PC,5.

FIGURE 4-8: LOADING OF PC

BRANCH IN STRUCTIONS -

PIC12C5XX

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL i nstruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any pro-

gram memory page (512 words long).

PA0

STATUS

PC 87 0

PCL

910

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PA0

STATUS

PC 87 0

PCL

910

Instruction Word

Reset to ‘0’

4.6.1 EFFECTS OF RESET

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page i.e., the oscillator calibration instruction. After

executing MOVLW XX, the PC will roll over to location

00h, and begin executing user code.

The STATUS register page preselect bits are cleared

upon a RESET, which means that page 0 is pre-

selected.

Therefore, upon a RESET, a GOTO instruction will

automatically cause the program to jump to page 0

until the value of the page bits is altered.

4.7 Stack

PIC12C5XX devices have a 12-bit wide L.I.F.O.

hardware push/pop stack.

A CALL instruction will

push

the current value of stack

1 into stack 2 and then push the current program

counter value, incremented by one , into stack level 1. If

more than two sequential CALL’s are executed, only

the most recent two return addresses are stored.

A RETLW instruction will

pop

the contents of stack level

1 into the program counter and then copy stack level 2

contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2. Note that the

W register will be loaded with the literal value specified

in the instruction. This is particularly useful for the

implementation of data look-up tables within the

program memory.

Upon any reset, the contents of the stack remain

unchanged, however the program counter (PCL) will

also be reset to 0.

Note 1: There are no STATUS bits to indicate

stack overflows or stack underflow condi-

tions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLW instructions.

PIC12C5XX

DS4013 9E -pag e 2 0  1999 Microchip Technology Inc.

4.8 Indirect Data Addressing; INDF and

FSR Registers

The INDF register is not a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a

pointer

). This is indirect ad dressin g.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 07 contains the value 10h

• Register file 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Wr iting to th e INDF register indi rectly results i n a

no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x10 ;initialize pointer

movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer

btfsc FSR,4 ;all done?

goto NEXT ;NO, clear next

CONTINUE : ;YES, continue

The FSR is a 5-bit wide register. It is used in

conjunction with the INDF register to indirectly address

the data m emory area.

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

PIC12C508/PIC12C508A/PIC12CE518: Does not

use banking. FSR<7:5> are unimplemented and read

as '1's.

PIC12C509/PIC12C509A/PIC12CR509A/

PIC12CE519: Uses FSR<5>. Selects between bank 0

and bank 1. FSR<7:6> is unimplemented, read as '1’ .

FIGURE 4-9: DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 4.2.

Note 2: PIC12C509, PIC12C509A, PIC12CR509A, PIC12CE519.

bank location select

location select

bank select

Indirect Addressing

Direct Addressing

Data

Memory(1) 0Fh

10h

Bank 0 Bank 1(2)

6(FSR)

00 01

00h

1Fh 3Fh

(opcode) 04

(FSR)

Addresses

map back to

addresses

in Bank 0.

 1999 Microchip Technology Inc. DS40139E-page 21

PIC12C5XX

5.0 I/O PORT

As with any other register, the I/O register can be

written and read under program c ontrol. However, read

instructions (e.g., MOVF GPIO,W) always read the I /O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance) since the I/O control registers are all

set. See Section 7.0 for SCL and SDA description for

PIC12CE5XX.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits

are used (GP5:GP0). Bits 7 and 6 are unimplemented

and read as '0's. Pleas e note that GP3 is an input only

pin. The configuration word can set several I/O’s to

alternate functions. When acting as alternate functions

the pins will read as ‘0’ during port read. Pins GP0,

GP1, and GP3 can be configured with weak pull-ups

and also with wake-up on change. The wake-up on

change and weak pull-up functions are not pin

selectable. If pin 4 is configured as MCLR , weak pull-

up is always on and wake-up on change for this pin is

not enabled.

5.2 TRIS Register

The output driver control register is loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the conte nts of the output data latch o n the

selected pins, enabling the output buffer. The

exceptions are GP3 which is input only and GP2 which

may be controlled by the op tion re gister, see Figure 4-

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

Note: A read of th e ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the exter nal system is holding it low, a

read of the port will indi cate that th e pi n is

low.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All port pins, except GP3 which is input

only, ma y be used for both input and output operations.

For input operations these por ts are non-latc hing. Any

input must be present until read by an input instruction

(e.g., MOVF GPIO,W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the correspon ding TRIS bit must be set. Any I/O

pin (except GP3) can be programmed individually as

input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data

Bus

CK P

Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O

pin(1,3)

Reg

Latch

Reset (2)

Note 1: I/O pins have protection diodes to VDD

and VSS.

Note 2: See Table 3-1 for buffer type.

Note 3: See Section 7.0 for SCL and SDA

description for PIC12CE5XX

PIC12C5XX

DS40139E-page 22  1999 Microchip Technology Inc.

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset Value on

All Other Resets

N/A TRIS — — --11 1111 --11 1111

N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

03H STATUS GPWUF —PAO TO PD ZDC C0001 1xxx q00q quuu(1)

06h

GPIO

(PIC12C508/

PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A) —— GP5 GP4 GP3 GP2 GP1 GP0 --xx xxxx --uu uuuu

06h

GPIO

(PIC12CE518/

PIC12CE519) SCL SDA GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

q = see tables in Section 8.7 for possible v alues.

Note 1: If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0.

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONA L I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCF and BSF in str u ct ion s, for

example, read the entire port into the CPU, execute

the bit operation and re-wr ite the result. Caution must

be used when these i nstructions a re applied to a por t

where one or more pins are used as input/outputs. For

example, a BSF operation on bit5 of GPIO will cause

all eight bits of GPIO to b e read into the CPU, b it5 to

be set and the GP IO val ue to be written to the output

latches. If another bit of GPIO is used as a bi-

directional I/O pin (say bit0) and it is defined as an

input at this time, the input signal present on the pin

itself would be rea d into the C PU and rewritten to the

data latch of this particular pin, overwriting the

previous content. As long as the pin stays in the input

mode, no problem occurs. However, i f bit0 is sw itched

into output mode later on, the content of the data latch

may now be unknown.

Example 5-1 shows the effect of two sequential read-

modify-wri te instructions (e.g., BCF, BSF, etc.) on an

I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”, “wired-

and”). The resul ting high output curren ts may damage

the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

;Initial GPIO Settings

; GPIO<5:3> Inputs

; GPIO<2:0> Outputs

;

; GPIO latch GPIO pins

; ---------- ----------

BCF GPIO, 5 ;--01 -ppp --11 pppp

BCF GPIO, 4 ;--10 -ppp --11 pppp

MOVLW 007h ;

TRIS GPIO ;--10 -ppp --11 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

5.4.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of

an instruction cycle, whereas for reading, the data

must be valid at the beginning of the instruction cycle

(Figure 5-2). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should

allow the pin voltage to stabilize (load dependent)

before the next instruction, which causes that file to be

read into the CPU, is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

 1999 Microchip Technology Inc. DS40139E-page 23

PIC12C5XX

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2 PC + 3

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Instruction

fetched

GP5:GP0

MOVWF GPIO NOP

Port pin

sampled here

NOP

MOVF GPIO,W

Instruction

executed MOVWF GP IO

(Write to

GPIO)

NOP

MOVF GPIO,W

This example shows a write to GPIO followed

by a read from GPIO.

Data setup time = (0.25 TCY – TPD)

where: TCY = instr uct ion cyc le.

TPD = propag atio n delay

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

(Read

GPIO)

Port pin

written here

PIC12C5XX

DS40139E-page 24  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 25

PIC12C5XX

6.0 TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written , the increment is inhibited for

the following two instruction cycles (Figure 6-2 and

Figure 6-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on ever y r ising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge.

Restri ctions on the ex ternal clock input are disc ussed

in detail in Section 6.1.

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of 1:2,

1:4,..., 1:256 are selectable. Section 6.2 details the

operation of the prescaler.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figur e 6-5).

T0CS(1)

FOSC/4

Programmable

Prescaler(2)

Sync with

Internal

Clocks TMR0 reg

PSout

(2 TCY delay)

PSout

Data bus

PSA(1)

PS2, PS1, PS0(1)

Sync

T0SE

GP2/T0CKI

PIC12C5XX

DS40139E-page 26  1999 Microchip Technology Inc.

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCAL E

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

01h TMR0 Timer0 - 8-bi t real-time clock/counter xxxx xxxx uuuu uuuu

N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

N/A TRIS ——GP5GP4 GP3 GP2 GP1 GP0 --11 1111 --11 1111

Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged,

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0+1 NT0+2

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

 1999 Microchip Technology Inc. DS40139E-page 27

PIC12C5XX

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it

must meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1 E XTERNAL CLOCK SYNCHRONIZATION

When no pres caler is used, the external clo ck input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampl ing th e pres caler out put on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-4). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they

do not violate the minimum pulse wi dth requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figu re 6-4 shows the

delay from the external clock edge to the timer

incrementing.

6.1.3 OPTION REGISTER EFFECT ON GP2 TRIS

If the option register is set to read TIMER0 from the pin,

the port is forced to an input regardless of the TRIS reg-

ister setting.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

External Clo ck/P res cal er

Output After Sampling (3)

Note 1:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

Prescaler Output (2)

(1)

PIC12C5XX

DS4013 9E -pag e 2 8  1999 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT), respectively (Section 8.6). For simplicity,

this counter is being referred to as “prescaler”

throughout this data sheet. Note that the prescaler

may be used by either the Timer0 module or the WDT,

but not both. Thus, a prescaler assignment for the

Timer0 module means that there is no prescaler for

the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>)

determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1,x, etc.) will clear the prescaler.

When assigned to WDT, a CLRWDT instruction will

clear the pre scaler along with the W DT. The pre scaler

is neither readable nor writable. On a RESET, the

prescaler contains all '0's.

6.2.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under softwa re cont rol

(i.e., it can be changed “on the fly” during program

execution). To avoid an unintended device RESET, the

following instruction sequence (Example 6-1) must be

ex ecuted when changing the prescaler assignment from

Timer0 to the WDT.

EXAMPLE 6-1: CHANGIN G PRESCALER

(TIMER0→WDT)

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ; T h e s e 3 l i n e s ( 5 , 6 , 7 )

4.OPTION ; are required only if

; desired

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0

modul e, use th e sequ enc e show n in Ex amp le 6-2 . This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

sw i tching t he prescaler.

EXAMPLE 6-2: CHANGIN G PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW 'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

OPTION

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

Sync

Cycles TMR0 reg

8-bit Prescaler

8 - to - 1MUX

MUX

Watchdog

Timer

PSA

WDT

Time-Out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

PSA

WDT Enable bit

Data Bus

PSA

T0CS

T0SE

GP2/T0CKI

 1999 Microchip Technology Inc. DS40139E-page 29

PIC12C5XX

7.0 EEPROM PERIPHERAL

OPERATION

This section applies to PIC12CE518 and

PIC12CE519 only.

The PIC12CE518 and PIC12CE519 each have 16

bytes of EEPROM data memory. The EEPROM mem-

or y has an endurance of 1,000,000 erase/write cycles

and a data retention of greater than 40 years. The

EEPROM data memory supports a bi-directional 2-wire

bus and data transmission protoc ol. These two-wires

are serial data (SDA) and serial clock (SCL), that are

mapped to bit6 and bit7, respectively, of the GPIO reg-

ister (SFR 06h). Unlike the GP0-GP5 that are con-

nected to the I/O pins, SDA and SCL are only

connected to the internal EEPROM peripheral. For

most applications, all that is re quired is calls to th e fol-

lowing functions:

; Byte_Write: Byte write routine

; Inputs: EEPROM Address EEADDR

; EEPROM Data EEDATA

; Outputs: Return 01 in W if OK, else

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

; Inputs: NONE

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK, else

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

address

; Inputs: EEPROM Address EEADDR

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK,

else return 00 in W

The code for these functions is av ailable on our website

www.microchip.com. The code will be accessed by

either including the source c ode FL51XINC.ASM or by

linking FLASH5IX.ASM.

It is very important to check the return codes when

using these calls, and retry the operation if unsuccess-

ful. Unsuccessful return codes occur when the EE data

memory is busy with the previous write, which can take

up to 4 mS.

7.0.1 SERIAL DATA

SDA is a b i-directional pin us ed to transfer addresses

and data into and data out of the device.

For normal data transfer SD A is allo wed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

The EEPROM interface is a 2-wire bus protocol con-

sisting of data (SDA) and a clock (SCL). Although

these lines are mapped into the GPIO register, they are

not accessible as external pins; only to the internal

EEPROM peripheral. SDA and SCL operation is also

slightly different than GPO-GP5 as listed below.

Namely, to avoid code overhead in modifying the TRIS

read data from the EEPROM peripheral requires out-

putting a ‘1’ on SDA placing it in high-Z state, where

only the internal 100K pull-up is activ e on the SDA line.

SDA: Built-in 100K (typical) pull-up to VDD

Open-drain (pull-down only)

Always an output

Outputs a ‘1’ on reset

SCL: Full CMOS output

Always an output

Outputs a ‘1’ on reset

The following example requires:

• Code Space: 77 words

• RAM Space: 5 bytes (4 are overlayable)

• Stack Le vels:1 (The call to the function itself. The

functions do not call any lower level functions.)

• Timing:

- WRITE_BYTE takes 328 cycles

- READ_CURRENT takes 212 cycles

- READ_RANDOM takes 416 cycles.

• IO Pins: 0 (No external IO pins are used)

This code must reside in the lower half of a page. The

code achieves it’s small size without additional calls

through the use of a s equencing table. The table is a

list of procedures that must be called in order. The

table uses an ADDWF PCL,F instruc tion, effectively a

computed goto, to sequence to the next procedure.

However the ADDWF PCL,F instr uction yields an 8 bit

address, forcing the code to reside in the first 256

addresses of a page.

PIC12C5XX

DS4013 9E -pag e 3 0  1999 Microchip Technology Inc.

Figure 7-1: Bloc k diagram of GPIO6 (SDA line)

Figure 7-2: Bloc k diagram of GPIO7 (SCL line)

reset

ck Q

databus write

Output Latch

To 24L00 SDA

Schmitt Trigger

ltchpin

Input Latch

Read

VDD

Pad

GPIO

ck Q

databus write

To 24LC00 SCL

ltchpin

Read

VDD

Pad

Schmitt Trigger

GPIO

 1999 Microchip Technology Inc. DS40139E-page 31

PIC12C5XX

7.0.2 SERIAL CLOCK

This SCL input is used to synchroniz e the data transf er

from and to the device.

7.1 BUS CHARACTERISTICS

The following bus protocol is to be used with the

EEPROM data memory.

• Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable

whenever the clock line is HIGH. Chan ges in the data

line while the clock line is HIGH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 7-3).

7.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

7.1.2 ST ART DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

7.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH deter min es a STOP condition. All

operations must be ended with a STOP condition.

7.1.4 DATA VALID (D)

The state of the data line rep resents valid data when,

after a START condition, the data l ine is stable fo r the

duration of the HIGH period of the clock signal.

The data on the line must be changed duri ng the LOW

period of the clock signal. There is one bit of da ta per

clock pulse.

Each data transfer is initiated with a START condition

and ter m inated wi th a STOP condition. The numbe r of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited.

7.1.5 ACKNOWLEDGE

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the

SD A line during the ac knowledge clock pulse in such a

way that the SDA line is stable LOW during the HIG H

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clock ed out of the slave . In this case,

the slave must leave the dat a line HIGH to enable the

master to generate the STOP condition (Figure 7-4).

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

PIC12C5XX

DS40139E-page 32  1999 Microchip Technology Inc.

FIGURE 7-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 7-4: ACKNOWLEDGE TIMING

(A) (B) (C) (D) (A)(C)

SCL

SDA

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL 987654321123

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this poi nt

so the Transmitter can continue sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

7.2 Device Addressing

After generating a START condition, the bus master

transmits a control byte consisting of a slave address

and a Read/Write bit that indicates what type of opera-

tion is to be performed. T he slave add ress consists of

a 4-bit device code (1010) followed by three don’t care

bits.

The last bit of the control byte determines the operation

to be perf ormed. When set to a one a read operation is

selected, and when set to a zero a write operation is

selected. (Figure 7-5). The bus is monitored for its cor-

responding slave address all the time. It generates an

acknowledge bit if the slave address was true and it is

not in a programming mode.

FIGURE 7-5: CONTROL BYTE FORMAT

1010XXXSACKR/W

Device Select

Bits Don’t Care

Bits

Slave Address

Acknowledge Bit

Start Bit

Read/Write Bit

 1999 Microchip Technology Inc. DS40139E-page 33

PIC12C5XX

7.3 WRITE OPERATIONS

7.3.1 BYTE WRITE

Following the start signal from the master, the device

code (4 bits), the don’t care bits (3 bits), and the R/W

bit (which is a logic low) are placed onto the bus by the

master transmitter. This indicates to the addressed

slave receiv er that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the master is the word address and will be written

into the address pointer. Only the lower four address

bits are used by the device, and the upper four bits are

don’t cares. The address byte is acknowledgeable and

the master device will then transmit the data word to be

written into the addressed memory location. The mem-

ory acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this time will not generate acknowledge sig-

nals (Figure 7-7). After a byte write command, the inter-

nal address counter will not be incremented and will

point to the same address location that was just written.

If a stop bit is transmitted to the device at any point in

the write command sequence before the entire

sequence is complete, then the command will abort

and no data will be written. If more than 8 data bits are

transmitted before the stop bit is sent, then the dev ice

will clear the previously loaded byte and begin loading

the data buffer again. If more than one data byte is

transmitted to the device and a stop bit is sent bef ore a

full eight data bits hav e been transmitted, then the write

command will abort and no data will be written. The

EEPROM memory employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below minimum VDD.

Byte write operations must be preceded and immedi-

ately followed by a bus not busy bus cycle where both

SDA and SCL are held high.

7.4 ACKNOWLEDGE P OLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the inter nally timed write c ycle. ACK polling can

be initiated immediately . This inv olves the master send-

ing a star t condition followed by the control byte for a

write command (R/W = 0). If the de vice is still busy with

the write cycle, then no A CK will be returned. If no ACK

is retur ned, then the s tar t bit and cont rol byte must be

re-sent. If the cycle is complete, then the device will

retur n the ACK and the master can then proceed with

the next read or write command. See Figure 7-6 for

flow diagram.

FIGURE 7-6: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 7-7: BYTE WRITE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE WORD

ADDRESS DATA

10 X10 XXX

X = Don’t Care Bit

XXX

PIC12C5XX

DS4013 9E -pag e 3 4  1999 Microchip Technology Inc.

7.5 READ OPERATIONS

Read operations are initiated in the same way as wr ite

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.5.1 CURR ENT ADDRESS READ

It contains an address counter that maintains the

address of the last word accessed, internally incre-

mented by one. Therefore, if the prev ious read access

was to address n, the next current address read opera-

tion would access data from address n + 1. Upon

receipt of the slav e address with the R/W bit set to one,

the device issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer b ut does generate a stop condition and the

device discontinues transmission (Figure 7-8).

7.5.2 RANDOM READ

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

device as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then th e master issues the c ontrol byte again but

with the R/W bit set to a one. It will then issue an

acknowledge and transmits the eight bit data word. The

master will not acknowledge the transfer but does gen-

erate a stop condition and the device discontinues

transmission (Figure 7-9). After this command, the

intern al ad dress cou nter will poin t to the addres s loca-

tion following the one that was just read.

7.5.3 SEQUENTIAL READ

Sequential reads are initiated in the same way as a ran-

dom read except that after the device transmits the first

data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the device to transmit the next sequentially

addressed 8-bit word (Figure 7-10).

To provide sequential reads, it contains an internal

address pointer which is incremented by one at the

completion of each read operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

FIGURE 7-8: CURRENT ADDRESS READ

FIGURE 7-9: RANDOM READ

FIGURE 7-10: SEQUENTIAL READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

1100XXX1

X = Don’t Care Bit

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

DATA (n)

XXXX

S1 100XXX0 S1100XXX1

X = Don’t Care Bit

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

 1999 Microchip Technology Inc. DS40139E-page 35

PIC12C5XX

8.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other

processors are special circuits to deal with the needs

of real-time applications. The PIC12C5XX family of

microcontrollers has a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power

saving operating modes and offer code protection.

These features are:

• Oscillator selection

• Reset

- Power-On Reset (POR)

-Device Reset Timer (DRT)

- Wake-up from SLEEP on pin change

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit Serial Programming

The PIC12C5XX has a Watchdog Timer which can be

shut off only through configuration bit WDTE. It runs

off of its own RC os cillator for added reliability. If using

XT or LP selectable oscillator options, there is always

an 18 ms (nominal) delay provided by the Device

Reset Timer (DRT), intended to keep the chip in reset

until the crystal oscillator is stable. If using INTRC or

EXTRC there is an 18 ms delay only on VDD power-up .

With this timer on-chip, most applications need no

external reset circuitry.

The SLEEP mode is designed to offer a very low

current power-down mode. The user can wake-up

from SLEEP through a change on input pins or

through a Watchdog Timer time-o ut. Several oscillator

options are also made available to allow the par t to fit

the applic ation, including an internal 4 MHz oscillator.

The EXTRC oscillator opti on saves system cost while

the LP crystal option saves power. A set of

configuration bits are used to select various options.

8.1 Configuration Bits

The PIC12C5XX configuration word consists of 12

bits. Configuration bits can be programmed to select

various device configurations. Two bits are for the

selection of the os cillator type, one bit is the Watchdog

Timer enable bit, and one bit is the MCLR enable bit.

FIGURE 8-1: CONFIGURATION WORD FOR PIC12C5XX

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0 Register: CONFIG

Address(1):FFFh

bit1110987654321bit0

bit 11-5: Unimplemented

bit 4: MCLRE: MCLR enable bit.

1 = MCLR pin enabled

0 = MCLR tied to VDD, (Internally)

bit 3: CP: Code protection bit.

1 = Code protection off

0 = Code protection on

bit 2: WDTE: Wat chd og time r enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = EXTRC - external RC oscillator

10 = INTRC - internal RC oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC12C5XX Programming Specifications to determine how to access the

configuration word. This register is not user addressable during device operation.

PIC12C5XX

DS4013 9E -pag e 3 6  1999 Microchip Technology Inc.

8.2 Oscillator Configurations

8.2.1 OSCILLATOR TYPES

The PIC12C5XX can be operated in four different

oscillator modes. The user can program two

configuration bits (FOSC1:FOSC0) to select one of

these four modes:

•LP: Low Power Crystal

• XT: Crystal/Resonator

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

8.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT or LP modes, a crystal or ceramic resonator is

connected to the GP5/OSC1/CLKIN and GP4/OSC2

pins to establish oscillation (Figure 8-2). The

PIC12C5XX oscillator design requires the use of a

paral lel cut crystal. Us e of a series cut crystal ma y giv e

a frequency out of the crystal manufacturers

specifications. When in XT or LP modes, the device

can have an external clock source drive the GP5/

OSC1/CLKIN pin (Figure 8- 3).

FIGURE 8-2: CRYSTAL OPERATION (OR

CERAMIC RESONATOR) (XT

OR LP OSC

CONFIGURATION)

FIGURE 8-3: EXTERNAL CLOCK INPUT

OPERATION (X T OR LP OSC

CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF approximate value = 10 MΩ.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To internal

logic

RS(2)

PIC12C5XX

Clock from

ext. system OSC1

OSC2

Open PIC12C5XX

TABLE 8-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12C5XX

TABLE 8-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR -

PIC12C5XX

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 4.0 MHz 30 pF 30 pF

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

Osc

Type Reson ator

Freq Cap.Range

C1 Cap. Range

LP 32 kHz(1) 15 pF 15 pF

XT 200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

These values are for design guidance only. Rs may

be required to avoid overdriving crystals with low

drive level specification. Since each crystal has its

own characteristics, the user should consult the crys-

tal manufacturer for appropriate values of external

components.

 1999 Microchip Technology Inc. DS40139E-page 37

PIC12C5XX

8.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

Figure 8-4 shows implementation of a parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negati ve feedback for s tability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

FIGURE 8-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 8-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency o f the cr ystal. The inverter perform s a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 8-5: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04

CLKIN

To Other

Devices

PIC12C5XX

330

74AS04 74AS04

CLKIN

To Other

Devices

XTAL

330

74AS04

0.1 µF

PIC12C5XX

8.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low Cext values. The user als o needs to

take into account variation due to tolerance of exter nal

R and C components used.

Figure 8-6 shows how the R/C combination is

connected to the PIC12C5XX. For Rext values below

2.2 kΩ, the oscillator operation may become unsta ble,

or stop completely. For very high Rext values

(e.g., 1 MΩ) the oscillator bec omes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

Rext between 3 kΩ and 100 k Ω.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

The Electrical Specifications sections show RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capa citance will affect RC frequency

more).

Also, see the Electrical Specifications sections for

variation of oscillator frequency due to VDD for given

Rext/Cext values as well as frequency vari ation due to

operating temperature f or giv en R, C, and VDD values.

FIGURE 8-6: EXTERNA L RC OSCILLATOR

MODE

VDD

Rext

Cext

VSS

OSC1 Internal

clock

NPIC12C5XX

PIC12C5XX

DS4013 9E -pag e 3 8  1999 Microchip Technology Inc.

8.2.5 INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator provides a fix ed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, see “Electri-

cal Specifications” section for information on variation

over voltage and temperature.

In addition, a calibration instruction is programmed into

the top of memory which contains the calibration value

for the internal RC oscillator . This location is nev er code

protected regar dless of the code protect se ttings. This

value is programmed as a MOVLW XX instruction where

XX is the calibration value, and is placed at the reset

vector. This will load the W register with the calibration

value upon reset and the PC will then roll over to the

users program at address 0x000. The user then has the

option of writing the value to the OSCCAL Register

(05h) or ignoring it.

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remov e process variation

from the oscillator frequency. .

For the PIC12C508A, PIC12C509A, PIC12CE518,

PIC12CE519, and PIC12CR509A, bits <7:2>, CAL5-

CAL0 are used for calibration. Adjusting CAL5-0 from

000000 to 1111 11 yields a higher clock speed. Note

that bits 1 and 0 of OSCCAL are unimplemented and

should be written as 0 when modifying OSCCAL for

compatibility with future devices.

For the PIC12C508 and PIC12C509, the upper 4 bits of

the register are used. Writing a larger value in this loca-

tion yields a higher clock speed.

8.3 RESET

The device differentiates between various kinds of

reset:

a) Power on reset (POR)

b) MCLR reset during normal operation

c) MCLR reset during SLEEP

d) WDT time-out reset during normal operation

e) WDT time-out reset during SLEEP

f) Wake-up from SLEEP on pin change

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be read prior to

erasing the part. so it can be repro-

grammed correctly later.

Some registers are not reset in any way; they are

unknown on POR and unchanged in any other reset.

Most other registers are reset to “reset state” on pow er-

on reset (POR), MCLR, WDT or wake-up on pin

change reset during normal operation. They are not

affected by a WDT reset during SLEEP or MCLR reset

during SLEEP, since these resets are viewed as

resumption of normal operation. The exceptions to this

are TO, PD, and GP WUF bits. They are set or cleared

differently in different reset situations. These bits are

used in s oftware to determine the n ature of res et. See

Table 8-3 for a full description of reset states of all

registers.

 1999 Microchip Technology Inc. DS40139E-page 39

PIC12C5XX

TABLE 8-3: RESET CONDITIONS FOR REGISTERS

TABLE 8-4: RESET CONDITION FOR S PECIAL REGISTERS

WDT time-out

Wake-up on Pin Change

W (PIC12C 508/509) —qqqq xxxx (1) qqqq uuuu (1)

W (PIC12C508A/509A/

PIC12CE518/519/

PIC12CE509A)

—qqqq qqxx (1) qqqq qquu (1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx q00q quuu (2,3)

FSR (PIC12C508/

PIC12C508A/

PIC12CE518)

04h 111x xxxx 111u uuuu

FSR (PIC12C509/

PIC12C509A/

PIC12CE519/

PIC12CR509A)

04h 110x xxxx 11uu uuuu

OSCCAL

(PIC12C508/509) 05h 0111 ---- uuuu ----

OSCCAL

(PIC12C508A/509A/

PIC12CE518/512/

PIC12CR509A)

05h 1000 00-- uuuu uu--

GPIO

(PIC12C508/PIC12C509/

PIC12C508A/

PIC12C509A/

PIC12CR509A)

06h --xx xxxx --uu uuuu

GPIO

(PIC12CE518/

PIC12CE519)

06h

11xx xxxx 11uu uuuu

OPTION — 1111 1111 1111 1111

TRIS — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory .

Note 2: See Table 8-7 for reset value for specific conditions

Note 3: If reset was due to wake-up on pin change, then bit 7 = 1. All other resets will cause bit 7 = 0.

STATUS Addr: 03h PCL Addr: 02h

Power on reset 0001 1xxx 1111 1111

MCLR reset during normal operation 000u uuuu 1111 1111

MCLR reset during SLEEP 0001 0uuu 1111 1111

WDT reset during SLEEP 0000 0uuu 1111 1111

WDT reset normal operation 0000 uuuu 1111 1111

Wake-up from SLEEP on pin change 1001 0uuu 1111 1111

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.

PIC12C5XX
DS4013 9E -pag e 4 0  1999 Microchip Technology Inc.
8.3.1 MCLR ENABLE
This configuration bit wh en unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the inter nal
VDD, and the pin is assigned to be a GPIO. See
Figure 8-7.  When pin GP3/MCLR/VPP is configured as
MCLR, the internal pull-up is always on.
FIGURE 8-7: MCLR SELECT
8.4 Power-On Reset (POR)
The PIC12C5XX family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal
chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resist or  to  VDD or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor .
Refer to Table 11-1 for the pull-up resistor ranges. This
will eliminate extern al RC compone nts u sually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Electrical Specifications for
details.
When the device starts normal operation (exits the
reset condition), de vice operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 8-8. 
GP3/MCLR/VPP
MCLRE
INTERNAL MCLR
WEAK
PULL-UP
The Power-On Reset circuit and the Device Reset
Timer (Section 8.5) circuit are closely related. On
power-up, the reset latch is set and the  DRT is reset.
The DRT timer begins counting o nce it detects MCLR
to be high. After the time-out per iod, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR is held low is
shown in Figure 8-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
In Figure 8-10, the  on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be GP3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 8-
11 depicts a problem situation where VDD rises too
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and VDD) actually
reach their full value, is too long. In this situation, when
the star t-up timer times  out, VDD has not reached the
VDD  (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-10).
For additional information refer to Application Notes
“
Power-Up Considerations”
 - AN522 and “
Power-up
Trouble Shooting
” - AN607.
Note: When the device starts normal operation
(exits  the reset condition), de vice operating
parameters (voltage, frequency, tempera-
ture, etc.) must be meet to ensure opera-
tion. If these conditions are not met, the
device must be held in reset until the oper-
ating conditions are met.

 1999 Microchip Technology Inc. DS40139E-page 41

PIC12C5XX

FIGURE 8-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME

VDD

GP3/MCLR/VPP

Power-Up

Detect

On-Chip

DRT OSC

POR (Power-On Reset)

WDT Time-out

RESET

CHIP RESET

8-bit Asynch

Ripple Counter

(Start-Up Timer)

MCLRE

SLEEP

Pin Change Wake-up on

pin change

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNA L RES ET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERN AL RES ET

TDRT

PIC12C5XX

DS4013 9E -pag e 4 2  1999 Microchip Technology Inc.

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME

VDD

MCLR

INTERNAL POR

DRT TIME-O UT

INTERNAL RESET

TDRT

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In

this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

8.5 Device Reset Timer (DRT)

In the PIC12C5XX, DRT runs from RESET and varies

based on oscillator selection (see Table 8-5.)

The DRT operates on an internal RC oscillator. The

processor is kept in RESET as long as the DRT is

active. The DRT delay allows VDD to rise above VDD

min., and for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a R ESET condition for approximately 18

ms after MCLR has reached a logic high (VIHMCLR)

level. Thus, programming GP3/MCLR/VPP as MCLR

and using an external RC network connected to the

MCLR input is not required in most cases, allowing for

savings in cost-sensitive and/or space restricted

applications, as well as allowing the use of the GP3/

MCLR/VPP pin as a general purpose input.

The De vi ce Reset time del ay will vary from chip to c hip

due to VDD, temperature, and process variation. See

AC parameters for details.

The DRT will also be triggered upon a Watchdog

Timer time-out. This is particularly important for

applications using the WDT to wake from SLEEP

mode autom atically.

8.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free runni ng on-chip

RC oscillator which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the GP5/OSC1/CLKIN pin

and the in ternal 4 MHz os cillator. That means that the

WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or SLEEP, a WDT

reset or wake-up reset generates a device RESET.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset.

The WDT can be permanently disabled by

programming the configuration bit WDTE as a ’0’

(Section 8.1). Refer to the PIC12C5XX Programming

Specifications to determine how to access the

configuration word.

TABLE 8-5: DRT (DEVICE RESET TIMER

PERIOD)

Oscillator

Configuration POR Reset Subsequent

Resets

IntRC &

ExtRC 18 ms (typical) 300 µs (typical)

XT & LP 18 ms (typical) 18 ms (typical)

 1999 Microchip Technology Inc. DS40139E-page 43

PIC12C5XX

8.6.1 WDT PERIOD

The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is

desire d, a prescal er with a division ratio of up to 1:128

can be assigned to the WDT (under software control)

by writing to the OPTION register. Thus, a time-out

period of a nominal 2.3 seconds can be realized.

These peri ods vary with temperature, VDD and part-to-

part process variations (see DC specs).

Under worst case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

8.6.2 WDT PR OGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it

from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum SLEEP time before a WDT wake-up reset.

FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged

From Timer0 Clock S ource

(Figure 8-5)

To Timer0 (Figure 8-4)

Postscaler

WDT Enable

Confi g uration B i t

PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Postscaler

Watchdog

Timer

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

PIC12C5XX

DS4013 9E -pag e 4 4  1999 Microchip Technology Inc.

8.7 Time-Out Sequence, Power Down,

and Wake-up from SLEEP Status Bits

(TO/PD/GPWUF)

The TO, PD, and GPWUF bits in the STATUS register

can be tested to determine if a RESET condition has

been caused by a power-up condition, a MCLR or

Watchdog Timer (WDT) reset.

8.8 Reset on Brown-Out

A brown-out is a condition where device power (VDD)

dips below its minimum v alue, b ut not to z ero, and then

recovers. The device should be reset i n the event of a

brown-out.

To reset PIC12C5XX devices when a brown-out

occurs, external brown-out protection circuits may be

built, as shown in Figure 8-13 , Figure 8-14 and

Figure 8-15

FIGURE 8-13: BROWN-OUT PROTECTION

CIRCUIT 1

TABLE 8-7: TO/PD/GPWUF STATUS

AFTER RESET

GPWUF TO PD RESET caused by

0 0 0 WDT wake-up from

SLEEP

0 0 u WDT time-out (not from

SLEEP)

010MCLR

wake-up from

SLEEP

011Power-up

0uuMCLR

not during SLEEP

1 1 0 Wake-up from SLEEP on

pin change

Legend: u = unchanged

Note 1: The TO, PD, and GPWUF bits maintain

their status (u) until a reset occurs. A low-

pulse on the MCLR input does not change

the TO, PD, and GPWUF status bits.

This circuit will activate reset when VDD goes below

Vz + 0.7V (where Vz = Zener voltage).

*Refer to Figure 8-7 and Table 11-1 for internal

weak pull-up on MCLR.

33k

10k

40k* MCLR

PIC12C5XX

VDD

FIGURE 8-14: BROWN-OUT PROTECTION

CIRCUIT 2

FIGURE 8-15: BROWN-OUT PROTECTION

CIRCUIT 3

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 tur ns off when VDD

is below a certain level such that:

*Refer to Figure 8-7 and Table 11-1 for internal

weak pull-up on MCLR.

VDD • R1

R1 + R2 = 0.7V

R2 40k* MCLR

PIC12C5XX

VDD

This brown-out protection circuit employs

Microchip Technology’s MCP809 microcontroller

supervisor. The MCP8XX and MCP1XX f amil y of

super visors provide push-pull and open col lector

outputs with both high and low active reset pins.

There are 7 different trip point selections to

accomodate 5V and 3V systems.

MCLR

PIC12C5XX

VDD

Vss

RST

MCP809

VDD

bypass

capacitor

 1999 Microchip Technology Inc. DS40139E-page 45

PIC12C5XX

8.9 Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

8.9.1 SLEEP

The Power-Down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATU S<3>) is cleared and the oscillator dr iver is

turn ed off. The I/O p orts maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

It should be noted that a R ESET generated by a WDT

time-out does not drive the MCLR pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the GP3/

MCLR/VPP pin must be at a logic hig h level (VIHMC) if

MCLR is enabled.

8.9.2 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. An externa l reset input on GP3/MCLR /VPP pin,

when configured as MCLR.

2. A Watchdog Timer time-out reset (if WDT was

enabled).

3. A change on input pin GP0, GP1, or GP3/

MCLR/VPP when wake-up on change is

enabled.

These events cause a device reset. The TO, PD, and

GPWUF bits can be used to determine the cause of

device reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The GPWUF bit indicates a change in state while in

SLEEP at pins GP0, GP1, or GP3 (since the last time

there was a file or bit operation on GP port).

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

Caution: Right before entering SLEEP, read the

input pins. When in SLEEP, wake up

occurs when the values at the pins change

from the state they were in at the last

reading. If a wake-up on change occurs

and the pins are not read before

reentering SLEEP, a wake up will occur

immediately even if no pins change while

in SLEEP mode.

8.10 Program Verification/Code Protection

If the code protection bit has not been programmed,

the on-chip program memory can be read out for

verification purposes.

The first 64 l ocations can be read by the PIC12C5XX

regardless of the code protection bit se tting.

The last mem ory location cannot b e read if code pro-

tection is enabled on the PIC12C508/509.

The last memory location can be read regardless of the

code protection bit setting on the PIC12C508A/509A/

CR509A/CE518/CE519.

8.11 ID Locations

Four memory loca tions are design ated as I D loc ations

where the user can store checksum or other code-

identification numbers. These locations are not

accessible during normal execution but are readable

and writable during program/verify.

Use only the lower 4 bits of the ID locations and

always program the upper 8 bits as ’0’s.

PIC12C5XX

DS4013 9E -pag e 4 6  1999 Microchip Technology Inc.

8.12 In-Circuit Serial Programming

The PIC12C5XX microcontrollers with EPROM pro-

gram memory can be serially programmed while in the

end application circuit. This is simply done with two

lines for clock and data, and three other lines for power ,

ground, and the progr amming voltage. This allows cus-

tomers to manufacture boards with unprogrammed

devices, and then program the microcontroller just

before shipping the product. This also allows the mo st

recent firmware or a custom firmware to be pro-

grammed.

The device is placed into a program/verify mode by

holding the GP1 and GP0 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). GP1 becomes the programming clock

and GP0 becomes the programming data. Both GP1

and GP0 are Schmitt Trigger inputs in this mode.

After reset, a 6-bit command is then supplied to the

device. Depending on the command, 14-bits of pro-

gram data are then supplied to or from the device,

depending if the command was a load or a read. For

complete details of serial programming, please refer to

the PIC12C5XX Programming Specifications.

A typical in-circuit serial programming connection is

shown in Figure 8-16.

FIGURE 8-16: TY PICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC12C5XX

VDD

VSS

MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

 1999 Microchip Technology Inc. DS40139E-page 47

PIC12C5XX

9.0 INSTRUC TION SET SUMM ARY

Each PIC12C5XX instruction is a 12-bit word divided

into an OPCODE, wh ich specifies the instr uction type,

and one or more operands which further specify the

operation of the instruction. The PIC12C5XX

instruction set summary in Table 9-2 groups the

instructions into byte-oriented, bit-oriented, and literal

and control operations. Table 9-1 shows the opcode

field descriptions.

For byte-oriented instructions, ’f’ represents a file

designator. The file register designator is used to

specify which one of the 32 file regis ters is to be used

by the instruction.

The destination designator specifies where the result

of the operation is to be placed. If ’d’ is ’0’, the r esult is

placed in the W register. If ’d’ is ’1’, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ’b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ’f’ represents the number of the

file in which the bit is located.

For literal and control operations, ’k’ represents an

8 or 9-bit constant or literal value.

TABLE 9-1: OPCODE FIELD

DESCRIPTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

Don’t care location (= 0 or 1)

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility

with all Microchip software tools.

Destinati on sele ct;

d = 0 (store result in W)

d = 1 (store result in file register ’f’)

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counte r

WDT Watchdog Timer Counter

TO Time-Out bit

PD Power-Down bit

dest Destination, either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Register bit field

∈In the set of

talics

User defined term (font is courier)

All instr uctions are executed within a si ngle instr uct ion

cycle, unless a conditional test is true or the program

counter is change d as a result of an instr ucti on. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the nor mal

instruction e xecution time is 1 µs . If a conditional test is

true or the program counter is changed as a result of

an instruction, the instruction execution time is 2 µs.

Figure 9-1 shows the three general formats that the

instructions can have . All examples in the figure use the

following format to represent a hexadecimal number:

0xhhh

where ’h’ si gnifies a hexadecimal digit.

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

PIC12C5XX

DS4013 9E -pag e 4 8  1999 Microchip Technology Inc.

TABLE 9-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles

12-Bit Opcode Status

Affected NotesMSb LSb

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f,d

–

f, d

–

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f thr ough Carry

Rotate right f through Carry

Subtract W from f

Swap f

Exclusive OR W with f

1(2)

0001

0000

0010

0000

0010

0011

0001

0010

0000

0011

0000

0011

0001

11df

01df

011f

0100

01df

11df

10df

11df

00df

001f

0000

01df

00df

10df

ffff

0000

ffff

0000

ffff

C,DC,Z

None

C,DC,Z

None

1,2,4

2,4

1,4

2,4

1,2,4

2,4

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

0100

0101

0110

0111

bbbf

ffff

None

2,4

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

XORLW

–

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

1110

1001

0000

101k

1101

1100

0000

1000

0000

1111

kkkk

0000

kkkk

0000

kkkk

0000

kkkk

0100

kkkk

0010

kkkk

0011

0fff

kkkk

None

TO, PD

None

TO, PD

None

Note 1: The 9th bit of the program counter will be f orced to a ’ 0’ b y any instruction that writes to the PC e xcept for GOTO.

(Section 4.6)

2: When an I/O register is modified as a function of itself (e.g. MOVF GPIO, 1), the value used will be that value

present on the pins themselves . F or e xample, if the data latch is ’ 1’ for a pin configured as input and is driven

low by an external de vice, the data will be written back with a ’ 0’ .

3: The instruction TRI S f, where f = 6 causes the contents of the W register to be written to the tristate latches of

GPIO. A ’ 1’ forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is ex ecuted on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

 1999 Microchip Technology Inc. DS40139E-page 49

PIC12C5XX

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1 ]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 0001 11df ffff

Description: Add the contents of the W register and

in the W register. If ’d’ is ’1’ the result is

stored back in register ’f’.

Words: 1

Cycles: 1

Example: ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0xD9

FSR = 0xC2

ANDLW And literal with W

Syntax: [

label

] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W).AND. (k) → (W)

Status Affected: Z

Encoding: 1110 kkkk kkkk

Description: The contents of the W register are

AND’ed with the eight-bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: ANDLW 0x5F

Before Instruction

W= 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 0001 01df ffff

Description: The con t ent s of th e W re gi s te r ar e

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

'1' the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example: ANDWF FSR, 1

Before Instruction

W = 0x1 7

FSR = 0xC2

After Instruction

W = 0x17

FSR = 0x02

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 0100 bbbf ffff

Description: Bit 'b' in register 'f' is cleared.

Words: 1

Cycles: 1

Example: BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

PIC12C5XX

DS40139E-page 50  1999 Microchip Technology Inc.

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 0101 bbbf ffff

Description: Bit ’b’ in register ’f’ is set.

Words: 1

Cycles: 1

Example: BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 0110 bbbf ffff

Description: If bit ’b’ in register ’f’ is 0 then the next

instruction is skipped.

If bit ’b’ is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example: HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1>=0,

PC = address (TRUE);

if FLAG<1>=1,

PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 0111 bbbf ffff

Description: If bit ’b’ in register ’f’ is ’1’ then the next

instruction is skipped.

If bit ’b’ is ’1’, then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1

Cycles: 1(2)

Example: HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

Before Instruction

PC = add ress (HERE)

After Instruction

If FLAG<1> = 0,

PC = address (FALSE);

if FLAG<1>=1,

PC = address (TRUE)

 1999 Microchip Technology Inc. DS40139E-page 51

PIC12C5XX

CALL Subro utine Call

Syntax: [

label

] CALL k

Operands: 0 ≤ k ≤ 255

Operation: (PC) + 1→ Top of Stack;

k → PC<7:0>;

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: None

Encoding: 1001 kkkk kkkk

Description: Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS< 6:5>, PC< 8> is cleared . CALL is

a two cycle instruction.

Words: 1

Cycles: 2

Example: HERE CALL THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 1)

CLRF Clear f

Syntax: [

label

] CLRF f

Operands: 0 ≤ f ≤ 31

Operation: 00h → (f);

1 → Z

Status Affected: Z

Encoding: 0000 011f ffff

Description: The contents of register ’f’ are cleared

and the Z bit is set.

Words: 1

Cycles: 1

Example: CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00

Z=1

CLRW Clear W

Syntax: [

label

] CLRW

Operands: None

Operation: 00h → (W);

1 → Z

Status Affected: Z

Encoding: 0000 0100 0000

Description: The W register is cleared. Zero bit (Z)

is set.

Words: 1

Cycles: 1

Example: CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

Status Affected: TO, PD

Encoding: 0000 0000 0100

Description: The CLRWDT instruction resets the

WDT. It also resets the prescaler, if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Words: 1

Cycles: 1

Example: CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescale = 0

TO =1

PD =1

PIC12C5XX

DS40139E-page 52  1999 Microchip Technology Inc.

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 0010 01df ffff

Description: The contents of register ’f’ are comple-

mented. If ’d’ is 0 the result is stored in

the W register. If ’d’ is 1 the result is

stored back in register ’f’.

Words: 1

Cycles: 1

Example: COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – 1 → (dest)

Status Affected: Z

Encoding: 0000 11df ffff

Description: Decrement register ’f’. If ’d’ is 0 the

resul t i s st ore d in the W regi st er. If ’ d ’ is

1 the result is stored back in register ’f’.

Words: 1

Cycles: 1

Example: DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – 1 → d; skip if result = 0

Status Affected: None

Encoding: 0010 11df ffff

Description: The contents of register ’f’ are decre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words: 1

Cycles: 1(2)

Example: HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT - 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT ≠0,

PC = address (HERE+1)

GOTO Unconditional Branch

Syntax: [

label

] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

Encoding: 101k kkkk kkkk

Description: GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS <6:5> . GOTO is a

two cycle instruction.

Words: 1

Cycles: 2

Example: GOTO THERE

After Instruction

PC = address (THERE)

 1999 Microchip Technology Inc. DS40139E-page 53

PIC12C5XX

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 0010 10df ffff

Description: The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

Words: 1

Cycles: 1

Example: INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 0011 11df ffff

Description: The contents of register ’f’ are incre-

mented. If ’d’ is 0 the result is placed in

the W register. If ’d’ is 1 the result is

placed back in register ’f’.

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

Words: 1

Cycles: 1(2)

Example: HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1;

if CNT = 0,

PC = address (CONTINUE);

if CNT ≠0,

PC = address (HERE +1)

IORLW Inclusive OR literal with W

Syntax: [

label

] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. (k) → (W)

Status Affected: Z

Encoding: 1101 kkkk kkkk

Description: The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W= 0xBF

Z=0

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W).OR. (f) → (dest)

Status Affected: Z

Encoding: 0001 00df ffff

Description: Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1

Cycles: 1

Example: IORWF RESULT, 0

Before Instruction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=0

PIC12C5XX

DS40139E-page 54  1999 Microchip Technology Inc.

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 0010 00df ffff

Description: The contents of register ’f’ is moved to

destination ’d’. If ’d ’ is 0, destination is

the W register. If ’d’ is 1, the destination

is file register ’f’. ’d’ is 1 is useful to test

a file register since status flag Z is

affected.

Words: 1

Cycles: 1

Example: MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 1100 kkkk kkkk

Description: The ei g ht bi t l i t eral ’k ’ is lo ad ed i nt o t he

W register . The don’t cares will assem-

ble as 0s.

Words: 1

Cycles: 1

Example: MOVLW 0x5A

After Instruction

W= 0x5A

MOVWF M ove W to f

Syntax: [

label

] MOVWF f

Operands: 0 ≤ f ≤ 31

Operation: (W) → (f)

Status Affected: None

Encoding: 0000 001f ffff

Description: Move data from the W register to regis-

ter 'f'.

Words: 1

Cycles: 1

Example: MOVWF TEMP_REG

Before Instruction

TEMP_REG = 0xFF

W = 0x4F

After Instruction

TEMP_REG = 0x4F

W = 0x4F

NOP No Operation

Syntax: [

label

] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 0000 0000 0000

Description: No operation.

Words: 1

Cycles: 1

Example: NOP

 1999 Microchip Technology Inc. DS40139E-page 55

PIC12C5XX

OPTION Load OPTION Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 0000 0000 0010

Description: The content of the W register is loaded

into the OPTION register.

Words: 1

Cycles: 1

Example OPTION

Before Instruction

W=0x07

After Instruction

OPTION = 0x07

RETLW Return with Literal in W

Syntax: [

label

] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 1000 kkkk kkkk

Description: The W register is loaded with the eight

bit literal ’k’. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W= 0x07

After Instruction

W= value of k8

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 0011 01df ffff

Description: The contents of register ’f’ are rotated

one bit to the left through the Carry

Flag. If ’d’ is 0 the result is placed in the

W register. If ’d’ is 1 the result is stored

back in register ’f’.

Words: 1

Cycles: 1

Example: RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 0011 00df ffff

Description: The contents of register ’f’ are rotated

one bit to the right through the Carry

Flag. If ’d’ is 0 the result is placed in the

W regi s t er. If ’d’ is 1 th e r e su l t i s p l ac ed

back in register ’f’.

Words: 1

Cycles: 1

Example: RRF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W=0111 0011

C=0

Cregister ’f’

PIC12C5XX

DS40139E-page 56  1999 Microchip Technology Inc.

SLEEP Enter SLEEP Mode

Syntax: [

label

]SLEEP

Operands: None

Operation: 00h → WDT;

0 → WDT prescaler;

1 → TO;

0 → PD

Status Affected: TO, PD, GPWUF

Encoding: 0000 0000 0011

Description: Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

GPWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into SLEEP mode

with the oscilla tor stop pe d. See sec-

tion on SLEEP for more details.

Words: 1

Cycles: 1

Example: SLEEP

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f) – (W) → (dest)

Status Affected: C, DC, Z

Encoding: 0000 10df ffff

Description: Subtract (2’s complement method) the

W re gi s te r f r om r eg i st e r 'f '. If 'd' i s 0 t h e

resul t i s st ore d in t he W r egi st er. If ' d' i s

1 the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example 1:SUBWF REG1, 1

Before Instruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1 ; result is positive

Example 2:

Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1 ; result is zero

Example 3:

Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = FF

W=2

C = 0 ; result is negative

 1999 Microchip Technology Inc. DS40139E-page 57

PIC12C5XX

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: 0011 10df ffff

Description: The upper and lower nibbles of register

’f’ are e xchanged. If ’d’ is 0 the result is

placed in W register. If ’ d’ is 1 the result

is placed in register ’f’.

Words: 1

Cycles: 1

Example SWAPF REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0X5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: f = 6

Operation: (W) → TRIS register f

Status Affected: None

Encoding: 0000 0000 0fff

Description: TRI S re gis ter ’ f’ (f = 6) is l oad ed w it h th e

contents of the W register

Words: 1

Cycles: 1

Example TRIS GPIO

Before Instruction

W=0XA5

After Instruction

TRIS = 0XA5

Note: f = 6 for PIC12C5XX only.

XORLW Exclusive OR literal with W

Syntax: [

label

]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 1111 kkkk kkkk

Description: The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W= 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 0001 10df ffff

Description: Exclusive OR the contents of the W

resul t i s st ore d in t he W r egi st er. If ' d' i s

1 the result is stored back in register 'f'.

Words: 1

Cycles: 1

Example XORWF REG,1

Before Instruction

REG = 0xAF

W=0xB5

After Instruction

REG = 0x1A

W=0xB5

PIC12C5XX

DS40139E-page 58  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 59

PIC12C5XX

10.0 DEVELOPMENT SUPPORT

10.1 Development Tools

The PICmicro microcontrollers are supported with a

full range of hardware and software dev elopment tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

•PRO MATE

 II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

• SIMICE

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

•MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzz y Lo gic Develo pm en t Sy st em

(

fuzzy

TECH−MP)

•K

EELOQ® Evaluation Kits and Programmer

10.2 MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is

intended t o provide the pr oduct development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). MPLAB-ICE is

supplied with the MPLAB Integrated Development

Environment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

Interchangeable processor modules allow the system

to be easily reconfig ured for emulation of different pro-

cessors. The universal architectur e of the M PLAB-ICE

allows expansion to suppor t all new Microchip micro-

controllers.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive de vel-

opment tools. The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE is available in two versions.

MPLAB-ICE 1000 is a basic, low-cost emulator system

with simple trace capabilities. It shares processor mod-

ules with the MPLAB-ICE 200 0. This is a full-featu red

emulator system with enhanced trace, trigger , and data

monitori ng fea tures. Both systems will operate across

the entire operating speed range of the PICmicro

MCU.

10.3 ICEPIC: Low-Cost PICmicro

In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dows NT environment. ICEPIC features real time, non-

intrusive emulation.

10.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD di splay for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to suppor t various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

gram PIC12CXXX, PIC14C000, PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

configuration and code-protect bits in this mode.

10.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efficient. PICST AR T Plus is not

recommended for production programming.

PICSTART Pl us supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

por ted with an adapter socket. PICSTART Plus is CE

compliant.

PIC12C5XX

DS4013 9E -pag e 6 0  1999 Microchip Technology Inc.

10.6 SIMICE Entry-Level Hardware

Simulator

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) software. Specifically, SIMICE provides hardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC16C5X families of PICmicro 8-bit microcon-

trollers. SIMICE works in conjunction with MPLAB-SIM

to provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

files. SIMICE is a valuable debugging tool for entry-

level system development.

10.7 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 i s a simple boa rd which demo nstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and downlo ad t h e

firmware to the emulator for testing. Additional proto-

type area i s available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

10.8 PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sa mpl e micr ocon tro lle rs prov ided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTAR T-Plus, and easily test firmware.

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test firmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the f eatures include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of the I2C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.9 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microc on tro l ler s w ith a LCD Modu l e . Al l th e nec e s-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcon troller sock et(s). So me of th e fea tur es inc lude

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a ke ypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-2 32 interface and Windows 3.1 software for

showing the demultiplex ed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

 1999 Microchip Technology Inc. DS40139E-page 61

PIC12C5XX

10.10 MPLAB Integrated Development

Environment Software

The MPLAB IDE Software brings an ea se of software

development previously unsee n in the 8-bit microc on-

troller mar ket. MPLAB is a windows based appli cation

which conta ins:

• A full featured editor

• Three operating modes

-editor

-emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source files

- absolute lis ting file

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

10.11 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and sev eral source and listing f ormats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

MPASM has the following features to assist in develop-

ing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful

in making the development of your assemble source

code shorter and more maintainable.

10.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pin s. The input/

output radix can be set by the user and the execution

can be performed in; single step, e xecute until break, or

in a trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

offers the low cost flexibility to dev elop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

10.13 MPLAB-C17 Compiler

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment environment for Microchip’ s PIC17CXXX family of

microcontrolle rs. The compi ler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

10.14 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems.

Both versions include Mi crochip’s

fuzzy

LAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

10.15 SEEVAL Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wi re and 3-wire Serial EEPROMs. The kit

includes everything neces sary to r ead, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

significantly reduce time-to-market and result in an

optimized system.

PIC12C5XX

DS4013 9E -pag e 6 2  1999 Microchip Technology Inc.

10.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS ev al-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

 1999 Microchip Technology Inc. DS40139E-page 63

PIC12C5XX

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulator Products

MPLAB™-ICE

ICEPIC Low-Cost

In-Circuit Emulator

Software Tools

MPLAB

Integrated

Development

Environment

MPLAB C17*

Compiler

fuzzy

TECH-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

Total Endurance

Software Model

Programmers

PICSTARTPlus

Low-Cost

Universal Dev. Kit

PRO MATE II

Universal

Programmer

KEELOQ

Programmer

Demo Boards

SEEVAL

Designers Kit

SIMICE

PICDEM-14A

PICDEM-1

PICDEM-2

PICDEM-3

KEELOQ®

Evaluation Kit

KEELOQ

Transponder Kit

PIC12C5XX

DS4013 9E -pag e 6 4  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 65

PIC12C5XX

11.0 ELECTRICAL CHARACTERISTICS - PIC12C508/PIC12C509

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–40°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ................ .................................................................................................0 to +7.5 V

Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V

Voltage on all other pins with respect to VSS ............................................................................... –0.6 V to (VDD + 0.6 V)

Total Power Dissipation(1) ....................................................................................................................................700 mW

Max. Current out of VSS pin ......................................... .........................................................................................200 mA

Max. Current into VDD p in .....................................................................................................................................150 mA

Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output Clamp Current, IOK (VO < 0 or VO > VDD).............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................25 mA

Max. Output Current sourced by I/O port (GPIO) ......................................................................................... ........100 mA

Max. Output Current sunk by I/O port (GPIO )......................................................................................................100 mA

Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

†NOTICE: Stresses above those listed under "Maximum Ratings" may cause permane nt damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC12C5XX

DS4013 9E -pag e 6 6  1999 Microchip Technology Inc.

11.1 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Parm

No. Characteristic Sym Min Typ(1) Max Units Conditions

D001 Supply Voltage VDD 2.5

3.0

5.5

FOSC = DC to 4 MHz ( Commercial/

Industrial)

FOSC = DC to 4 MHz (Extended)

D002 RAM Data Retention

Voltage(2) VDR 1.5* V Device in SLEEP mode

D003 VDD Star t Voltage to

ensure Power-on Reset VPOR VSS V See section on Power-on Reset for details

D004 VDD Rise Rate to ensure

Power-on Reset SVDD 0.05

*V/ms See section on Power-on Reset for details

D010

D010C

D010A

Supply Current(3) IDD —

—

.78

1.1

2.4

µA

XT and EXTRC options (4)

FOSC = 4 MHz, VDD = 5.5V

INTRC Op tion

FOSC = 4 MHz, VDD = 5.5V

LP OPTION, Commercial Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

LP OPTION, Industrial Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

LP OPTION, Extended Temperature

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D020

D021

D021B

Power-Down Current (5) IPD —

—

0.25

µA

VDD = 3.0V, Commercial WDT disabled

VDD = 3.0V, Industrial WDT disabled

VDD = 3.0V, Extended WDT disabled

D022 ∆IWDT —

—

3.75

µA

VDD = 3.0V, Commercial

VDD = 3.0V, Industrial

VDD = 3.0V, Extended

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as

bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an

impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current

is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or

VSS.

 1999 Microchip Technology Inc. DS40139E-page 67

PIC12C5XX

11.2 DC CHARACTERISTICS: PIC12C508/509 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating voltage VDD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No. Characteristic Sym Min Typ† Max Units Conditions

Input Low Voltage

I/O ports VIL -

D030 with TTL buffer VSS -0.8VV4.5 < VDD ≤ 5.5V

-0.15V

DD Votherwise

D031 with Sc hmitt Trigger buffer VSS -0.15VDD V

D032 MCLR, GP2/T0CKI (in EXTRC mode) VSS -0.15VDD V

D033 OSC1 (EXTRC) (1) VSS -0.15VDD

D033 OSC1 (in XT and LP) VSS -0.3VDD VNote1

Input High Voltage

I/O ports VIH -

D040 with TTL buffer VSS 2.0V - VDD V4.5 ≤ VDD ≤ 5.5V

D040A 0.25VDD +

0.8V -VDD Votherwise

D041 with Sc hmitt Trigger buffer 0.85VDD -VDD V For entire VDD range

D042 MCLR/GP2/T0CKI 0.85VDD -VDD V

D042A O SC1 (XT and LP) 0.7VDD -VDD VNote1

D043 OSC1 (in EXTRC mode) 0.85VDD -VDD V

D070 GPIO weak pull-up cur rent IPUR 50 250 400 µAVDD = 5V, VPIN = VSS

Input Leakage Current (2, 3) For V DD ≤5.5V

D060 I/O ports IIL -1 0.5 +1µA Vss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR, GP2/T0CKI 20 130

0.5 250

+5 µA

µAVPIN = VSS + 0.25V(2)

VPIN = VDD

D063 OSC1 -3 0.5 +3 µA Vss ≤ VPIN ≤ VDD,

XT and LP options

Output Low Voltage

D080 I/O ports/CLKOUT VOL --0.6VIOL = 8.7 mA, VDD = 4.5V

Output High Voltage

D090 I/O ports/CLKOUT (3) VOH VDD - 0.7--VIOH = -5.4 mA, VDD = 4.5V

Capacitive Loading Specs on

Output Pins

D100 OSC2 pin COSC2 - - 15 pF In XT and LP modes when

external clock is used to drive

OSC1.

D101 All I/O pins CIO - - 50 pF

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that

the PIC12C5XX be driven with exter nal clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

PIC12C5XX

DS4013 9E -pag e 6 8  1999 Microchip Technology Inc.

TABLE 11-1: PULL-UP RESISTOR RANGES - PIC12C508/C509

VDD (Volts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 38K 42K 63K Ω

25 42K 48K 63K Ω

85 42K 49K 63K Ω

125 50K 55K 63K Ω

5.5 –40 15K 17K 20K Ω

25 18K 20K 23K Ω

85 19K 22K 25K Ω

125 22K 24K 28K Ω

GP3

2.5 –40 285K 346K 417K Ω

25 343K 414K 532K Ω

85 368K 457K 532K Ω

125 431K 504K 593K Ω

5.5 –40 247K 292K 360K Ω

25 288K 341K 437K Ω

85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

 1999 Microchip Technology Inc. DS40139E-page 69

PIC12C5XX

11.3 Timing Parameter Symbology and Load Conditions - PIC12C508/C509

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time

Lowercase subscripts (pp) and their meanings:

2to mcMCLR

ck CLKOUT osc oscillator

cy cycle time os OSC1

drt device reset timer t0 T0CKI

io I/O po rt wdt watchdog timer

Uppercase letters and their meanings:

F Fall P Period

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

FIGURE 11-1: LOAD CONDITIONS - PIC12C508/C509

VSS

Pin CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT or LP

modes when external clock

is used to drive OSC1

PIC12C5XX

DS4013 9E -pag e 7 0  1999 Microchip Technology Inc.

11.4 Timing Diagrams and Specifications

FIGURE 11-2: EXTERNAL CLOCK TIMING - PIC12C508/C509

TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

FOSC External CLKIN Frequency(2)

DC — 4 MHz XT osc mode

DC — 200 kHz LP osc mode

Oscillator Frequency(2)

0.1 — 4 MHz XT osc mode

DC — 200 kHz LP osc mode

OSC External CLKIN Period(2) 250 — — ns EXTRC osc mode

250 — — ns XT osc mode

5 — — ms LP osc mode

Oscillator Period(2) 250 — — ns EXTRC osc mode

250 — 10,000 ns XT osc mode

5 — — ms LP osc mode

2Tcy

Instruction Cycle Time(3) —4/FOSC ——

3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

2* — — ms LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

— — 50* ns LP oscillator

* These paramet ers are charact er ized but not tested .

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these specified limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input osc illator time base period.

OSC1

Q4 Q1 Q2 Q3 Q4 Q1

133

 1999 Microchip Technology Inc. DS40139E-page 71

PIC12C5XX

TABLE 11-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509

FIGURE 11-3: I/O TIMING - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1

Parameter

No. Sym Characteristic Min* Typ(1) Max* Units Conditions

Internal Calibrated RC Frequency 3.58 4.00 4.32 MHz VDD = 5.0V

Internal Calibrated RC Frequency 3.50 —4.26MHzV

DD = 2.5V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

OSC1

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

20, 21

Old Value New Value

Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

PIC12C5XX

DS4013 9E -pag e 7 2  1999 Microchip Technology Inc.

TABLE 11-4: TIMING REQUIREMENTS - PIC12C508/C509

FIGURE 11-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

No. Sym Characteristic Min Typ(1) Max Units

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(3) — — 100* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) TBD — — ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setu p time) TBD — — ns

20 TioR Port output rise time(2, 3) —1025**ns

21 TioF Port output fall time(2, 3) —1025**ns

* These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 1 1-1 for loading conditions.

VDD

MCLR

Internal

POR

DRT

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O pin

32 32

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

(Note 2)

2: Runs in MCLR or WDT reset only in XT and LP modes.

 1999 Microchip Technology Inc. DS40139E-page 73

PIC12C5XX

TABLE 11-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC12C508/C509

TABLE 11-6: DRT (DEVICE RESET TIMER PERIOD - PIC12C508/C509)

AC Characteristic s Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V

31 Twdt Watchdog Timer Time-out Period

(No Prescaler) 9* 18* 30* ms VDD = 5 V (Commercial)

32 TDRT Device Reset Timer Period(2) 9* 18* 30* ms VDD = 5 V (Commercial)

34 TioZ I/O Hi-impedance from MCLR Low — — 2000* ns

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 2: See Table 11-6.

Oscillator Configuration POR Reset Subsequent Resets

IntRC & ExtRC 18 ms (typical) 300 µs (typical)

XT & LP 18 ms (typical) 18 ms (typical)

PIC12C5XX

DS4013 9E -pag e 7 4  1999 Microchip Technology Inc.

FIGURE 11-5: TIMER0 CLOCK TIMINGS - PIC12C508/C509

TABLE 11-7: TIMER0 CLOCK REQUIREMENTS - PIC12C508/C509

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 11.1.

Parameter

No. Sym Characteristic Min Typ(1) Max Units Conditions

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* ——ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — n s

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

N — — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

T0CKI

40 41

 1999 Microchip Technology Inc. DS40139E-page 75

PIC12C5XX

12.0 DC AND AC CHARACTERISTICS - PIC12C 508/PIC12C509

The graphs and tables provided in this section are fo r design guidance and are not tested. In some graphs or tables

the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information

only and devices will operate properly only within the specified range.

The data presented i n this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” repr esents the mean of the distr ibution w hile “max” or “mi n” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 12-1: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

TEMPERATURE (VDD = 2.5V)

4.50

4.10

4.00

3.90

3.80

3.70

3.60

-40 25 85 125

Temperature (Deg.C)

Frequency (MHz)

Min.

Max.

4.40

4.30

4.20

3.50

FIGURE 12-2: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

TEMPERATURE (VDD = 5.0V)

4.50

4.10

4.00

3.90

3.80

3.70

3.60

-40 25 85 125

Temperature (Deg.C)

Frequency (MHz)

Min.

Max.

4.40

4.30

4.20

3.50

PIC12C5XX

DS40139E-page 76  1999 Microchip Technology Inc.

TABLE 12-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator Frequency VDD = 2.5V VDD = 5.5V

External RC 4 MHz 250 µA* 780 µA*

Internal RC 4 MHz 420 µA 1.1 mA

XT 4 MHz 251 µA 780 µA

LP 32 KHz 15 µA 37 µA

*Does not include current through external R&C.

FIGURE 12-3: WDT TIMER TIME-OUT

PERIOD VS. VDD

5234567

VDD (Volts)

WDT period (m S)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

FIGURE 12-4: SHORT DRT PERIOD VS. VDD

1000

900

800

700

600

500

400

300

200

100234567

VDD (Volts)

WDT period (µs)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

 1999 Microchip Technology Inc. DS40139E-page 77

PIC12C5XX

FIGURE 12-5: IOH vs. VOH, VDD = 2.5 V

FIGURE 12-6: IOH vs. VOH, VDD = 5.5 V

500m 1.0 1.5

VOH (Volts)

IOH (mA)

2.0 2.5

-1

-2

-3

-4

-5

-6

-7

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

3.5 4.0 4.5

VOH (Vo l ts )

IOH (mA)

5.0 5.5

-5

-10

-15

-20

-25

-30

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

FIGURE 12-7: IOL vs. VOL, VDD = 2.5 V

FIGURE 12-8: IOL vs. VOL, VDD = 5.5 V

0250.0m 500.0m 1.0

VOL (Volts)

IOL (mA)

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

0500.0m 750.0m 1.0

VOL (Volts)

IOL (mA)

250.0m

Min +85°C

Max –40°C

Typ +25°C

Min +125°C

PIC12C5XX

DS40139E-page 78  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS40139E-page 79

PIC12C5XX

13.0 ELECTRICAL CHARACTERISTICS - PIC12C508A/PIC12C509A/

PIC12LC508A/PIC12LC509A/PIC12CR509A/PIC12CE518/PIC12CE519/

PIC12LCE518/PIC12LCE519/PIC12LCR509A

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–40°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ................ .................................................................................................0 to +7.0 V

Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V

Voltage on all other pins with respect to VSS ............................................................................... –0.3 V to (VDD + 0.3 V)