IRFP2907Z - International Rectifier

IRFP2907Z

HEXFET® Power MOSFET

VDSS = 75V

RDS(on) = 4.5mΩ

ID = 90A

06/17/04

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AUTOMOTIVE MOSFET

HEXFET® is a registered trademark of International Rectifier.

Description

Specifically designed for Automotive applications,

this HEXFET® Power MOSFET utilizes the latest

processing techniques to achieve extremely low

on-resistance per silicon area. Additional features

of this design are a 175°C junction operating

temperature, fast switching speed and improved

repetitive avalanche rating . These features com-

bine to make this design an extremely efficient

and reliable device for use in Automotive applica-

tions and a wide variety of other applications.

Features

lAdvanced Process Technology

lUltra Low On-Resistance

l175°C Operating Temperature

lFast Switching

lRepetitive Avalanche Allowed up to Tjmax

PD - 95873

TO-247AC

Absolute Maximum Ratings

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9)

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)

IDM Pulsed Drain Current

PD @TC = 25°C Maximum Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

EAS Single Pulse Avalanche Energy (Thermally Limited)

EAS (tested) Single Pulse Avalanche Energy Tested Value

IAR Avalanche Current

EAR Repetitive Avalanche Energy

TJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

Mounting torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case

––– 0.49 °C/W

RθCS Case-to-Sink, Flat, Greased Surface

j

0.24 –––

RθJA Junction-to-Ambient

––– 40

Max.

170

120

680

10 lbf•in (1.1N•m)

310

2.0

± 20

520

690

See Fig.12a,12b,15,16

300 (1.6mm from case )

-55 to + 175

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Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C,

L=0.13mH, RG = 25Ω, IAS = 90A, VGS =10V.

Part not recommended for use above this value.

ISD ≤ 90A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

Coss eff. is a fixed capacitance that gives the same

charging time as Coss while VDS is rising from 0 to 80% VDSS.

Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive

avalanche performance.

This value determined from sample failure population. 100%

tested to this value in production.

Rθ is measured at TJ of approximately 90°C.

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. T

p. Max. Units

V(BR)DSS Drain-to-Source Breakdown Volta

e75––––––V

∆ΒVDSS

∆TJ Breakdown Volta

e Temp. Coefficient ––– 0.069 ––– V/°C

RDS(on) Static Drain-to-Source On-Resistance ––– 3.5 4.5 mΩ

VGS(th) Gate Threshold Volta

e2.0–––4.0V

fs Forward Transconductance 180 ––– ––– S

IDSS Drain-to-Source Leaka

e Current ––– ––– 20

––– ––– 250

IGSS Gate-to-Source Forward Leaka

e ––– ––– 200 nA

Gate-to-Source Reverse Leaka

e ––– ––– -200

QgTotal Gate Char

e ––– 180 270

Qgs Gate-to-Source Char

e ––– 46 ––– nC

Qgd Gate-to-Drain ("Miller") Char

e ––– 65 –––

td(on) Turn-On Dela

Time –––19–––ns

trRise Time ––– 140 –––

td(off) Turn-Off Dela

Time –––97–––

tfFall Time ––– 100 –––

LDInternal Drain Inductance ––– 5.0 ––– nH Between lead,

6mm (0.25in.)

LSInternal Source Inductance ––– 13 ––– from packa

and center of die contact

Ciss Input Capacitance ––– 7500 ––– pF

Coss Output Capacitance ––– 970 –––

Crss Reverse Transfer Capacitance ––– 510 –––

Coss Output Capacitance ––– 3640 –––

Coss Output Capacitance ––– 650 –––

Coss eff. Effective Output Capacitance ––– 1020 –––

Diode Characteristics

Parameter Min. T

p. Max. Units

ISContinuous Source Current ––– ––– 90

(Body Diode) A

ISM Pulsed Source Current ––– ––– 680

(

Bod

Diode

)

c

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time –––4161ns

Qrr Reverse Recover

Char

e ––– 59 89 nC

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

RG = 2.5Ω

ID = 90A

VDS = 25V, ID = 90A

VDD = 38V

ID = 90A

VGS = 20V

VGS = -20V

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 10V

MOSFET symbol

VGS = 0V

VDS = 25V

VGS = 0V, VDS = 60V, ƒ = 1.0MHz

Conditions

VGS = 0V, VDS = 0V to 60V

ƒ = 1.0MHz, See Fig. 5

TJ = 25°C, IF = 90A, VDD = 38V

di/dt = 100A/

TJ = 25°C, IS = 90A, VGS = 0V

showing the

integral reverse

p-n junction diode.

VDS = 60V

VGS = 10V

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 90A

VDS = VGS, ID = 250µA

VDS = 75V, VGS = 0V

VDS = 75V, VGS = 0V, TJ = 125°C

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Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

≤60µs PULSE WIDTH

Tj = 25°C

4.5V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

ID, Drain-to-Source Current (A)

4.5V

≤60µs PULSE WIDTH

Tj = 175°C

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

2 4 6 8 10

VGS, Gate-to-Source Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current (Α)

TJ = 25°C

TJ = 175°C

VDS = 25V

≤60µs PULSE WIDTH

0 25 50 75 100 125 150

ID,Drain-to-Source Current (A)

100

150

200

Gfs, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C, Capacitance(pF)

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, C ds SHORTED

Crss = Cgd

Coss = Cds + Cgd

Coss

Crss

Ciss

0 50 100 150 200

QG Total Gate Charge (nC)

0.0

2.0

4.0

6.0

8.0

10.0

12.0

VGS, Gate-to-Source Voltage (V)

VDS= 60V

VDS= 38V

VDS= 15V

ID= 90A

0.0 0.5 1.0 1.5 2.0 2.5

VSD, Source-to-Drain Voltage (V)

100

1000

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

1 10 100 1000

VDS, Drain-to-Source Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY R DS(on)

100µsec

Tc = 25°C

Tj = 175°C

Single Pulse

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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 10. Normalized On-Resistance

vs. Temperature

25 50 75 100 125 150 175

TC , Case Temperature (°C)

100

125

150

175

ID, Drain Current (A)

Limited By Package

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 90A

VGS = 10V

1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

Thermal Response ( Z thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W) τi (sec)

0.1224 0.000360

0.1238 0.001463

0.2433 0.021388

τJ

τ1

τ2

τ2τ3

τ3

R1R2

R2R3

τC

Ci i/Ri

Ci= τi/Ri

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QGS QGD

Charge

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

VCC

DUT

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

500

1000

1500

2000

2500

EAS , Single Pulse Avalanche Energy (mJ)

TOP 16A

25A

BOTTOM 90A

-75 -50 -25 025 50 75 100 125 150 175 200

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

VGS(th) Gate threshold Voltage (V)

ID = 250µA

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Fig 15. Typical Avalanche Current Vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

100

1000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

100

200

300

400

500

600

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 90A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* V

GS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



VDS

90%

10%

VGS

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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Data and specifications subject to change without notice.

This product has been designed and qualified for the Automotive [Q101] market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 06/04

TO-247AC package is not recommended for Surface Mount Application.

TO-247AC Package Outline

Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

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Note: "P" in assembly line

position indicates "Lead-Free"

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Note: For the most current drawings please refer to the IR website at:

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