Absolute Maximum Ratings
Parameter Units
ID @ VGS = 10V, TC = 25°C Continuous Drain Current 4.5
ID @ VGS = 10V, TC = 100°C Continuous Drain Current 2.8
IDM Pulsed Drain Current 18
PD @ TC = 25°C Max. Power Dissipation 14 W
Linear Derating Factor 0.11 W/°C
VGS Gate-to-Source Voltage ±20 V
EAS Single Pulse Avalanche Energy 0.242 mJ
IAR Avalanche Current 2.2 A
EAR Repetitive Avalanche Energy 1.4 mJ
dv/dt Peak Diode Recovery dv/dt 5.5 V/ns
TJOperating Junction -55 to 150
TSTG Storage Temperature Range
Pckg. Mounting Surface Temp. 300 (for 5s)
Weight 0.42(typical) g
The leadless chip carrier (LCC) package represents the
logical next step in the continual evolution of surface
mount technology. Desinged to be a close replacement
for the TO-39 package, the LCC will give designers the
extra flexibility they need to increase circuit board density.
International Rectifier has engineered the LCC package
to meet the specific needs of the power market by
increasing the size of the bottom source pad, thereby
enhancing the thermal and electrical performance. The
lid of the package is grounded to the source to reduce
RF interference.
°C
A
08/03/07
www.irf.com 1
Product Summary
Part Number BVDSS RDS(on) ID
IRFE120 100V 0.30 4.5A
Features:
nSurface Mount
nSmall Footprint
nAlternative to TO-39 Package
nHermetically Sealed
nDynamic dv/dt Rating
nAvalanche Energy Rating
nSimple Drive Requirements
nLight Weight
For footnotes refer to the last page
REPETITIVE AVALANCHE AND dv/dt RATED
HEXFET®TRANSISTORS
SURFACE MOUNT (LCC-18)
IRFE120
JANTX2N6788U
REF:MIL-PRF-19500/555
100V, N-CHANNEL
LCC-18
PD - 93983A
IRFE120, JANTX2N6788U
2www.irf.com
For footnotes refer to the last page
Note: Corresponding Spice and Saber models are available on International Rectifier Website.
Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified)
Parameter Min Typ Max Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage 100 V VGS = 0V, ID = 1.0mA
BVDSS/TJTemperature Coefficient of Breakdown 0.10 V/°C Reference to 25°C, ID = 1.0mA
Voltage
RDS(on) Static Drain-to-Source On-State 0.30 VGS = 10V, ID = 2.8A
Resistance 0.35 VGS = 10V, ID = 4.5A
VGS(th) Gate Threshold Voltage 2.0 — 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 1.5 — — S VDS > 15V, IDS = 2.8A
IDSS Zero Gate Voltage Drain Current 25 VDS = 80V, VGS = 0V
250 VDS = 80V
VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Leakage Forward 100 VGS = 20V
I
GSS Gate-to-Source Leakage Reverse -100 VGS = -20V
QgTotal Gate Charge 18 VGS = 10V, ID = 4.5A
Qgs Gate-to-Source Charge 4.0 nC VDS = 50V
Qgd Gate-to-Drain (‘Miller’) Charge 9.0
td(on) Turn-On Delay Time 40 VDD = 35V, ID = 4.5A
trRise Time 70 VGS = 10V, RG = 7.5
td(off) Turn-Off Delay Time 40
tfFall Time 70
LS + LDTotal Inductance 6.1
Ciss Input Capacitance 350 VGS = 0V, VDS = 25V
Coss Output Capacitance 150 pF f = 1.0MHz
Crss Reverse Transfer Capacitance 24
nA
nH
ns
µA
Measured from the center of
drain pad to center of source
pad
Thermal Resistance
Parameter Min Typ Max Units Test Conditions
RthJC Junction to Case 8.93
RthJ-PCB Junction to PC Board 26 Soldered to a copper clad PC board
°C/W
Source-Drain Diode Ratings and Characteristics
Parameter Min Typ Max Units Test Conditions
ISContinuous Source Current (Body Diode) 4.5
ISM Pulse Source Current (Body Diode) —— 18
VSD Diode Forward Voltage 1.8 V Tj = 25°C, IS = 4.5A, VGS = 0V
trr Reverse Recovery Time 240 ns Tj = 25°C, IF = 4.5A, di/dt 100A/µs
QRR Reverse Recovery Charge 2.0 µC VDD 50V
ton Forward Turn-On Time Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
A
www.irf.com 3
IRFE120, JANTX2N6788U
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
IRFE120, JANTX2N6788U
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
13 a & b
www.irf.com 5
IRFE120, JANTX2N6788U
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width 1 µs
Duty Factor 0.1 %
RD
VGS
RG
D.U.T.
VGS
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
IRFE120, JANTX2N6788U
6www.irf.com
QG
QGS QGD
VG
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
www.irf.com 7
IRFE120, JANTX2N6788U
Foot Notes:
ISD 4.5A, di/dt 110A/µs, VDD 100V, TJ 150°C
Suggested RG =7.5
Pulse width 300 µs; Duty Cycle 2%
Repetitive Rating; Pulse width limited by
maximum junction temperature.
VDD = 25V, starting TJ = 25°C,
Peak IL = 2.2A, L = 100µH
Case Outline and Dimensions — LCC-18
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/2007