PD - 93983A REPETITIVE AVALANCHE AND dv/dt RATED (R) HEXFET TRANSISTORS SURFACE MOUNT (LCC-18) IRFE120 JANTX2N6788U REF:MIL-PRF-19500/555 100V, N-CHANNEL Product Summary Part Number BVDSS RDS(on) ID IRFE120 100V 0.30 4.5A LCC-18 The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. Features: n n n n n n n n Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight Absolute Maximum Ratings Parameter ID @ VGS = 10V, TC = 25C ID @ VGS = 10V, TC = 100C IDM PD @ TC = 25C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight Units 4.5 2.8 18 14 0.11 20 0.242 2.2 1.4 5.5 -55 to 150 A W W/C V mJ A mJ V/ns C 300 (for 5s) 0.42(typical) g For footnotes refer to the last page www.irf.com 1 08/03/07 IRFE120, JANTX2N6788U Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified) BVDSS BVDSS/TJ Parameter Min Drain-to-Source Breakdown Voltage 100 Typ Max Units -- -- V -- 0.10 -- V/C -- -- 2.0 1.5 -- -- -- -- -- -- -- -- 0.30 0.35 4.0 -- 25 250 VGS(th) g fs IDSS Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current IGSS IGSS Qg Q gs Q gd td(on) tr td(off) tf LS + LD Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.1 100 -100 18 4.0 9.0 40 70 40 70 -- C iss C oss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance -- -- -- 350 150 24 -- -- RDS(on) V S A nA nC Test Conditions VGS = 0V, ID = 1.0mA Reference to 25C, ID = 1.0mA VGS = 10V, ID = 2.8A VGS = 10V, ID = 4.5A VDS = VGS, ID = 250A VDS > 15V, IDS = 2.8A V DS = 80V, VGS = 0V VDS = 80V VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VGS = 10V, ID = 4.5A VDS = 50V VDD = 35V, ID = 4.5A VGS = 10V, RG = 7.5 ns nH Measured from the center of drain pad to center of source pad pF VGS = 0V, VDS = 25V f = 1.0MHz Source-Drain Diode Ratings and Characteristics Parameter Min Typ Max Units IS ISM VSD trr Q RR Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge ton Forward Turn-On Time -- -- -- -- -- -- -- -- -- -- 4.5 18 1.8 240 2.0 Test Conditions A V ns C Tj = 25C, IS = 4.5A, VGS = 0V Tj = 25C, IF = 4.5A, di/dt 100A/s VDD 50V Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD. Thermal Resistance Parameter RthJC RthJ-PCB Junction to Case Junction to PC Board Min Typ Max -- -- -- -- 8.93 26 Units C/W Test Conditions Soldered to a copper clad PC board Note: Corresponding Spice and Saber models are available on International Rectifier Website. For footnotes refer to the last page 2 www.irf.com IRFE120, JANTX2N6788U Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFE120, JANTX2N6788U 13 a & b Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode Forward Voltage 4 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 8. Maximum Safe Operating Area www.irf.com IRFE120, JANTX2N6788U V DS V GS RG RD D.U.T. + -V DD VGS Pulse Width 1 s Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit VDS 90% Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFE120, JANTX2N6788U 15V L VDS D.U.T RG VGS 20V IAS DRIVER + - VDD A 0.01 tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Current Regulator Same Type as D.U.T. Fig 12b. Unclamped Inductive Waveforms 50K QG 10 V QGS .2F .3F D.U.T. QGD + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 12V IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRFE120, JANTX2N6788U Foot Notes: Repetitive Rating; Pulse width limited by maximum junction temperature. VDD = 25V, starting TJ = 25C, ISD 4.5A, di/dt 110A/s, VDD 100V, TJ 150C Suggested RG =7.5 Pulse width 300 s; Duty Cycle 2% Peak IL = 2.2A, L = 100H Case Outline and Dimensions -- LCC-18 IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 08/2007 www.irf.com 7