1
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ISO102/106
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ISO102
ISO106
DESCRIPTION
The ISO102 and ISO106 isolation buffer amplifiers
are two members of our series of capacitive coupled
isolation products from Burr-Brown. They have the
same electrical performance and they differ in accu-
racy. The ISO102 is rated for 1500Vrms in a 24-pin
DIP. The ISO106 is rated for 3500Vrms in a 40-pin
DIP. Both side-brazed DIPs are 600mil wide and have
industry standard package dimensions with the excep-
tion of missing pins between input and output stages.
This permits utilization of automatic insertion tech-
niques in production. The three-chip hybrid with its
generous high voltage spacing is easy to use (no
external components are required).
Each buffer accurately isolates ±10V analog signals
by digitally encoding the input voltage and uniquely
coupling across a differential ceramic capacitive bar-
FEATURES
●14-BIT LINEARITY
●INDUSTRY’S FIRST HERMETIC
ISOLATION AMPLIFIERS AT LOW COST
●EASY-TO-USE COMPLETE CIRCUIT
●RUGGED BARRIER, HV CERAMIC
CAPACITORS
●100% TESTED FOR HIGH VOLTAGE
BREAKDOWN
ISO102: 4000Vrms/10s, 1500Vrms/1min
ISO106: 8000Vpk/10s, 3500Vrms/1min
●ULTRA HIGH IMR: 125dB min at 60Hz,
ISO106
●WIDE INPUT RANGE: –10V to +10V
●WIDE BANDWIDTH: 70kHz
●VOLTAGE REFERENCE OUTPUT: 5VDC
SIGNAL ISOLATION BUFFER AMPLIFIERS
Covered by patent number 4,748,419 and others pending.
+V
–V
CC1
CC1
Gain
Adjust
+V
–V
CC2
CC2
Digital
Common
Isolation
Barrier
V
IN
Offset
Adjust
Offset
Common
1
Reference
1
+5V
Common
2
Reference
2
C
2
C
1
V
OUT
+5V
rier. All elements necessary for operation are con-
tained within the DIP. This provides compact signal
isolation in a hermetic package.
APPLICATIONS
●INDUSTRIAL PROCESS CONTROL
Transducer channel isolator for thermo-
couples, RTDs, pressure bridges, flow
meters
●4mA TO 20mA LOOP ISOLATION
●MOTOR AND SCR CONTROL
●GROUND LOOP ELIMINATION
●BIOMEDICAL/ANALYTICAL
MEASUREMENTS
●POWER PLANT MONITORING
●DATA ACQUISITION/TEST EQUIPMENT
ISOLATION
●MILITARY EQUIPMENT
© 1987 Burr-Brown Corporation PDS-716F Printed in U.S.A. January, 1995
®
SBOS151
2
®
ISO102/106
SPECIFICATIONS
ELECTRICAL
At TA = +25°C and VCC1 = VCC2 = ±15V unless otherwise noted.
ISO102, ISO106, ISO102B, ISO106B
PARAMETER CONDITIONS MIN TYP MAX UNITS
ISOLATION
Voltage
Rated Continuous(1)
ISO102: AC, 60Hz TMIN to TMAX 1500 Vrms
DC TMIN to TMAX 2121 VDC
ISO106: AC, 60Hz TMIN to TMAX 3500 Vrms
DC TMIN to TMAX 4950 VDC
Test Breakdown, AC, 60Hz
ISO102 10s 4000 Vrms
ISO106 10s 8000 Vpk
Isolation-Mode Rejection(2) VISO = Rated Continuous, 60Hz
AC: ISO102 115 120 dB
12µVrms/V
ISO106 125 130 dB
0.3 0.6 µVrms/V
DC 140 160 dB
0.01 0.10 µVDC/V
Barrier Resistance 1014 Ω
Barrier Capacitance 6pF
Leakage Current VISO = 240Vrms, 60Hz 0.5 1 µArms
INPUT
Voltage Range Rated Operation –10 +10 V
Resistance 75 100 kΩ
Capacitance 5pF
OUTPUT
Voltage Range Rated Operation –10 +10 V
Derated Operation –12 +12 V
Current Drive ±5mA
Short Circuit Current 92050mA
Ripple Voltage(6) f = 0.5MHz to 1.5MHz 3 mVp-p
Resistance 0.3 1 Ω
Capacitive Load Drive Capability 10,000 pF
Overload Recovery Time, 0.1% |VO| > 12V 30 µs
OUTPUT VOLTAGE NOISE
Voltage: f = 0.1Hz to 10Hz 300 µVp-p
f = 0.1Hz to 70kHz 16 µV/ Hz
Dynamic Range(7): f = 0.1Hz to 70kHz 12-Bit Resolution, 1LSB, 20V FS 74 dB
f = 0.1Hz to 280Hz 16-Bit Resolution, 1LSB, 20V FS 96 dB
FREQUENCY RESPONSE
Small Signal Bandwidth 70 kHz
Full Power Bandwidth, 0.1% THD VO = ±10V 5 kHz
Slew Rate VO = ±10V 0.5 V/µs
Settling Time, 0.1% VO = –10V to +10V 100 µs
Overshoot, Small Signal(8) C1 = C2 = 0 40 %
VOLTAGE REFERENCES
Voltage Output, Ref1, Ref2No Load +4.975 +5 +5.025 VDC
B Grade No Load +4.995 +5 +5.005 VDC
vs Temperature ±5 20 ppm/°C
vs Supplies 10 µV/V
vs Load 400 1000 µV/mA
Current Output –0.1 +5 mA
Short Circuit Current 61430mA
POWER SUPPLIES
Rated Voltage, ±VCC1, ±VCC2 Rated Performance ±15 V
Voltage Range ±10 ±20 V
Quiescent Current: +VCC1 No Load +11 +15 mA
–VCC1 –9 –12 mA
+VCC2 +25 +33 mA
–VCC2 –15 –20 mA
Dissipation: ±VCC1 300 400 mW
±VCC2 600 800 mW
TEMPERATURE RANGE
Specification –25 +85 °C
Operating(9) –25 +85 °C
Storage –65 +150 °C
Thermal Resistance,
θ
JA 40 °C/W
θ
JC 12 °C/W
3
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ISO102/106
ORDERING INFORMATION
TEMPERATURE
MODEL PACKAGE RANGE
ISO102 Ceramic –25°C to +85°C
ISO102B Ceramic –25°C to +85°C
ISO106 Ceramic –25°C to +85°C
ISO106B Ceramic –25°C to +85°C
ELECTRICAL (CONT)
ISO102 ISO102B
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
GAIN
Nominal Gain 1 * V/V
Initial Error(3) ±0.1 ±0.25 0.07 0.13 % FSR
Gain vs Temperature ±20 ±50 ±12 ±25 ppm FSR/°C
Nonlinearity(4) VO = –10V to +10V ±0.007 ±0.012 ±0.002 ±0.003 % FSR
INPUT OFFSET VOLTAGE
Initial Offset VIN = 0V ±25 ±70 ±15 ±25 mV
vs Temperature ±250 ±500 ±150 ±250 µV/°C
vs Power Supplies(5) Input Stage, VCC1 = ±10V to ±20V 0 1.4 4.0 * * * mV/V
Output Stage, VCC2 = ±10V to ±20V –4 –1.4 0 * * * mV/V
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ISO106 ISO106B
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
GAIN
Nominal Gain 1 * V/V
Initial Error(3) ±0.1 ±0.25 0.07 * % FSR
Gain vs Temperature ±20 ±50 ±12 ±25 ppm FSR/°C
Nonlinearity(4) VO = –10V to +10V ±0.04 ±0.075 ±0.007 ±0.025 % FSR
INPUT OFFSET VOLTAGE
Initial Offset VIN = 0V ±25 ±70 * * mV
vs Temperature ±250 ±500 ±150 ±250 µV/°C
vs Power Supplies(5) Input Stage, VCC1 = ±10V to ±20V 3.7 * mV/V
Output Stage, VCC2 = ±10V to ±20V –3.7 * mV/V
* Specification same as model to the left.
NOTES: (1) 100% tested at rated continuous for one minute. (2) Isolation-mode rejection is the ratio of the change in output voltage to a change in isolation barrier voltage.
It is a function of frequency as shown in the Typical Performance Curves. This is specified for barrier voltage slew rates not exceeding 100V/µs. (3) Adjustable to zero.
FSR = Full Scale Range = 20V. (4) Nonlinearity is the peak deviation of the output voltage from the best fit straight line. It is expressed as the ratio of deviation to FSR.
(5) Power supply rejection = change in VOS/20V supply change. (6) Ripple is the residual component of the barrier carrier frequency generated internally. (7) Dynamic
range = FSR/(voltage spectral noise density x square root of user bandwidth). (8) Overshoot can be eliminated by band-limiting. (9) See “Power Dissipation vs
Temperature” performance curve for limitations. (10) Band limited to 10Hz, bypass capacitors located less than 0.25" from supply pins.
PACKAGE INFORMATION(1)
PACKAGE DRAWING
MODEL PACKAGE NUMBER
ISO102 24-Pin Ceramic 208
ISO102B 24-Pin Ceramic 208
ISO106 40-Pin Ceramic 206
ISO106B 40-Pin Ceramic 206
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
Supply Without Damage.................................................................... ±20V
Input Voltage Range.......................................................................... ±50V
Transient Immunity, dV/dt .......................................................... 100kV/µs
Continuous Isolation Voltage Across Barrier
ISO102 .................................................................................... 1500Vrms
ISO106 .................................................................................... 3500Vrms
Junction Temperature.................................................................... +160°C
Storage Temperature Range......................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
Amplifier and Reference Output
Short Circuit Duration .......................................Continuous to Common
4
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ISO102/106
PIN CONFIGURATION
–V
V
Gain Adjust
Common
C
Common
Reference
+V
+V
Offset Adjust
Offset
Reference
Digital Common
C
V
–V
1
2
3
4
9
10
11
12
24
23
22
21
16
15
14
13
CC1
CC2
CC1
ISO102
1
OUT
CC2
2
Isolation
Barrier
IN
1
1
2
2
–V
V
Gain Adjust
Common
C
Common
Reference
+V
+V
Offset Adjust
Offset
Reference
Digital Common
C
V
–V
1
2
3
4
17
18
19
20
40
39
38
37
24
23
22
21
CC1
CC2
CC1
ISO106
1
OUT
CC2
2
Isolation
Barrier
IN
1
1
2
2
PIN DESCRIPTIONS
±VCC1, Positive and negative power supply voltages and common (or ground) for the input stage. Common1 is the analog reference voltage for input
Common1signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier.
±VCC2, Positive and negative power supply voltages and common (or ground) for the output stage. Common2 is the analog reference voltage for output
Common2signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier.
VIN Signal input pin. Input impedance is typically 100kΩ. The input range is rated for ±10V. The input level can actually exceed the input stage
supplies. Output signal swing is limited only by the output supply voltages.
Gain This pin is an optional signal input. A series 5k Ω potentiometer between this pin and the input signal allows a guaranteed ±1.5% gain adjustment
Adjust range. When gain adjustment is not required, the Gain Adjust should be left open. Figure 4 illustrates the gain adjustment connection.
Reference1+5V reference output. This low-drift zener voltage reference is necessary for setting the bipolar offset point of the input stage. This pin must
be strapped to either Offset or Offset Adjust to allow the isolation amplifier to function. The reference is often useful for input signal
conditioning circuits. See “Effect of Reference Loading on Offset” performance curve for the effect of offset voltage change with reference loading.
Reference1 is identical to, but independent of, Reference2. This output is short circuit protected.
Reference2+5V reference output. This reference circuit is identical to, but independent of, Reference1. It controls the bipolar offset of the output stage through
an internal connection. This output is short-circuit protected.
Offset Offset input. This input must be strapped to Reference1 unless user adjustment of bipolar offset is required.
Offset This pin is for optional offset control. When connected to the Reference1 pin through a 1kΩ potentiometer, ±150mV of adjustment range is
Adjust guaranteed. Under this condition, the Offset pin should be connected to the Offset Adjust pin. When offset adjustment is not required, the Offset
Adjust pin is left open. See Figure 4.
Digital Digital common or ground. This separate ground carries currents from the digital portions of the output stage circuit. The best grounding practi-
Common ces require that digital common current does not flow in analog common connections. Both pins can be tied directly to a ground plane if available.
Difference in potentials between the Common2 and Digital Common pins can be ±1V. See Figure 2.
VOUT Signal output. Because the isolation amplifier has unity gain, the output signal is ideally identical to the input signal. The output is low impedance
and is short-circuit protected. This signal is referenced to Common2; subsequent circuitry should have a separate “sense” connection to Common 1
as well as VOUT.
C1, C2Capacitors for small signal bandwidth control. These pins connect to the internal rolloff frequency controlling nodes of the output low-pass filter.
Additional capacitance added to these pins will modify the bandwidth of the buffer. C2 is always twice the value of C1. See “Bandwidth Control”
performance curve for the relationship between bandwidth and C1 and C2. When no connections are made to these pins, the full small-signal
bandwidth is maintained. Be sure to shield C1 and C2 pins from high electric fields on the PC board. This preserves AC isolation-mode rejection
by reducing capacitive coupling effects.
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ISO102/106
TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = ±15VDC unless otherwise noted.
ISOLATION-MODE REJECTION
vs ISOLATION VOLTAGE FREQUENCY
Isolation Voltage Frequency (Hz)
Isolation-Mode Rejection (dB)
160
140
120
100
80
60 10 1M100 1k 10k 100k
ISO102
ISO106
DYNAMIC RANGE vs BANDWIDTH
Small Signal Bandwidth (Hz)
Bandwidth Control Capacitors (F)
Dynamic Range (dB)
120
110
100
90
80
70 1 10 100 1k 10k 100k
3µ 300n 30n 3nF 300p 30p
BW —
C —
1
See “Bandwidth
Control” Curve
See Figure 4
V
OUT
= ±1V V
OUT
= ±10V
ISOLATION LEAKAGE CURRENT
vs ISOLATION VOLTAGE FREQUENCY
Isolation Voltage Frequency (Hz)
Isolation Leakage Current (A)
10 1M
10m
1m
100µ
10µ
1µ
100n 100 1k 10k 100k
Isolation Voltage = 240Vrms
Isolation Voltage (V)
0 Rated
1
0.5
0
–0.5
–1
2
1
0
–1
–2
Gain
Offset
T = T to T
MIN MAX
∆
GAIN ERROR AND
∆
OFFSET VOLTAGE
vs ISOLATION VOLTAGE
Gain Error (%)
∆
∆
Offset Voltage (mV)
BANDWIDTH CONTROL
C1 (F)
Small Signal Bandwidth (Hz)
1M
100k
10k
1k
100
10
13p 30p 300p 3n 30n 300n 3µ
C2 = 2 (C1)
See Figure 4
POWER DISSIPATION vs TEMPERATURE
Ambient Temperature (°C)
Maximum Power Dissipation (W)
–25 85 95 105 115 125 135
1.6
1.4
1.2
1
0.8
0
Maximum Power Supplies (V)
±20
±15
±10
0.785
1.178
1.57
= (T – T )/
A
Slope =
P= 40°C/W
θ
JA
D MAX J MAX
θ
JA
Maximum Junction
Temperature = 160°C
Maximum Junction
Temperature = 150°C
0
6
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ISO102/106
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
LARGE SIGNAL TRANSIENT RESPONSE
Time (µs)
0 100 200 300 400
15
10
5
0
–5
–10
–15
Output Voltage (V)
C = 100pF
C = 200pF
1
2
TOTAL HARMONIC DISTORTION
0 Frequency (Hz)
100 1k 10k 100k
THD + Noise (%)
10
1
0.1
0
V = 20Vp-p
O
V = 5Vp-p
O
RECOMMENDED RANGE OF ISOLATION VOLTAGE
Isolation Voltage Frequency (Hz)
1k 10k 100k 1M
10k
Maximum Isolation Voltage (Vpk)
1k
100
10
2k
5k ISO106
ISO102 Nonspecified
Operation
Operational
Region
GAIN/PHASE vs FREQUENCY
0 10 100 1k 10k 100k
Frequency (Hz)
Small Signal Gain (dB)
6
0
–6
–12
–18
90
0
–90
–180
–270
Phase Shift (degrees)
No external C
1
, C
2
Gain
Phase
OUTPUT SPECTRAL NOISE DENSITY
40
35
30
25
20
15
10
5
0
Spectral Noise Density (dB/ Hz)
10µV/ Hz
Reference Signal = 0dBV
0 10 20 30 40 50
Frequency (kHz)
PWR SPEC A: –95.9dBV/ Hz, 31.375kHz
N: 128
: 125Hz
FS: –47dBV
β
GAIN FLATNESS vs FREQUENCY
0 1 2 3 4 5 6 7 8
Frequency (kHz)
Slew Rate Limit
Large Signal Gain (dB)
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
V = 20Vp-p
IN
C = 100pF
C = 200pF
See Figure 4
1
2
7
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ISO102/106
TYPICAL PERFORMANCE CURVES (CONT)
TA = +25°C, VCC = ±15VDC unless otherwise noted.
FIGURE 1. Simplified Diagram of ISO102 and ISO106.
39
23
Offset
Adjust
40
24
+V
CC1
1
1
–V
CC1
20
12
+V
CC2
21
13
–V
CC2
19
11
Ref
2
3
3
4
4
37
Offset
Ref
1
21
38 22
2 2
V
IN
Isolation
Barrier
V
2214
OUT
10
18
16
24 Digital
Common
Common
2
Common
1
ISO102
ISO106
+5V
Out
0.5kΩ 24.5kΩ
2.5kΩ 97.5kΩ Osc.
f
O
f
O
VCO
3pF
3pF
3kΩ
3kΩ
Sense
Amp
C
2
15
23
9
17
C
1
Detector
-Freq.
θ
VCO
+5V Out
Loop
Filter LP
Filter
PLL
Gain
Adjust
f
O
V
IN
THEORY OF OPERATION
The ISO102 and ISO106 have no galvanic connection be-
tween the input and output. The analog input signal refer-
enced to the input common is accurately duplicated at the
output referenced to the output common. Because the barrier
information is digital, potentials between the two commons
can assume a wide range of voltages and frequencies with-
out influencing the output signal. Signal information re-
mains undisturbed until the slew rate of the barrier voltage
exceeds 100V/µs. The isolation amplifier’s ability to reject
fast dV/dt changes between the two grounds is specified as
transient immunity. The amplifier is protected from damage
for slew rates up to 100,000V/µs.
A simplified diagram of the ISO102 and ISO106 is shown in
Figure 1. The design consists of an input voltage-controlled
oscillator (VCO) also known as a voltage-to-frequency con-
verter (VFC), differential capacitors, and output phase lock
loop (PLL). The input VCO drives digital levels directly into
the two 3pF barrier capacitors. The digital signal is fre-
quency modulated and appears differentially across the bar-
rier, while the externally applied isolation voltage appears
common-mode.
EFFECT OF REFERENCE LOADING ON OFFSET
Voltage Reference Load (mA)
10 2
50
0
–50
Output Offset (mV)
Ref1
Ref2
0.01
0.005
0
–0.005
–0.01
ISO102B TYPICAL LINEARITY
–10 0 10
V
OUT
= V
IN
(V)
Nonlinearity (%)
T = –25°C to +85°C bandwidth limited to 10Hz.
(Linearity is limited by 1/f noise). Bypass
capacitors located 0.25" from supply pins.
A
5–5
8
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ISO102/106
A sense amplifier detects only the differential information.
The output stage decodes the frequency modulated signal by
the means of a PLL. The feedback of the PLL employs a
second VCO that is identical to the encoder VCO. The PLL
forces the second VCO to operate at the same frequency
(and phase) as the encoder VCO; therefore, the two VCOs
have the same input voltage. The input voltage of the
decoder VCO serves as the isolation buffer’s output signal
after passing through a 100kHz second-order active filter.
For a more detailed description of the internal operation of
the ISO102 and ISO106, refer to Proceedings of the 1987
International Symposium on Microelectronics, pages 202-
206.
ABOUT THE BARRIER
For any isolation product, barrier composition is of para-
mount importance in achieving high reliability. Both the
ISO102 and ISO106 utilize two 3pF high voltage ceramic
coupling capacitors. They are constructed of tungsten thick
film deposited in a spiral pattern on a ceramic substrate.
Capacitor plates are buried in the package, making the
barrier very rugged and hermetically sealed. Capacitance
results from the fringing electric fields of adjacent metal
runs. Dielectric strength exceeds 10kV and resistance is
typically 1014Ω. Input and output circuitry are contained in
separate solder-sealed cavities, resulting in the industry’s
first fully hermetic hybrid isolation amplifier.
FIGURE 3. Technique for Wiring Analog and Digital Com-
mons Together.
FIGURE 2. Power Supply and Signal Connection.
Input Power Supplies
Input
Ground
Plane
–V
V
Gain Adjust
Common
IN
CC1
1
C
Common
Reference
+V
1
2
CC2
2
CC2
Digital Common
C
V
–V
OUT
2
+V
Offset Adjust
Offset
Reference
1
CC1
NC
0.1µF
NC
IN
V
0.1µF
Output Power Supplies
0.1µF
NC
Output
Ground
Plane
0.1µF
OUT
V
ISO102/106
NC
NC
NC—no connection necessary.
The ISO102 and ISO106 are designed to be free from partial
discharge at rated voltages. Partial discharge is a form of
localized breakdown that degrades the barrier over time.
Since it does not bridge the space across the barrier, it is
difficult to detect. Both isolation amplifiers have been exten-
sively evaluated at high temperature and high voltage.
POWER SUPPLY AND SIGNAL CONNECTIONS
Figure 2 shows the proper power supply and signal connec-
tions. Each supply should be AC-bypassed to Analog Com-
mon with 0.1µF ceramic capacitors as close to the amplifier
as possible. Short leads will minimize lead inductance. A
ground plane will also reduce noise problems. Signal com-
mon lines should tie directly to the common pin even if a
low impedance ground plane is used. Refer to Digital Com-
mon in the Pin Descriptions table.
To avoid gain and isolation-mode rejection (IMR) errors
introduced by the external circuit, connect grounds as indi-
cated, being sure to minimize ground resistance. Any ca-
pacitance across the barrier will increase AC leakage current
and may degrade high frequency IMR. The schematic in
Figure 3 shows the proper technique for wiring analog and
digital commons together.
DISCUSSION OF
SPECIFICATIONS
The IS0102 and IS0106 are unity gain buffer isolation
amplifiers primarily intended for high level input voltages
on the order of 1V to 10V. They may be preceded by
operational, differential, or instrumentation amplifiers that
precondition a low level signal on the order of millivolts and
translate it to a high level.
Input
Common
Load
Circuit
Power
Supply
C
INTERNAL
V
OUT
R
–V
CC
+V
CC
Common
2
Analog Output
Ground
Digital Common
Digital Output
Ground*
V
ISO
C
EXT2
C
EXT1
C
C
EXT1
has minimal effect on total IMR.
and R have a direct effect.
EXT2
Common
1
*Part of ground plane to
reduce voltage drops.
9
®
ISO102/106
noise power varies with the square root of the bandwidth of
the buffer. It is recommended that the bandwidth be reduced
to about twice the maximum signal bandwidth for optimum
dynamic range as shown in the “Dynamic Range vs Band-
width” performance curve. The output spectral noise density
measurement is displayed in the “Output Spectral Noise
Density” performance curve. The noise is flat to within
5dB√Hz between 0.1Hz to 70kHz.
The overall AC gain of the buffer amplifiers is shown in two
performance curves: “Gain Flatness vs Frequency” and
“Gain/Phase vs Frequency.” Note that with C1 = 100pF and
C2 = 200pF, the AC gain remains flat within ±0.01dB up to
7kHz. The total harmonic distortion for large-signal sine
wave outputs is plotted in the “Total Harmonic Distortion”
performance curve. The phase-lock-loop displays slightly
nonuniform rise and fall edges under maximum slew condi-
tions. Reducing the output filter bandwidth to below 70kHz
smoothes the output signal and eliminates any overshoot.
See the “Large Signal Transient Response” performance
curve.
OPTIONAL OFFSET AND GAIN ADJUSTMENT
In many applications the factory-trimmed offset is adequate.
For situations where reduced or modified gain and offset are
required, adjustment of each is easy. The addition of two
potentiometers as shown in Figure 4 provides for a two step
calibration.
Offset should be adjusted first. Gain adjustment does not
interfere with offset. The potentiometer’s TCR adds only
2% to overall temperature drift. The offset and gain adjust-
ment procedures are as follows:
1. Set VIN to 0V and adjust R1 to desired offset at the output.
2. Set VIN to full scale (not zero). Adjust R2 for desired gain.
ISOLATION-MODE REJECTION
The IS0102 and IS0106 provide exceptionally high isola-
tion-mode rejection over a wide range of isolation-mode
voltages and frequencies. The typical performance curves
should be used to insure operation within the recommended
range. The maximum barrier voltage allowed decreases as
the frequency of the voltage increases. As with all isolation
amplifiers, a change of voltage across the barrier will induce
leakage current across the barrier. In the case of the IS0102
and IS0106, there exists a threshold of leakage current
through the signal capacitors that can cause over-drive of the
decoder’s sense amplifier. This occurs when the slew rate of
the isolation voltage reaches 100V/µs. The output will
recover in about 50µs from transients exceeding 100V/µs.
The first two performance curves indicate the expected
isolation-mode rejection over a wide range of isolation
voltage frequencies. Also plotted is the typical leakage
current across the barrier at 240Vrms. The majority of the
leakage current is between the input common pin and the
output digital ground pin.
The IS0102 and IS0106 are intended to be continuously
operated with fully rated isolation voltage and temperature
without significant drift of gain and offset. See the “Gain
Error/Offset Isolation Voltage” performance curve for
changes in gain and offset with isolation voltage.
SUPPLY AND TEMPERATURE RANGE
The IS0102 and IS0106 are rated for +15V supplies; how-
ever, they are guaranteed to operate from ±10V to ±20V.
Performance is also rated for an ambient temperature range
of –25°C to +85°C. For operation outside this temperature
range, refer to the “Power Dissipation vs Temperature”
performance curve to establish the maximum allowed sup-
ply voltage. Supply currents are fairly insensitive to changes
in supply voltage or temperature. Therefore, the maximum
current limits can be used in computing the maximum
junction temperature under nonrated conditions.
OPTIONAL BANDWIDTH CONTROL
The following discussion relates optimum dynamic range
performance to bandwidth, noise, and settling time.
The outputs of the IS0102 and IS0106 are the outputs of a
second-order low-pass Butterworth filter. Its low impedance
output is rated for ±5mA drive and ±12V range with 10,000pF
loads. The closed-loop bandwidth of the PLL is 70kHz,
while the output filter is internally set at 100kHz. The output
filter lowers the residual voltage of the barrier FM signal to
below the noise floor of the output signal.
Two pins are available for optional modification of the
filter’s bandwidth. Only two capacitors are required. The
“Bandwidth Control” performance curve gives the value of
C1 (C2 is equal to twice C1) for the desired bandwidth. Figure
4 illustrates the optional connection of both capacitors.
A tradeoff can be achieved between the required signal
bandwidth and system dynamic range. The noise floor of the
output limits the dynamic range of the output signal. The
–V
V
Gain Adjust
Common
IN
CC1
1
Common
Reference
+V
2
CC2
2
CC2
Digital Common
V
–V
OUT
+V
Offset Adjust
Offset
Reference
1
CC1
0.1µF
IN
V
0.1µF
0.1µF 0.1µF
OUT
V
ISO102/106
NC
–15V
2
C
2
R
1kΩ
+15V–15V
1
R
5kΩ
C
1
+15V
Increase
Offset
Increase Gain
* PCB rings terminate HV fields.
C
1
2
C *
*
FIGURE 4. Optional Gain Adjust, Offset Adjust, and Band-
width Control.
10
®
ISO102/106
PRINTED CIRCUIT BOARD LAYOUT
The distance across the isolation barrier, between external
components, and conductor patterns, should be maximized
to reduce leakage and arcing at high voltages. Good layout
techniques that reduce stray capacitance will assure low
leakage current and high AC IMR. For some applications,
applying conformal coating compound such as urethane is
useful in maintaining good performance. This is especially
true where dirt, grease or moisture can collect on the PC
board surface, component surface, or component pins. Fol-
lowing this industry-accepted practice will give best results,
particularly when circuits are operated or tested in a mois-
ture-condensing environment. Optimum coating can be
achieved by administering urethane under vacuum condi-
tions. This allows complete coverage of all areas. Grounded
rings around the Cl and C2 contacts on the board greatly
reduce high voltage electric fields at these pins.
APPLICATIONS
The ISO102 and ISO106 isolation amplifiers are used in
three categories of applications:
1. accurate isolation of signals from high voltage ground
potentials,
2. accurate isolation of signals from severe ground noise,
and
3. fault protection from high voltages in analog measure-
ment systems.
Figures 5 through 15 show a variety of application circuits.
Additional discussion of applications can be found in the
December 11, 1986 issue of Electronic Design, pages 91-96.
FIGURE 5. Isolated Power Current Monitor for Motor Cir-
cuit. (The ISO102 allows reliable, safe measure-
ment at high voltages.)
Data
Bus
ISO 102
+500VDC
100A
21
22
2
1V
0.01 Ω 4 16
10 14
V
IN
ADC574
13
12
Digital
Ground
Power
Supply
Analog
Ground
Plane
1–5V1+5V 1–5V1+5V
24 1
Y-Connected
Power Transformer
ISO 102
21
22
4 10
16 14
VOUT
13
12
1–5V1+5V 1–5V1+5V
24 1
120Vrms
100A
10INA1
0.005
Power
Resistor
Ω 0.5V
0.001µF
200kΩ
200kΩ
–15V
6 7
9
1
2 8
10
1+5V
Differential input accurately senses power resistor voltage.
Two resistors protect INA110 from open power resistor.
High frequency spike reject filter has f = 400Hz.
CO
2
FIGURE 6. Isolated Power Line Monitor (0.5µA leakage
current at 120Vrms).
FIGURE 7. Battery Monitor for High Voltage Charging
Circuit.
ISO 102
21
22
4 10
16
14
13
12
1–5V1+5V 1–5V1+5V
241
2
Address
Selects
Battery
to be
Measured
MPC8S
Multi-
plexer
+720V
12V
750V
60
B
60
ISO 102
V
Monitor
to ADC
and
Computer
OUT
R
B
1
+708V 1
11
®
ISO102/106
FIGURE 11. Low Cost Eight-Channel Isolation Amplifier Block with Channel-to-Channel Isolation.
ISO 106
38
4 24
18
22
21
20
1–5V1+5V 1–5V1+5V
401
+0.5V to +2.5V
2
37
+5V Ref.
Thermometrics Thermistor
B43KB753F
206.9kΩ
1/2
LM358
75kΩ
133.3kΩ 69.76kΩ
V
OUT
2.5V
0 0.5V
10°C
50°F 30°C
86°F
V
OUT
FIGURE 8. Isolated RTD Temperature Amplifier.
ISO 1
37
38
4 24
18
22
21
20
1–5V1+5V 1–5V1+5V
40 1
V
OUT
2
V
IN
+5V
Reference
25kΩ
25kΩ
7
5
6
–5V
Reference
INA105 25kΩ
2
31
4
1+5V
1–5V
06
FIGURE 10. Isolation Amplifier with Isolated Bipolar Input
Reference.
FIGURE 9. Programmable-Gain Isolation Channel with Gains
of 1, 10, and 100.
ISO 102
21
22
4 10
16
14
13
12
1–5V1+5V 1–5V1+5V
24 1
02PGA
3
5
15
8
6 1
V
OUT
Digital
Optocoupler
A
O
A
1
2
2
1
7
V
IN
4
ISO 1
24
22
13
14
12
1–5V
1+5V
1 4
V
OUT
2
V
IN1
02
+5V Reference Out
Uses 8 ISO102s, 1 isolator/driver, 8 transformers, and 8 rectifiers.
Channel
1
21
0.1µF
10 16
0.1µF
Input Common*
1–5V
Bridge Rectifier
PWS740-3 Transformer
PWS740-2 Oscillator/Driver
PWS740-1
+V
CC
T
T
Power to
Other 7
Channels 1+5V
1µF 0.33µF
100µH/0. Ω1
13
4
5
6
7
12
11
10
9
Input From
Other 7
Channels
14
3
*Supplies 15mA (35mA
max) of isolated supply
current per channel.
MPC8S
1
A
1
A
0
16
8 Analog
Ground
Digital
Ground
1–5V
Offset
12
®
ISO102/106
ISO 102
21
22
4 16
10
14
13
12
1–5V1+5V 1–5V1+5V
24 1
1
V
OUT
2
INA101G or P
2
14
13
1+5V
1–5V
Ground Loop Through Conduit
+In
–In
12
3
5
10
R
G
4
11
1+5V
IN914 K Thermocouple
1MΩ
4990Ω
100Ω
15kΩ
1–5V
FIGURE 12. Thermocouple Amplifier with Ground Loop Elimination, Cold Junction Compensation, and Upscale Burn-out.
FIGURE 13. Remote Isolated Thermocouple Transmitter with Cold Junction Compensation.
PWS 725A
ISO
4
32
1
Offset Adjust
2
16
14
16
102
Analog
Ground
23
2
3
25kΩ
20µH/0.2Ω
1µF
0.33µF
Isolated
Power
1
24
1 4 31
1–5V
1+5V
1–5V
1+5V
Digital
Ground
0.1µF
01
41
0.1µF
1
0.0 µF1
1–5V
1+5V
Isolated
0V to +10V
10kΩ
50kΩ
–1V to
–5V
250Ω
0.02µF
XTR01 1
0.µF1
+V
CC
Twisted
Pair
7
8
11 01
1mA
1mA
3
4
5
6
2500Ω
53.9Ω1
0.0 µF1
5 Ω1 Ω2k
Type
J
20Ω
V
OUT
V
OUT
= °C (Temperature)
100°C/V
1+5V
7
2
0.µF1
3
1+5V
4 0.µF1
6
OPA27
1+5V
7
2
0.µF1
3
1–5V
4 0.µF1
6
OPA27
1+5V
e
1
Zero
Adjust 4mA to
20mA
I
OUT
1kΩ
Gain
Adjust
5kΩ
500Ω
13
®
ISO102/106
FIGURE 15. Right-Leg-Driven ECG Amplifier (with defibrillator protection and calibrator).
+V
CC2
–V
CC1
20µH
0.3µF
1µF
726A
14 16
20
1 4
32 +V
CC1
23 V
OUT
20
ISO
21
1
–V
CC1
+V
CC1
2
5MΩ
5V Reference
1kΩ
1mV
0.0082µF
39µF
11
13
12
0.0082µF
10
8
9
–V
CC1
100kΩ
–V
CC1
Gain = 1000
–V
CC1
+V
CC1
3
2
7
6
4
OPA121
NE2H
180kΩ
300kΩ
500pF
Right
Leg
Left
Arm
NOTE: Diodes are IN4148.
NE2H
500pF
200pF
50kΩ
50kΩ
NE2H
300kΩ
300kΩ
Right
Arm
On
Calibration
+V
CC1
+V
CC1
+V
CC1
–V
CC1
15
4
7
5
6
14
INA102
PWS
Calibration
On
Calibration
On
–V
CC2
22
0.082µF
C
2
24
1718
106
4 +V
CC2
0.039µF
C
1
1V/mV
37
38
40
FIGURE 14. Isolated Instrumentation Amplifier for 300Ω Bridge. (Reference voltage from isolation amplifier is used to excite
bridge.)
PWS
PWS
PWS
PWS
PWS
725A
726A
740
745
750
ISO
ISO
Isolated
DC/DC
102
106
20µH/0.2Ω
1µF
0.33µF
1+5V
300Ω
INA102
Digital
Ground
V
OUT
1–5V
Analog Ground
2.7mA 14mA
680Ω
16.7mA
+5V
Out
V
REF1
V
IN
V
OUT
=
x00 V
B
1
Isolation
Barrier
Gnd
0.1µF
Common
1
5
6
7 11
10
9
12 1+5V
1–5V
15
14
Instrumentation
Amplifier
(A = 1000)
V
V
ISO
∆
V
B
∆
14
®
ISO102/106
AN ERROR ANALYSIS OF THE IS0102 IN A
SMALL SIGNAL MEASURING APPLICATION
High accuracy measurements of low-level signals in the
presence of high isolation mode voltages can be difficult due
to the errors of the isolation amplifiers themselves.
This error analysis shows that when a low drift operational
amplifier is used to preamplify the low-level source signal,
a low cost, simple and accurate solution is possible.
In the circuit shown in Figure 16, a 50mV shunt is used to
measure the current in a 500VDC motor. The OPA27
amplifies the 50mV by 200 x to 10V full scale. The output
of the OPA27 is fed to the input of the IS0102, which is a
unity-gain isolation amplifier. The 5kΩ and 1kΩ potentiom-
eters connected to the IS0102 are used to adjust the gain and
offset errors to zero as described in Discussion of Specifica-
tions.
Some Observations
The total errors of the op amp and the ISO amp combined are
approximately 0.11% of full-scale range (see Figure 17). If
the op amp had not been used to preamplify the signal, the
errors would have been 2.6% of FSR. Clearly, the small cost
of adding the op amp buys a large performance improve-
ment. Optimum performance, therefore, is obtained when
the full ±10V range of the IS0102/106 is utilized.
The rms noise of the IS0102 with a 120Hz bandwidth is only
0.18mVrms, which is only 0.0018% of the 10V full scale
output. Therefore, even though the 16µV/ √Hz noise spectral
density specification may appear large compared to other
isolation amplifiers, it does not turn out to be a significant
error term. It is worth noting that even if the bandwidth is
increased to 10kHz, the noise of the iso amp would only
contribute 0.016%FSR error.
Input
Power
Supply
ISO 102
1+5V
OPA27
200kΩ
V
IN
V
OUT
4
8
1
7
2
3
DC Motor
Output
Power
Supply 1–5V
1+5V
1–5V
10 16 9 15
14
0.04µF
C
2
Bandwidth
Control
C
1
0.022µF
Output
Common
V
ISO
500VDC
Input Common
V
D
1kΩ
R
1
+500VDC
R
F
1+5V
0kΩ1
Offset
Adjust
+V
CC1
6
V
D
= 50mVDC (FS)
1+5V
0.1µF0.1µF
+V
CC2
0.1µF
0.1µF
1–5V
–V
CC2
1+5V
+V
CC1
1–5V
–V
CC1
13
12
1
24
3
2
5kΩ
Gain
Adjust
kΩ
Offset Adjust
22
23
21
1
1–5V
–V
CC1
Offset Adjust
Reference
1
Offset
FIGURE 16. 50mV Shunt Measures Current in a 500VDC Motor.
15
®
ISO102/106
The Errors of the Op Amp at 25°C (Referred to Input, RTI)
VE (OPA) = VD 1 – 1 + 1 + VOS (1 + R1/RF) + IB R1 + P.S.R. + Noise
VE (OPA) = Total Op Amp Error (RTI)
VD = Differential Voltage (Full Scale) Across Shunt
1 – 1 + 1 = Gain Error Due to Finite Open Loop Gain
β = Feedback Factor
AVOL = Open Loop Gain at Signal Frequency
VOS = Input Offset Voltage
IB = Input Bias Current
P.S.R. = Power Supply Rejection (µV/V) [Assuming a 5% change with ±15V supplies. Total error is twice that due to one supply.]
Noise = 5nV/ Hz (for 1kΩ source resistance and 1kHz bandwidth)
ERROR(OPA) (RTI) GAIN ERROR OFFSET P.S.R. NOISE
VE (OPA) = 50mV 1 – 1 + 1 {0.025mV (1 + 1/ 200) + 40 x 10–9 x 10 3}(20µV/V x 0.75V x 2) {5nV√120 (nVrms)}
= 0.01mV (0.0251mV + 0.04mV) + 0.03mV + 0.055 x 10–3mVrms
Error as % of FSR = 0.02% + (0.05% + 0.08%) + 0.06% + 0.00011%
After Nulling = 0.01mV + (0mV + 0mV) + 0.03mV + 0.055 x 10–3mVrms
= 0.10mV
Error as % of FSR* = 0.02% + (0% + 0%) + 0.06% + 0.00011%
= 0.08% of 50mV
*FSR = Full-Scale Range. 50mV at input to op amp, or 10V at input (and output) of ISO amp.
The Errors of the Iso Amp at 25°C (RTI)
VE (ISO) = 1/ 200 (VISO/IMR + VOS + G.E. + Nonlinearity + P.S.R. + Noise)
VE (ISO) = Total ISO Amp Error
IMR = Isolation Mode Rejection
VOS = Input Offset Voltage
VISO = VIMV = Isolation Voltage = Isolation Mode Voltage
G.E. = Gain Error (% of FSR)
Nonlinearity = Peak-to-peak deviation of output voltage from best-fit straight line. It is expressed as ratio based on full-scale range.
P.S.R. = Change in VOS /10V x Supply Change
Noise = Spectral noise density x √bandwidth. It is recommended that bandwidth be limited t o twic e maximum signal bandwidth for optimum dynamic range.
ERROR(ISO) (RTI) IMR VOS G.E. NONLINEARITY P.S.R. NOISE
VE (ISO) = 1/200 { 500VDC/140dB + 70mV + 20V x 0.25 /100 + 0.003/100 x 20V 1.4mV x 0.75V x 2+16µV√120 (rms) }
= 1/200 { 0.05mV + 70mV + 50mV + 0.6mV + 2.1mV + 0.175mVrms }
Error as % of FSR = 0.0005% + 0.7% + 0.5% + 0.006% + 0.021% + 0.00175%
After Nulling
VE (ISO) = 1/200 { 0.05mV + 0mV + 0mV + 0.6mV + 2.1mV + 0.175mVrms }
= 1/200 (3.0mV)
= 0.03mV
Error as % of FSR = 0.0005% + 0% + 0% + 0.006% + 0.021% + 0.00175%
= 0.03% of 50mV
Total Error = VE (OPA) +V
E (ISO)
= 0.10mV + 0.03mV
= 0.08% of 50mV + 0.03% of 50mV
= 0.11% of 50mV
{ }
β AVOL
{ }
β AVOL
{ }
106/200
FIGURE 17. Op Amp and Iso Amp Error Analysis.
1
1
1
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ISO102 NRND CDIP SB JVE 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO102B NRND CDIP SB JVE 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO106 NRND CDIP SB JVD 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
ISO106B NRND CDIP SB JVD 16 1 Green (RoHS &
no Sb/Br) AU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-May-2009
Addendum-Page 1
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