(R) ISO102 ISO106 SIGNAL ISOLATION BUFFER AMPLIFIERS FEATURES APPLICATIONS 14-BIT LINEARITY INDUSTRIAL PROCESS CONTROL Transducer channel isolator for thermocouples, RTDs, pressure bridges, flow meters 4mA TO 20mA LOOP ISOLATION MOTOR AND SCR CONTROL INDUSTRY'S FIRST HERMETIC ISOLATION AMPLIFIERS AT LOW COST EASY-TO-USE COMPLETE CIRCUIT RUGGED BARRIER, HV CERAMIC CAPACITORS GROUND LOOP ELIMINATION BIOMEDICAL/ANALYTICAL MEASUREMENTS POWER PLANT MONITORING DATA ACQUISITION/TEST EQUIPMENT ISOLATION MILITARY EQUIPMENT 100% TESTED FOR HIGH VOLTAGE BREAKDOWN ISO102: 4000Vrms/10s, 1500Vrms/1min ISO106: 8000Vpk/10s, 3500Vrms/1min ULTRA HIGH IMR: 125dB min at 60Hz, ISO106 WIDE INPUT RANGE: -10V to +10V WIDE BANDWIDTH: 70kHz VOLTAGE REFERENCE OUTPUT: 5VDC DESCRIPTION The ISO102 and ISO106 isolation buffer amplifiers are two members of our series of capacitive coupled isolation products from Burr-Brown. They have the same electrical performance and they differ in accuracy. The ISO102 is rated for 1500Vrms in a 24-pin DIP. The ISO106 is rated for 3500Vrms in a 40-pin DIP. Both side-brazed DIPs are 600mil wide and have industry standard package dimensions with the exception of missing pins between input and output stages. This permits utilization of automatic insertion techniques in production. The three-chip hybrid with its generous high voltage spacing is easy to use (no external components are required). rier. All elements necessary for operation are contained within the DIP. This provides compact signal isolation in a hermetic package. Each buffer accurately isolates 10V analog signals by digitally encoding the input voltage and uniquely coupling across a differential ceramic capacitive bar- Isolation Barrier +VCC1 +VCC2 -VCC1 -VCC2 Gain Adjust Digital Common VIN Offset Adjust C1 Offset Reference 1 Common 1 Covered by patent number 4,748,419 and others pending. VOUT C2 +5V +5V Reference 2 Common 2 International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) 1987 Burr-Brown Corporation PDS-716F 1 (R) SBOS151 Printed in U.S.A. January, 1995 ISO102/106 SPECIFICATIONS ELECTRICAL At TA = +25C and VCC1 = VCC2 = 15V unless otherwise noted. ISO102, ISO106, ISO102B, ISO106B PARAMETER ISOLATION Voltage Rated Continuous(1) ISO102: AC, 60Hz DC ISO106: AC, 60Hz DC Test Breakdown, AC, 60Hz ISO102 ISO106 Isolation-Mode Rejection(2) AC: ISO102 CONDITIONS MIN TMIN to TMAX TMIN to TMAX TMIN to TMAX TMIN to TMAX 1500 2121 3500 4950 Vrms VDC Vrms VDC 10s 10s VISO = Rated Continuous, 60Hz 4000 8000 Vrms Vpk 115 ISO106 125 DC 140 Barrier Resistance Barrier Capacitance Leakage Current VISO = 240Vrms, 60Hz INPUT Voltage Range Resistance Capacitance Rated Operation OUTPUT Voltage Range -10 75 OUTPUT VOLTAGE NOISE Voltage: f = 0.1Hz to 10Hz f = 0.1Hz to 70kHz Dynamic Range(7): f = 0.1Hz to 70kHz f = 0.1Hz to 280Hz FREQUENCY RESPONSE Small Signal Bandwidth Full Power Bandwidth, 0.1% THD Slew Rate Settling Time, 0.1% Overshoot, Small Signal(8) VOLTAGE REFERENCES Voltage Output, Ref1, Ref2 B Grade vs Temperature vs Supplies vs Load Current Output Short Circuit Current POWER SUPPLIES Rated Voltage, VCC1, VCC2 Voltage Range Quiescent Current: +VCC1 -VCC1 +VCC2 -VCC2 Dissipation: VCC1 VCC2 2 0.6 0.10 1 UNITS dB Vrms/V dB Vrms/V dB VDC/V pF Arms V k pF +10 +12 30 V V mA mA mVp-p pF s 12-Bit Resolution, 1LSB, 20V FS 16-Bit Resolution, 1LSB, 20V FS 300 16 74 96 Vp-p V/ Hz dB dB VO = 10V VO = 10V VO = -10V to +10V C1 = C2 = 0 70 5 0.5 100 40 kHz kHz V/s s % -10 -12 5 9 f = 0.5MHz to 1.5MHz 100 5 20 3 0.3 50 1 10,000 |VO | > 12V No Load No Load +4.975 +4.995 -0.1 6 Rated Performance 10 No Load +5 +5 5 10 400 14 15 +11 -9 +25 -15 300 600 TEMPERATURE RANGE Specification Operating(9) Storage Thermal Resistance, JA -25 -25 -65 (R) 2 +5.025 +5.005 20 1000 +5 30 VDC VDC ppm/C V/V V/mA mA mA 20 +15 -12 +33 -20 400 800 V V mA mA mA mA mW mW +85 +85 +150 40 12 JC ISO102/106 120 1 130 0.3 160 0.01 1014 6 0.5 MAX +10 Rated Operation Derated Operation Current Drive Short Circuit Current Ripple Voltage(6) Resistance Capacitive Load Drive Capability Overload Recovery Time, 0.1% TYP C C C C/W C/W ELECTRICAL (CONT) ISO102 PARAMETER CONDITIONS GAIN Nominal Gain Initial Error(3) Gain vs Temperature Nonlinearity(4) MIN V O = -10V to +10V INPUT OFFSET VOLTAGE Initial Offset vs Temperature vs Power Supplies(5) VIN = 0V Input Stage, VCC1 = 10V to 20V Output Stage, VCC2 = 10V to 20V 0 -4 CONDITIONS MIN ISO102B TYP MAX 1 0.1 20 0.007 25 250 1.4 -1.4 MIN TYP MAX UNITS 0.25 50 0.012 * 0.07 12 0.002 0.13 25 0.003 V/V % FSR ppm FSR/C % FSR 70 500 4.0 0 * * 15 150 * * 25 250 * * mV V/C mV/V mV/V TYP MAX MIN TYP MAX UNITS 1 0.1 20 0.04 0.25 50 0.075 * 0.07 12 0.007 * 25 0.025 V/V % FSR ppm FSR/C % FSR ISO106 PARAMETER GAIN Nominal Gain Initial Error(3) Gain vs Temperature Nonlinearity(4) V O = -10V to +10V INPUT OFFSET VOLTAGE Initial Offset vs Temperature vs Power Supplies(5) 25 250 3.7 -3.7 VIN = 0V Input Stage, VCC1 = 10V to 20V Output Stage, VCC2 = 10V to 20V ISO106B 70 500 * 150 * * * 250 mV V/C mV/V mV/V * Specification same as model to the left. NOTES: (1) 100% tested at rated continuous for one minute. (2) Isolation-mode rejection is the ratio of the change in output voltage to a change in isolation barrier voltage. It is a function of frequency as shown in the Typical Performance Curves. This is specified for barrier voltage slew rates not exceeding 100V/s. (3) Adjustable to zero. FSR = Full Scale Range = 20V. (4) Nonlinearity is the peak deviation of the output voltage from the best fit straight line. It is expressed as the ratio of deviation to FSR. (5) Power supply rejection = change in VOS/20V supply change. (6) Ripple is the residual component of the barrier carrier frequency generated internally. (7) Dynamic range = FSR/(voltage spectral noise density x square root of user bandwidth). (8) Overshoot can be eliminated by band-limiting. (9) See "Power Dissipation vs Temperature" performance curve for limitations. (10) Band limited to 10Hz, bypass capacitors located less than 0.25" from supply pins. ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION MODEL PACKAGE ISO102 ISO102B ISO106 ISO106B Ceramic Ceramic Ceramic Ceramic Supply Without Damage .................................................................... 20V Input Voltage Range .......................................................................... 50V Transient Immunity, dV/dt .......................................................... 100kV/s Continuous Isolation Voltage Across Barrier ISO102 .................................................................................... 1500Vrms ISO106 .................................................................................... 3500Vrms Junction Temperature .................................................................... +160C Storage Temperature Range ......................................... -65C to +150C Lead Temperature (soldering, 10s) ............................................... +300C Amplifier and Reference Output Short Circuit Duration ....................................... Continuous to Common TEMPERATURE RANGE -25C -25C -25C -25C to to to to +85C +85C +85C +85C PACKAGE INFORMATION(1) MODEL PACKAGE PACKAGE DRAWING NUMBER ISO102 ISO102B ISO106 ISO106B 24-Pin Ceramic 24-Pin Ceramic 40-Pin Ceramic 40-Pin Ceramic 208 208 206 206 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 3 ISO102/106 PIN CONFIGURATION ISO102 ISO106 -VCC1 1 24 +VCC1 V IN 2 23 Offset Adjust Gain Adjust 3 22 Offset Common1 4 21 Reference1 Isolation Barrier -VCC1 1 40 +VCC1 V IN 2 39 Offset Adjust Gain Adjust 3 38 Offset Common1 4 37 Reference1 C1 17 24 Digital Common Isolation Barrier C1 9 16 Digital Common Common 2 10 15 C2 Reference 2 11 14 VOUT +VCC2 12 13 -V CC2 Common 2 18 23 C2 Reference 2 19 22 VOUT +VCC2 20 21 -V CC2 PIN DESCRIPTIONS VCC1 , Common1 Positive and negative power supply voltages and common (or ground) for the input stage. Common1 is the analog reference voltage for input signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier. VCC2 , Common2 Positive and negative power supply voltages and common (or ground) for the output stage. Common2 is the analog reference voltage for output signals. The voltage between Common1 and Common2 is the isolation voltage and appears across the internal high voltage barrier. VIN Signal input pin. Input impedance is typically 100k. The input range is rated for 10V. The input level can actually exceed the input stage supplies. Output signal swing is limited only by the output supply voltages. Gain Adjust This pin is an optional signal input. A series 5k potentiometer between this pin and the input signal allows a guaranteed 1.5% gain adjustment range. When gain adjustment is not required, the Gain Adjust should be left open. Figure 4 illustrates the gain adjustment connection. Reference1 +5V reference output. This low-drift zener voltage reference is necessary for setting the bipolar offset point of the input stage. This pin must be strapped to either Offset or Offset Adjust to allow the isolation amplifier to function. The reference is often useful for input signal conditioning circuits. See "Effect of Reference Loading on Offset" performance curve for the effect of offset voltage change with reference loading. Reference1 is identical to, but independent of, Reference2 . This output is short circuit protected. Reference2 +5V reference output. This reference circuit is identical to, but independent of, Reference1. It controls the bipolar offset of the output stage through an internal connection. This output is short-circuit protected. Offset Offset input. This input must be strapped to Reference1 unless user adjustment of bipolar offset is required. Offset Adjust This pin is for optional offset control. When connected to the Reference1 pin through a 1k potentiometer, 150mV of adjustment range is guaranteed. Under this condition, the Offset pin should be connected to the Offset Adjust pin. When offset adjustment is not required, the Offset Adjust pin is left open. See Figure 4. Digital Common Digital common or ground. This separate ground carries currents from the digital portions of the output stage circuit. The best grounding practices require that digital common current does not flow in analog common connections. Both pins can be tied directly to a ground plane if available. Difference in potentials between the Common2 and Digital Common pins can be 1V. See Figure 2. VOUT Signal output. Because the isolation amplifier has unity gain, the output signal is ideally identical to the input signal. The output is low impedance and is short-circuit protected. This signal is referenced to Common2; subsequent circuitry should have a separate "sense" connection to Common1 as well as VOUT. C1, C2 Capacitors for small signal bandwidth control. These pins connect to the internal rolloff frequency controlling nodes of the output low-pass filter. Additional capacitance added to these pins will modify the bandwidth of the buffer. C2 is always twice the value of C1. See "Bandwidth Control" performance curve for the relationship between bandwidth and C1 and C2. When no connections are made to these pins, the full small-signal bandwidth is maintained. Be sure to shield C1 and C2 pins from high electric fields on the PC board. This preserves AC isolation-mode rejection by reducing capacitive coupling effects. (R) ISO102/106 4 TYPICAL PERFORMANCE CURVES TA = +25C, VCC = 15VDC unless otherwise noted. ISOLATION LEAKAGE CURRENT vs ISOLATION VOLTAGE FREQUENCY ISOLATION-MODE REJECTION vs ISOLATION VOLTAGE FREQUENCY 10m Isolation Leakage Current (A) Isolation-Mode Rejection (dB) 160 140 ISO106 120 100 ISO102 80 60 Isolation Voltage = 240Vrms 1m 100 10 1 100n 10 100 1k 10k 100k 1M 10 100 Isolation Voltage Frequency (Hz) 1k 10k 100k 1M Isolation Voltage Frequency (Hz) GAIN ERROR AND OFFSET VOLTAGE vs ISOLATION VOLTAGE POWER DISSIPATION vs TEMPERATURE 2 1.6 1 Gain 0 0 Offset -0.5 -1 -1 Offset Voltage (mV) Gain Error (%) 0.5 Maximum Power Dissipation (W) T = TMIN to TMAX 1.4 Maximum Junction Temperature = 150C 15 1.178 1 Slope = JA = 40C/W P D MAX = (TJ MAX - TA )/ JA 0.8 10 0.785 0 0 -25 85 95 Isolation Voltage (V) 105 115 125 135 Ambient Temperature (C) DYNAMIC RANGE vs BANDWIDTH BANDWIDTH CONTROL 120 1M 100k 110 Dynamic Range (dB) Small Signal Bandwidth (Hz) Maximum Junction Temperature = 160C 1.2 -2 Rated 0 20 1.57 Maximum Power Supplies (V) 1 C2 = 2 (C1) 10k 1k 100 See Figure 4 See "Bandwidth Control" Curve 100 90 VOUT = 1V VOUT = 10V 80 10 See Figure 4 1 3p 30p 300p 3n 30n 300n 70 BW -- 1 3 10 100 C1 (F) 1k 10k 100k Small Signal Bandwidth (Hz) C1-- 3 300n 30n 3nF 300p 30p Bandwidth Control Capacitors (F) (R) 5 ISO102/106 TYPICAL PERFORMANCE CURVES (CONT) TA = +25C, VCC = 15VDC unless otherwise noted. OUTPUT SPECTRAL NOISE DENSITY GAIN FLATNESS vs FREQUENCY 0.03 Reference Signal = 0dBV VIN = 20Vp-p 35 Slew Rate Limit Large Signal Gain (dB) 0.02 30 PWR SPEC A: -95.9dBV/ Hz, 31.375kHz N: 128 : 125Hz FS: -47dBV 25 20 10V/ Hz Spectral Noise Density (dB/ Hz) 40 15 10 0.01 0 C1 = 100pF C2 = 200pF See Figure 4 -0.01 -0.02 5 0 -0.03 0 10 20 30 40 50 0 1 2 3 4 5 6 7 8 Frequency (kHz) Frequency (kHz) TOTAL HARMONIC DISTORTION GAIN/PHASE vs FREQUENCY 6 10 90 0 Phase -6 -90 No external C1 , C2 -12 -180 THD + Noise (%) 0 Phase Shift (degrees) Small Signal Gain (dB) Gain 1 VO = 5Vp-p 0.1 VO = 20Vp-p -18 -270 0 10 100 1k 10k 0 100k 0 100 1k Frequency (Hz) LARGE SIGNAL TRANSIENT RESPONSE Maximum Isolation Voltage (Vpk) 10k Output Voltage (V) 10 5 0 C1 = 100pF C2 = 200pF -10 100k RECOMMENDED RANGE OF ISOLATION VOLTAGE 15 -5 10k Frequency (Hz) ISO106 5k 2k 100 Nonspecified Operation ISO102 1k Operational Region 10 -15 0 100 200 300 1k 400 (R) ISO102/106 10k 100k Isolation Voltage Frequency (Hz) Time (s) 6 1M TYPICAL PERFORMANCE CURVES (CONT) TA = +25C, VCC = 15VDC unless otherwise noted. ISO102B TYPICAL LINEARITY EFFECT OF REFERENCE LOADING ON OFFSET 0.01 TA = -25C to +85C bandwidth limited to 10Hz. (Linearity is limited by 1/f noise). Bypass capacitors located 0.25" from supply pins. 0.005 Nonlinearity (%) Output Offset (mV) 50 Ref 2 0 Ref1 0 -0.005 -0.01 -50 0 1 -10 2 -5 0 5 10 VOUT = VIN (V) Voltage Reference Load (mA) THEORY OF OPERATION The ISO102 and ISO106 have no galvanic connection between the input and output. The analog input signal referenced to the input common is accurately duplicated at the output referenced to the output common. Because the barrier information is digital, potentials between the two commons can assume a wide range of voltages and frequencies without influencing the output signal. Signal information remains undisturbed until the slew rate of the barrier voltage exceeds 100V/s. The isolation amplifier's ability to reject fast dV/dt changes between the two grounds is specified as transient immunity. The amplifier is protected from damage for slew rates up to 100,000V/s. Offset Adjust +VCC1 A simplified diagram of the ISO102 and ISO106 is shown in Figure 1. The design consists of an input voltage-controlled oscillator (VCO) also known as a voltage-to-frequency converter (VFC), differential capacitors, and output phase lock loop (PLL). The input VCO drives digital levels directly into the two 3pF barrier capacitors. The digital signal is frequency modulated and appears differentially across the barrier, while the externally applied isolation voltage appears common-mode. -VCC1 39 40 1 23 24 1 Isolation Barrier +VCC2 -VCC2 Ref2 20 21 19 12 13 11 +5V Out V IN fO VCO Ref1 37 21 +5V Out VCO 0.5k fO 24.5k 3pF 3k 38 22 fO Offset 2.5k 2 97.5k Osc. 3pF VOUT -Freq. Detector Sense Amp Loop Filter LP Filter 14 22 3k 2 PLL V IN ISO102 ISO106 3 4 10 16 9 15 3 4 18 24 17 23 C1 C2 Gain Adjust Common1 Common2 Digital Common FIGURE 1. Simplified Diagram of ISO102 and ISO106. (R) 7 ISO102/106 A sense amplifier detects only the differential information. The output stage decodes the frequency modulated signal by the means of a PLL. The feedback of the PLL employs a second VCO that is identical to the encoder VCO. The PLL forces the second VCO to operate at the same frequency (and phase) as the encoder VCO; therefore, the two VCOs have the same input voltage. The input voltage of the decoder VCO serves as the isolation buffer's output signal after passing through a 100kHz second-order active filter. For a more detailed description of the internal operation of the ISO102 and ISO106, refer to Proceedings of the 1987 International Symposium on Microelectronics, pages 202206. The ISO102 and ISO106 are designed to be free from partial discharge at rated voltages. Partial discharge is a form of localized breakdown that degrades the barrier over time. Since it does not bridge the space across the barrier, it is difficult to detect. Both isolation amplifiers have been extensively evaluated at high temperature and high voltage. POWER SUPPLY AND SIGNAL CONNECTIONS Figure 2 shows the proper power supply and signal connections. Each supply should be AC-bypassed to Analog Common with 0.1F ceramic capacitors as close to the amplifier as possible. Short leads will minimize lead inductance. A ground plane will also reduce noise problems. Signal common lines should tie directly to the common pin even if a low impedance ground plane is used. Refer to Digital Common in the Pin Descriptions table. To avoid gain and isolation-mode rejection (IMR) errors introduced by the external circuit, connect grounds as indicated, being sure to minimize ground resistance. Any capacitance across the barrier will increase AC leakage current and may degrade high frequency IMR. The schematic in Figure 3 shows the proper technique for wiring analog and digital commons together. ABOUT THE BARRIER For any isolation product, barrier composition is of paramount importance in achieving high reliability. Both the ISO102 and ISO106 utilize two 3pF high voltage ceramic coupling capacitors. They are constructed of tungsten thick film deposited in a spiral pattern on a ceramic substrate. Capacitor plates are buried in the package, making the barrier very rugged and hermetically sealed. Capacitance results from the fringing electric fields of adjacent metal runs. Dielectric strength exceeds 10kV and resistance is typically 1014. Input and output circuitry are contained in separate solder-sealed cavities, resulting in the industry's first fully hermetic hybrid isolation amplifier. Input Ground Plane DISCUSSION OF SPECIFICATIONS The IS0102 and IS0106 are unity gain buffer isolation amplifiers primarily intended for high level input voltages on the order of 1V to 10V. They may be preceded by operational, differential, or instrumentation amplifiers that precondition a low level signal on the order of millivolts and translate it to a high level. Input Power Supplies 0.1F Offset Adjust V IN NC 0.1F +V CC1 -V CC1 NC Offset Gain Adjust V IN Reference1 Common 1 C INTERNAL ISO102/106 V OUT NC C1 Digital Common R Common 2 NC Reference 2 C2 NC Common 2 Analog Output Ground C EXT2 VOUT VOUT +VCC2 -VCC2 0.1F Output Ground Plane Load Circuit Common 1 0.1F Input Common Output Power Supplies C EXT1 Digital Common Digital Output Ground* +V CC -V CC Power Supply V ISO C EXT1 has minimal effect on total IMR. C EXT2 and R have a direct effect. *Part of ground plane to reduce voltage drops. NC--no connection necessary. FIGURE 2. Power Supply and Signal Connection. FIGURE 3. Technique for Wiring Analog and Digital Commons Together. (R) ISO102/106 8 ISOLATION-MODE REJECTION The IS0102 and IS0106 provide exceptionally high isolation-mode rejection over a wide range of isolation-mode voltages and frequencies. The typical performance curves should be used to insure operation within the recommended range. The maximum barrier voltage allowed decreases as the frequency of the voltage increases. As with all isolation amplifiers, a change of voltage across the barrier will induce leakage current across the barrier. In the case of the IS0102 and IS0106, there exists a threshold of leakage current through the signal capacitors that can cause over-drive of the decoder's sense amplifier. This occurs when the slew rate of the isolation voltage reaches 100V/s. The output will recover in about 50s from transients exceeding 100V/s. The first two performance curves indicate the expected isolation-mode rejection over a wide range of isolation voltage frequencies. Also plotted is the typical leakage current across the barrier at 240Vrms. The majority of the leakage current is between the input common pin and the output digital ground pin. The IS0102 and IS0106 are intended to be continuously operated with fully rated isolation voltage and temperature without significant drift of gain and offset. See the "Gain Error/Offset Isolation Voltage" performance curve for changes in gain and offset with isolation voltage. -15V +15V 0.1F -V CC1 Increase Gain 0.1F +V CC1 V IN Offset Adjust R1 Gain Adjust Offset 5k V IN R2 Common 1 Reference1 1k ISO102/106 Increase Offset * C1 Digital Common C1 * NC Common 2 C2 Reference 2 VOUT C2 VOUT +VCC2 0.1F +15V -VCC2 0.1F * PCB rings terminate HV fields. -15V FIGURE 4. Optional Gain Adjust, Offset Adjust, and Bandwidth Control. noise power varies with the square root of the bandwidth of the buffer. It is recommended that the bandwidth be reduced to about twice the maximum signal bandwidth for optimum dynamic range as shown in the "Dynamic Range vs Bandwidth" performance curve. The output spectral noise density measurement is displayed in the "Output Spectral Noise Density" performance curve. The noise is flat to within 5dBHz between 0.1Hz to 70kHz. The overall AC gain of the buffer amplifiers is shown in two performance curves: "Gain Flatness vs Frequency" and "Gain/Phase vs Frequency." Note that with C1 = 100pF and C2 = 200pF, the AC gain remains flat within 0.01dB up to 7kHz. The total harmonic distortion for large-signal sine wave outputs is plotted in the "Total Harmonic Distortion" performance curve. The phase-lock-loop displays slightly nonuniform rise and fall edges under maximum slew conditions. Reducing the output filter bandwidth to below 70kHz smoothes the output signal and eliminates any overshoot. See the "Large Signal Transient Response" performance curve. SUPPLY AND TEMPERATURE RANGE The IS0102 and IS0106 are rated for +15V supplies; however, they are guaranteed to operate from 10V to 20V. Performance is also rated for an ambient temperature range of -25C to +85C. For operation outside this temperature range, refer to the "Power Dissipation vs Temperature" performance curve to establish the maximum allowed supply voltage. Supply currents are fairly insensitive to changes in supply voltage or temperature. Therefore, the maximum current limits can be used in computing the maximum junction temperature under nonrated conditions. OPTIONAL BANDWIDTH CONTROL The following discussion relates optimum dynamic range performance to bandwidth, noise, and settling time. The outputs of the IS0102 and IS0106 are the outputs of a second-order low-pass Butterworth filter. Its low impedance output is rated for 5mA drive and 12V range with 10,000pF loads. The closed-loop bandwidth of the PLL is 70kHz, while the output filter is internally set at 100kHz. The output filter lowers the residual voltage of the barrier FM signal to below the noise floor of the output signal. Two pins are available for optional modification of the filter's bandwidth. Only two capacitors are required. The "Bandwidth Control" performance curve gives the value of C1 (C2 is equal to twice C1) for the desired bandwidth. Figure 4 illustrates the optional connection of both capacitors. OPTIONAL OFFSET AND GAIN ADJUSTMENT In many applications the factory-trimmed offset is adequate. For situations where reduced or modified gain and offset are required, adjustment of each is easy. The addition of two potentiometers as shown in Figure 4 provides for a two step calibration. Offset should be adjusted first. Gain adjustment does not interfere with offset. The potentiometer's TCR adds only 2% to overall temperature drift. The offset and gain adjustment procedures are as follows: 1. Set VIN to 0V and adjust R1 to desired offset at the output. A tradeoff can be achieved between the required signal bandwidth and system dynamic range. The noise floor of the output limits the dynamic range of the output signal. The 2. Set VIN to full scale (not zero). Adjust R2 for desired gain. (R) 9 ISO102/106 PRINTED CIRCUIT BOARD LAYOUT The distance across the isolation barrier, between external components, and conductor patterns, should be maximized to reduce leakage and arcing at high voltages. Good layout techniques that reduce stray capacitance will assure low leakage current and high AC IMR. For some applications, applying conformal coating compound such as urethane is useful in maintaining good performance. This is especially true where dirt, grease or moisture can collect on the PC board surface, component surface, or component pins. Following this industry-accepted practice will give best results, particularly when circuits are operated or tested in a moisture-condensing environment. Optimum coating can be achieved by administering urethane under vacuum conditions. This allows complete coverage of all areas. Grounded rings around the Cl and C2 contacts on the board greatly reduce high voltage electric fields at these pins. Y-Connected Power Transformer +5V 1 -15V +5V 1 120Vrms 100A 21 0.005 Power Resistor 0.5V 0.001F 22 10 INA110 10 +5V 1 -5V 1 21 +5V 1 1-5V 24 1 12 R 22 2 750V B1 13 14 +720V ISO 102 16 12V 10 MPC8S 1 ISO 13 ADC574 Multiplexer 16 4 Digital Ground Analog Ground Plane 60 Address Selects Battery to be Measured FIGURE 7. Battery Monitor for High Voltage Charging Circuit. Power Supply FIGURE 5. Isolated Power Current Monitor for Motor Circuit. (The ISO102 allows reliable, safe measurement at high voltages.) (R) ISO102/106 102 VOUT Monitor to ADC and Computer B 60 Data Bus 10 1V 0.01 4 FIGURE 6. Isolated Power Line Monitor (0.5A leakage current at 120Vrms). 12 14 14 16 6 +5V 1 1-5V 102 VOUT 102 2 +708V ISO ISO 7 1 4 2 13 Differential input accurately senses power resistor voltage. Two resistors protect INA110 from open power resistor. High frequency spike reject filter has fCO = 400Hz. Figures 5 through 15 show a variety of application circuits. Additional discussion of applications can be found in the December 11, 1986 issue of Electronic Design, pages 91-96. VIN 9 -15V The ISO102 and ISO106 isolation amplifiers are used in three categories of applications: 1. accurate isolation of signals from high voltage ground potentials, 2. accurate isolation of signals from severe ground noise, and 3. fault protection from high voltages in analog measurement systems. 22 1 12 2 200k APPLICATIONS +500VDC +5V 1 -5V 1 100A 24 1 21 24 8 200k +5V 1 1- 5V 10 +5V 1 -5V 1 Thermometrics Thermistor B43KB753F +5V Ref. +5V 1 1-5V +5V Reference 5 40 1 37 133.3k 206.9k 69.76k 20 ISO V OUT +15V -15V 18 25k 4 -15V 37 1 3 +15V -15V 24 24 4 +15V 1- 5V 12 2 PGA102 15 FIGURE 10. Isolation Amplifier with Isolated Bipolar Input Reference. AO A1 1 21 1 8 VIN 22 1 06 VOUT VIN Digital Optocoupler 4 21 18 FIGURE 8. Isolated RTD Temperature Amplifier. 7 20 38 2 30C 86F 6 1 ISO 0.5V 0 10C 50F +15V 1- 5V 40 INA105 24 2.5V 2 -5V Reference 4 V OUT 25k 6 22 106 +0.5V to +2.5V 1/2 LM358 75k 25k 21 38 2 +15V 7 13 22 ISO 14 102 2 VOUT 5 16 3 10 4 FIGURE 9. Programmable-Gain Isolation Channel with Gains of 1, 10, and 100. Bridge Rectifier PWS740-3 Transformer PWS740-2 Oscillator/Driver PWS740-1 T +VCC T +15V Input Common* -15V Power to Other 7 Channels 0.1F 0.1F 1 Channel 1 100H/0.1 +15V 1F 0.33F 4 24 ISO 14 1 02 2 4 16 10 13 21 22 Input From Other 7 Channels +5V Reference Out *Supplies 15mA (35mA max) of isolated supply current per channel. -15V Offset Uses 8 ISO102s, 1 isolator/driver, 8 transformers, and 8 rectifiers. 5 6 7 12 11 10 9 -15V 13 1 16 MPC8S 12 VIN1 8 A0 A1 VOUT Analog Ground Digital Ground 3 14 FIGURE 11. Low Cost Eight-Channel Isolation Amplifier Block with Channel-to-Channel Isolation. (R) 11 ISO102/106 +15V -15V +15V -15V +15V 1- 5V 24 IN914 K Thermocouple 12 4 +In 100 RG 4990 1M 5 10 11 1 21 2 13 22 1 INA101G or P 12 ISO 14 102 2 VOUT 10 14 -In 16 3 13 4 15k -15V +15V Ground Loop Through Conduit FIGURE 12. Thermocouple Amplifier with Ground Loop Elimination, Cold Junction Compensation, and Upscale Burn-out. +15V 4 Isolated Power 1mA Zero Adjust +15V +VCC Twisted 11 0.02F -1V to 10 e1 Pair -5V 3 8 0.01F 50k 5 XTR10 1 10k 250 6 I OUT 7 4 +15V 4mA to 2500 20mA 0.1F 7 2 0.01F 2 OPA27 OPA27 6 3 3 4 0.1F 1k VOUT = C (Temperature) 100C/V -15V 0V to +10V 25k 725A 500 21 23 0.1F 5k Gain Adjust +15V 0.1F 7 16 ISO 12 14 102 VOUT 10 24 6 Digital Ground 12 1 Analog Ground 13 4 0.1F -15V 4 0.1F 0.1F +15V -15V Isolated FIGURE 13. Remote Isolated Thermocouple Transmitter with Cold Junction Compensation. ISO102/106 +15V 1F 0.33F 14 3 +15V (R) 20H/0.2 Offset Adjust 153.9 2k 51 20 Type J PWS 1 -15V 1mA 16 32 Isolated DC/DC Isolation Barrier 20H/0.2 PWS PWS PWS PWS PWS 725A 726A 740 745 750 +15V 1F 0.33F Gnd Common1 2.7mA 16.7mA 0.1F -15V 14mA 680 +15V 12 9 15 300 -15V V IN 10 VB INA102 7 14 11 ISO ISO VOUT 102 106 Instrumentation Amplifier (A V = 1000) +5V VREF1 Out 5 VOUT = 1 00 x V B Digital Ground 6 VISO Analog Ground FIGURE 14. Isolated Instrumentation Amplifier for 300 Bridge. (Reference voltage from isolation amplifier is used to excite bridge.) 5V Reference 1mV +VCC1 Calibration Left Arm 300k On Calibration Right Arm NE2H 300k On 50k +VCC1 500pF 200pF 50k -VCC1 15 4 7 5 6 14 500pF +VCC1 38 Calibration 13 INA102 11 10 39F 4 VOUT 22 106 18 0.082F 24 20 C1 1V/mV +VCC2 1 -VCC1 32 0.039F +VCC1 20 PWS 726A 7 180k 6 NE2H ISO 17 2 Right Leg 23 8 Gain = 1000 300k C2 21 On 100k +VCC1 -VCC2 2 0.0082F -VCC1 -VCC1 37 40 0.0082F 12 9 NE2H 1k +VCC1 5M OPA121 NOTE: Diodes are IN4148. 3 4 1 -VCC1 -VCC1 4 14 16 1F 20H 0.3F +VCC2 FIGURE 15. Right-Leg-Driven ECG Amplifier (with defibrillator protection and calibrator). (R) 13 ISO102/106 AN ERROR ANALYSIS OF THE IS0102 IN A SMALL SIGNAL MEASURING APPLICATION Some Observations The total errors of the op amp and the ISO amp combined are approximately 0.11% of full-scale range (see Figure 17). If the op amp had not been used to preamplify the signal, the errors would have been 2.6% of FSR. Clearly, the small cost of adding the op amp buys a large performance improvement. Optimum performance, therefore, is obtained when the full 10V range of the IS0102/106 is utilized. High accuracy measurements of low-level signals in the presence of high isolation mode voltages can be difficult due to the errors of the isolation amplifiers themselves. This error analysis shows that when a low drift operational amplifier is used to preamplify the low-level source signal, a low cost, simple and accurate solution is possible. The rms noise of the IS0102 with a 120Hz bandwidth is only 0.18mVrms, which is only 0.0018% of the 10V full scale output. Therefore, even though the 16V/ Hz noise spectral density specification may appear large compared to other isolation amplifiers, it does not turn out to be a significant error term. It is worth noting that even if the bandwidth is increased to 10kHz, the noise of the iso amp would only contribute 0.016%FSR error. In the circuit shown in Figure 16, a 50mV shunt is used to measure the current in a 500VDC motor. The OPA27 amplifies the 50mV by 200 x to 10V full scale. The output of the OPA27 is fed to the input of the IS0102, which is a unity-gain isolation amplifier. The 5k and 1k potentiometers connected to the IS0102 are used to adjust the gain and offset errors to zero as described in Discussion of Specifications. Input Power Supply +15V -15V RF 200k +15V +V CC1 +500VDC 7 R1 1 2 +V CC1 +15V Offset Adjust Gain Adjust 8 OPA27 6 Offset Adjust 3 4 -V CC1 +V CC2 +15V -V CC2 -15V 0.1F 0.1F 1 V IN 2 12 13 3 5k 1 k Reference1 21 ISO Offset 22 -15V 14 102 VOUT 9 15 Offset Adjust 23 VD -15V 24 0.1F 10k +15V -V CC1 -15V 0.1F 1k Output Power Supply 10 16 C2 Bandwidth Control 0.04F C1 0.022F Input Common V D = 50mVDC (FS) V ISO 500VDC DC Motor FIGURE 16. 50mV Shunt Measures Current in a 500VDC Motor. (R) ISO102/106 14 Output Common The Errors of the Op Amp at 25C (Referred to Input, RTI) VE (OPA) = VD 1 { 1-1+ } 1 + VOS (1 + R1 /RF ) + IB R1 + P.S.R. + Noise AVOL VE (OPA) = Total Op Amp Error (RTI) VD = Differential Voltage (Full Scale) Across Shunt 1 1-1+ 1 = Gain Error Due to Finite Open Loop Gain AVOL { } = Feedback Factor AVOL = Open Loop Gain at Signal Frequency VOS = Input Offset Voltage IB = Input Bias Current P.S.R. = Power Supply Rejection (V/V) [Assuming a 5% change with 15V supplies. Total error is twice that due to one supply.] Noise = 5nV/ Hz (for 1k source resistance and 1kHz bandwidth) ERROR(OPA) (RTI) GAIN ERROR { 1 } OFFSET P.S.R. NOISE {0.025mV (1 + 1/200) + 40 x 10-9 x 103} (20V/V x 0.75V x 2) {5nV120 (nVrms)} VE (OPA) = = 0.01mV (0.0251mV + 0.04mV) + 0.03mV Error as % of FSR = 0.02% + (0.05% + 0.08%) + 0.06% = 0.01mV + (0mV + 0mV) + 0.03mV = 0.10mV + (0% + 0%) + 0.06% 50mV 1-1+ 1 106 /200 + 0.055 x 10-3mVrms + 0.00011% After Nulling Error as % of FSR* = 0.02% = 0.08% of 50mV + 0.055 x 10-3mVrms + 0.00011% *FSR = Full-Scale Range. 50mV at input to op amp, or 10V at input (and output) of ISO amp. The Errors of the Iso Amp at 25C (RTI) VE (ISO) = 1/200 (VISO / IMR + VOS + G.E. + Nonlinearity + P.S.R. + Noise) VE (ISO) = Total ISO Amp Error IMR = Isolation Mode Rejection VOS = Input Offset Voltage VISO = VIMV = Isolation Voltage = Isolation Mode Voltage G.E. = Gain Error (% of FSR) Nonlinearity = Peak-to-peak deviation of output voltage from best-fit straight line. It is expressed as ratio based on full-scale range. P.S.R. = Change in VOS /10V x Supply Change Noise = Spectral noise density x bandwidth. It is recommended that bandwidth be limited to twice maximum signal bandwidth for optimum dynamic range. ERROR(ISO) (RTI) VE (ISO) IMR { 500VDC/140dB 1/200 { 0.05mV VOS G.E. NONLINEARITY P.S.R. NOISE 1.4mV x 0.75V x 2 + 16V120 (rms) = 1/200 + 70mV + 20V x 0.25/100 + 0.003/100 x 20V = + 70mV + 50mV + 0.6mV + 2.1mV + 0.175mVrms + 0.7% + 0.5% + 0.006% + 0.021% + 0.00175% + 0mV + 0mV + 0.6mV + 2.1mV + 0.175mVrms + 0% + 0% + 0.006% + 0.021% + 0.00175% Error as % of FSR = 0.0005% } } After Nulling VE (ISO) = = 1/200 { 0.05mV = 0.03mV Error as % of FSR = 0.0005% = Total Error } 1/200 (3.0mV) 0.03% of 50mV = VE (OPA) + VE (ISO) = 0.10mV + 0.03mV = 0.08% of 50mV = 0.11% of 50mV + 0.03% of 50mV FIGURE 17. Op Amp and Iso Amp Error Analysis. (R) 15 ISO102/106 PACKAGE OPTION ADDENDUM www.ti.com 25-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ISO102 NRND CDIP SB JVE 16 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type ISO102B NRND CDIP SB JVE 16 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type ISO106 NRND CDIP SB JVD 16 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type ISO106B NRND CDIP SB JVD 16 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. 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