1
ISL8120IR
Dual/n-Phase Buck PWM Controller with
Integrated Drivers
The ISL8120IRZEC integrates two voltage-mode
synchronous buck PWM controllers to control a dual
independent voltage regulator or a 2-phase single output
regulator. It has PLL circuits and can output a phase-shift-
programmable clock signal for the system to be expanded to
3-, 4-, 6-, 12- phases with desired interleaving phase shift. It
also integrates current sharing control for the power module
to operate in parallel, which offers high system flexibility.
It has voltage feed forward compensation to maintain a
constant loop gain for optimal transient response, especially
for applications with a wide input voltage range. Its
integrated high speed MOSFET drivers and multi- feature
functions provide complete control and protection for a
2/n-phase synchronous buck converter, dual independent
regulators, or DDR tracking applications (VDDQ and VTT
outputs).
The output voltage of a ISL8120IRZEC-based converter can be
precisely regulated to as low as the internal reference voltage
0.6V, with a system accuracy of ±0.9% over industrial
temperature and line load variations. Channel 2 can track an
external ramp signal for DDR/tracking applications.
The ISL8120IRZEC integrates an internal linear regulator,
which generates VCC from input rail for applications with
only one single supply rail. The internal oscillator is
adjustable from 150kHz to 1.5MHz, and is able to track an
external clock signal for frequency synchronization and
phase paralleling applications. The integra ted Pre-Biased
Digital Soft-St art, Dif ferential Remote Sensing Amplifier, and
Programmable Input Voltage POR features enhance the
value of ISL8120IRZEC.
The ISL8120IRZEC protects against overcurrent conditi ons
by inhibiting the PWM operation while monitoring the current
with rDS(ON) of the lower MOSFET, DCR of the output
inductor, or a precision resistor. It also has a PRE-POR
Overvoltage Protection option, which provides some
protection to the load device if the upper MOSFET(s) is
shorted. See “PRE-POR Overvoltage Protection (PRE-POR-
OVP)” on page 24 for details.
The ISL8120IRZEC’s Fault Hand Shake feature protects any
channel from overloading/stressing due to system faults or
phase failure. The undervoltage fault protection features are
also designed to prevent a negative transient on the output
voltage during falling down. This eliminates the Schottky
diode that is used in some systems for protecting the load
device from reversed output voltage damage.
Features
• Full Traceability Through Assembly and Test by
Date/Trace Code Assignment
• Enhanced Process Change Notification per MIL-PRF-38535
• Enhanced Obsolescence Management
• Wide VIN Range Operation: 3V to 22V
- VCC Operation from 3V to 5.60V
• Fast Transient Respon se
- 80MHz Bandwidth Error Amplifier
- Voltage-Mode PWM Leading-Edge Modulation Control
- Voltage Feed-Forward
• Dual Channel 5V High Speed 4A MOSFET Ga te Drivers
- Internal Bootstrap Diodes
• Internal Linear Regula tor Provides a 5.4V Bias from VIN
• External Soft-Start Ramp Reference Input for
DDR/Tracking Applications
• Excellent Output Voltage Regulation
- 0.6V ±0.6%/±0.9% Internal Reference Over Industrial
Temperature
- True Differential Remote Voltage Sensing
• Oscillator Programmable from 150kHz to 1.5MHz
• Frequency Synchronization
• Scale for 1-, 2-, 3-, 4-, 6-, up to 12- Phase with Single
Output
- Excellent Phase Current Balanc ing
- Programmable Phase Shift Between the 2 Phases
Controlled by the ISL8120IRZEC and Programmable
Phase Shift for Clockout Signal
- Interleaving Operation Results in Minimum Input RMS
Current and Minimum Output Ripple Cu rrent
• Fault Hand Shake Capability for High System Reliability
• Overcurrent Protection
- DCR, rDS(ON), or Precision Resistor Current Sensing
- Independent and Average Phase Current OCP
• Output Overvoltage and Undervoltage Protections
• Programmable Phase Shift in Dual Mode Operation
• Digital Soft-S t art with Pre-Charged Output S t art-up Capability
• Power-Good Indication
• Dual Independent Channel Enable Inputs with Precision
Voltage Monitor and Voltage Feed-Forward Capability
- Programmable In put Voltage POR and its Hysteresis
with a Resistor Divider at EN Input
• Over-Temperature Protection
• Pre-Power-On-Reset Overvoltage Protection Option
• 32 Ld 5x5 QFN Package - Near Chip-Scale Footprint
- Enhanced Thermal Performance for MHz Applications
• Pb-Free (RoHS compliant)
FN6763.2Data Sheet November 11, 2011
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6763.2
November 11, 2011
ISL8120IR
Applications
• Power Supply for Datacom/Telecom and POL
• Paralleling Power Module
• Wide and Narrow Input Voltage Range Buck Regulators
• DDR I and II Applications
• High Current Density Power Supplies
• Multiple Outputs VRM and VRD
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packag es”
Pinout ISL8120IRZEC
(32 LD QFN)
TOP VIEW
Ordering Information
PART
NUMBER
(Note) PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
(Pb-free) PKG.
DWG. #
ISL8120IRZEC ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
ISL8120IRZ-TEC* ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 ter mination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FB1
VMON1
VSEN1-
VSEN1+
ISEN1B
ISEN1A
VCC
BOOT1
COMP2
FB2
VMON2
VSEN2-
VSEN2+
ISEN2B
ISEN2A
VIN
COMP1
ISET
ISHARE
EN/VFF1
FSYNC
EN/VFF2
CLKOUT/REFIN
PGOOD
UGATE1
PHASE1
LGATE1
PVCC
LGATE2
PHASE2
UGATE2
BOOT2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
910111213141516
33
GND
3FN6763.2
November 11, 2011
ISL8120IR
Block Diagram (1/2)
BOOT1
UGATE1
PHASE1
FB1
COMP1
LGATE1
E/A1
PVCC
VCC
GATE
CONTROL
INTERNAL
REFERENCE
EN/FF1
PGOOD
PGOOD
COMP1
VMON1
VIN
LINEAR REGULATOR
OV/UV
COMP1
VSEN1+
VSEN1-
SOFT-START AND
FAULT LOGIC
OCP
VREF = 0.6V
UNITY GAIN
DIFF AMP1
POWER-ON
RESET (POR)
SAW1
ISEN1A
1V
PWM1
ICS1
CURRENT
CORRECTION
∑
+
-
PVCC
IAVG_CS
CHANNEL 1
CHANNEL 1
CURRENT
SAMPLING
700mV
VCC
ISEN1B
(BOTTOM PAD) GND
AVG_OCP
OVER-TEMPERATURE
PROTECTION (OTP)
ISHARE
105µA
7-CYCLE
DELAY
5.4V
CURRENT
CORRECTION ICSH_ERR
CHANNEL1 AVERAGE
OCP
PGOOD
VREF
OTP
ICSH_ERR
FIGURE 1. CHANNEL/PHASE 1 (VDDQ)
4FN6763.2
November 11, 2011
ISL8120IR
Block Diagram (2/2)
BOOT2
UGATE2
PHASE2
FB2
COMP2
GND
LGATE2
CHANNEL2
E/A2
PVCC
ISEN2A
GATE
CONTROL
105µA
EN/FF2
PGOOD
PGOOD
COMP2
VMON2
OV/UV
COMP2
VSEN2+
VSEN2-
FAULT LOGIC
OCP
VREF
UNITY GAIN
DIFF AMP2
POR
MASTER CLOCK
FSYNC
SAW1
k*VDDQ
∑
+
-
PWM2
CURRENT
CORRECTION
ICS2
ICS2
ICS1 +
+
IAVG
PVCC
CLKOUT/REFIN
SAW2
OSCILLATOR
GENERATOR
CHANNEL 2
SOFT-START AND
VREF2
CHANNEL 2
CURRENT
SAMPLING
700mV
VCC
RELATIVE
PHASE
CONTROL
ISEN2B
AVERAGE
CURRENT
CURRENT
SHARE
BLOCK
ISHARE
ICSH_ERR
+
-
-
IAVG_CS
ISET
AVG_OCP
OTP
7-CYCLE
DELAY
M/D CONTROL
M/D = 1: multiphase
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
ICSH_ERR = (VISARE - VISET)/GCS
0.6V =k*VDDQ
VREF
M/D = 0: DUAL OUTPUT OPERATION
IAVG_CS+15µA
IAVG_CS+15µA
M/D
CONTROL
FIGURE 2. CHANNEL/PHASE 2 (VTT)
5FN6763.2
November 11, 2011
ISL8120IR
Typical Application I (Dual Regulators with DCR Sensing and Remote Sense)
VOUT1
VOUT2
ISL8120IRZEC
Q1
Q2
COMP1
FB1
VCC
BOOT1
UGATE1
ISEN1A
LGATE1
LIN
LOUT1
CHFIN
CBOOT1
COUT1
RFB1
CF1
PHASE1
PVCC
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
+3.3 TO +22V
VMON1
VSEN1+
CSEN1 VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
ZFB1
Q3
Q4
COMP2
FB2
BOOT2
UGATE2
ISEN2A
LGATE2
LOUT2
CBOOT2
COUT2
RISEN2
RFB2
PHASE2
VSEN2- ROS2
VMON2
VSEN2+
CSEN2 VSENSE2-
VSENSE2+
10Ω
10Ω
ZCOMP2
ZFB2
VIN_F
VIN_F
CLKOUT/REFIN
ISHARE
GND
ISEN1B
CF2
ISEN2B
RISEN1
CBIN
RCC
ISET
VCC
RSET
2kΩ
2kΩ
EN2/FF2
EN1/FF1
VIN
6FN6763.2
November 11, 2011
ISL8120IR
Typical Application II (Double Data Rate I or II)
0.9V (DDR II)
0.9V
(DDR I)
1.25V
VDDQ
VTT
1.8V (DDR II)
(DDR I)
2.5V
ISL8120IRZEC
Q1
Q2
COMP1
FB1
VCC
BOOT1
UGATE1
ISEN1A
LGATE1
LIN
LOUT1
CHFIN
CBOOT1
COUT1
RFB1
CF1
PHASE1
PVCC
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
+3.3 TO +22V
VMON1
VSEN1+
CSEN1 VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
ZFB1
Q3
Q4
COMP2
FB2
BOOT2
UGATE2
ISEN2A
LGATE2
LOUT2
CBOOT2
COUT2
RISEN2
RFB2
PHASE2
VSEN2- ROS2
VMON2
VSEN2+
CSEN2 VSENSE2-
VSENSE2+
10Ω
10Ω
ZCOMP1
ZFB1
VIN_F
VDDQ Or VIN_F
CLKOUT/REFIN
GND
ISEN1B
CF2
ISEN2B
RISEN1
CBIN
(V
DDQ/2)
RCC
ISHARE
ISET
RSET
2kΩ
2kΩ
VDDQ
R
VIN
R*(VDDQ/0.6-1)
(See notes below)
Note 1: Set the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from
the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference aft er soft-start.
Note 2: Another way to set REFIN voltage is to connect VMON1 directly to REFIN pin.
1nF
(Or tie REFIN pin to VMON1 pin)
7FN6763.2
November 11, 2011
ISL8120IR
Typical Application III (2-Phase Operation with rDS(ON) Sensing and Voltage Trimming)
LIN
CHFIN CBIN
CF1
PVCC
CF2
RCC
+3V TO +22V
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
RFB1
PHASE1 VOUT1
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
VMON1/2
VSEN1+
CSEN1
VSENSE1-
VSENSE1+
10Ω
10Ω
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT2
VCC
EN/FF1,2
CLKOUT/REFIN
GND
GND
ISEN2B
FB2
ISEN1A
RISEN2
TRIM UP
PULLED TO VSENSE1-
TRIM DOWN
PULLED TO VSENSE1+
ISEN1B RISEN1
ISHARE
ISET
RSET
CF3
DNP
0Ω
VIN
ISL8120IRZEC
8FN6763.2
November 11, 2011
ISL8120IR
Typical Application IV (3-Phase Regulator with Precision Resistor Sensing)
CF1 PVCC CF2
RCC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1,2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VIN_F
VCC
LOUT3
VCC
EN/FF1,2
VSEN2+
GND
ISEN2B
FB2
ISEN1A
ZFB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V TO +22V
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT
PHASE1 VOUT
EN/FF1
VIN
VSEN1-
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
BOOT2
UGATE2
ISEN2A
LGATE2
PHASE2
VIN_F
VCC
EN/FF2
FSYNC
ISHARE
GND
VMON2
ISEN1A
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS FSYNC
CLKOUT/REFIN
CF3
VSEN2-
VSEN2+
FB2
RFB1
ROS1 CSEN1
VCC
GND
RISEN3
ISEN1B
VCC
ISEN1B
ISEN2B
RISEN2
RISEN1
RISEN1
GND
ISET
R
R
ISET
R
R
PHASE 1 AND 3
ISL8120IRZEC
ISL8120IRZEC
PHASE 2
9FN6763.2
November 11, 2011
ISL8120IR
Typical Application V (4 Phase Operation with DCR Sensing)
CF1 PVCC CF2
RCC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1,2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VIN_F
VCC
LOUT3
VCC
VSEN2+
GND
ISEN2B
FB2
ISEN1A
Z
FB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V TO +22V
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT
PHASE1 VOUT1
VIN
ROS1
PGOOD
VMON1/2
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN1,2-
VSEN1,2+
VIN_F
VCC
LOUT4
VCC
EN/FF1,2
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN_F
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS
FSYNC
CLKOUT/REFIN
CF3
PHASE 1 AND 3
PHASE 2 AND 4
RFB1
ROS1 CSEN1
2ND DIVIDER TO AVOID
SINGLE POINT FAILURE
RFB1
VCC
VCC
ISEN1B
RISEN2
RISEN4
ISEN1B
RISEN3
RISEN1
VCC
VCC
COS
ISET
R
ISET
R
R
R
ISL8120IRZEC
ISL8120IRZEC
10 FN6763.2
November 11, 2011
Typical Application VI (3-Phase Regulator with Resistor Sensing and 1 Phase Regulator)
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT3
VCC
EN/FF1, 2
VSEN2+
GND
ISEN2B
FB2
ISEN1A
ZFB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V TO +22V
ISL8120IRZEC
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT1
PHASE1 VOUT1
EN/FF1
VIN
VSEN1-
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VIN_F
VCC
LOUT4
EN/FF2
FSYNC
ISHARE
GND
VMON2
ISEN1A
VIN_F
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS FSYNC
CLKOUT/REFIN
CF3
VOUT2
VSENSE2-
VSENSE2+ VSEN2-
VSEN2+
10Ω
10Ω
ZFB2 ZCOMP2
COUT2
FB2
PHASE 1 AND 3
PHASE 2
RFB1
ROS1 CSEN1
VCC
GND
RISEN3
ISEN1B
RISEN4
VCC
VCC
ISEN1B
ISEN2B
RISEN2
RISEN1
RISEN1
ISET
R
ISET
R
R
PHASE 2
R
ISL8120IR
11 FN6763.2
November 11, 2011
ISL8120IR
Typical Application VII (6 Phase Operation with DCR Sensing)
LIN CIN
CF1 PVCC CF2
RCC
+3V TO +22V
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT6
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT6
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2 ISEN1A
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
PHASE1 VOUT1
EN/FF1, 2
VIN
VSEN1- ROS1
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT4
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
ZFB1
CSEN1
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT5
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT5
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
GND
GND PHASE 2 AND 5
PHASE 1 AND 4
PHASE 3 AND 6
VCC
VCC
VMON2
RFB1
ROS1 RFB1
ISEN1B
ISEN1B
ISEN1B RISEN1
RISEN4
RISEN2
RISEN5
RISEN3
RISEN6
R
ISET
R
ISET
R
ISET
R
GND
VIN
R
R
12 FN6763.2
November 11, 2011
ISL8120IR
Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)
CF1 PVCC CF2
RCC1
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VIN_F
VCC
LOUT2
GND
ISEN2B
ISEN1A
Z
FB1
LIN
CIN
CF4 PVCC CF5
RCC2
+3V TO +22V
ISL8120IRZEC
Q5
Q6
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
COUT2
PHASE1 VOUT2
VIN
PGOOD
VMON1/2
VSENSE2+
10Ω
10Ω
CF6
Q7
Q8
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT4
EN/FF1, 2
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN_F
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS
FSYNC
CLKOUT/REFIN
CF3
2-PHASE
2-PHASE
RFB1
ROS1 CSEN1
ISEN1B
RISEN3
RISEN4
ISEN1B
RISEN2
RISEN1
GND
ISET
R
ISET
R
R
R
COUT1
VOUT1
VSENSE1-
VSENSE1+
10Ω
10Ω
COMP1/2
VSEN1-
VSEN1+
ZCOMP2
Z
FB2
RFB2
ROS2 CSEN2 VSENSE2-
VSEN2-
VSEN2+
VCC
FB2
GND
RCSR1
RCSR2
VCC
VLOAD
MODULE #1
MODULE #2
13 FN6763.2
November 11, 2011
Typical Application VIIII (4 Outputs Operation with DCR Sensing)
COUT3
VOUT3
VSENSE3-
VSENSE3+
2Ω
2Ω
LIN CIN
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
PHASE1
EN/FF1
VIN
VSEN1-
PGOOD VMON1
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT6
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT6
EN/FF2
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
PHASE1 VOUT1
EN/FF1, 2
VIN
VSEN1- ROS1
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
2Ω
2Ω
CF3
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT4
VCC
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
ZFB1
CSEN1
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120IRZEC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT1
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT5
VCC
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
GND
GND OUTPUT 2
OUTPUT 1
OUTPUT 3 AND 4
VMON2
RFB1
ROS1 RFB1
ISEN1B
ISEN1B
ISEN1B RISEN1
RISEN4
RISEN2
RISEN5
RISEN3
RISEN6
ZCOMP2 ZFB2
VOUT2
VSENSE2-
VSENSE2+
2Ω
COUT2
2Ω
ROS2 CSEN2
RFB2
ROS3 CSEN3
RFB3
ZFB3
COUT4
VOUT4
VSENSE4-
VSENSE4+
2Ω2Ω
ROS4 CSEN4
RFB4
COMP2
ZCOMP4
ZFB3
VMON2
(PHASE 1 AND 4)
(PHASE 2 AND 5)
(PHASE 3 AND 6)
+3V TO +22V VIN
R
R
R
ISL8120IR
14 FN6763.2
November 11, 2011
Absolute Maximum Ratings Thermal Information
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT. . . . . . . . . . . . . . . . . .-0.3V to +36V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage, VBOOT - VPHASE . . -0.3V to VCC +0.3V
Input, Output or I/O Voltage. . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Recommended Operating Conditions
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Boot to Phase Voltage (Overcharged), VBOOT - VPHASE. . . . . .<6V
Industrial Ambient Temperature Range . . . . . . . . . . .-40°C to +85°C
Maximum Junction Temperature Range . . . . . . . . . . . . . . . .+125°C
Thermal Resistance (Typical Notes 1, 2) θJA(°C/W) θJC(°C/W)
32 Ld QFN Package . . . . . . . . . . . . . . 32 3.5
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Limits should be considered typical and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply VIN Current IQ_VIN VIN = 20V; VCC = PVCC; No Load;
FSW = 500kHz 11 15 20 mA
Nominal Supply VIN Current IQ_VIN VIN=3.3V;VCC = PVCC; No Load;
FSW = 500kHz 81214mA
Shutdown Supply PVCC Current IPVCC EN = 0V, PVCC = 5V 0.5 1 1.4 mA
Shutdown Supply VCC Current IVCC EN = 0V, VCC = 3V 7 10 12 mA
INTERNAL LINEAR REGULATOR
Maximum Current (Note 3) IPVCC PVCC = 4V to 5.6V 250 mA
PVCC = 3V to 4V 150 mA
Saturated Equivalent Impedance (Note 3) RLDO P-Channel MOSFET (VIN = 5V) 1 Ω
PVCC Voltage Level PVCC IPVCC = 0mA to 250mA 5.1 5.4 5.6 V
POWER-ON RESET
Rising VCC Threshold 2.85 3 V
Falling VCC Threshold 2.65 2.75 V
Rising PVCC Threshold 2.85 3.05 V
Falling PVCC Threshold 2.65 2.75 V
System Soft-Start Delay (Note 3) tSS_DLY Af ter PLL, VCC, and PVCC PORs, and
EN(s) above their thresholds 384 Cycles
ENABLE
Turn-On Threshold Voltage 0.75 0.8 0.86 V
Hysteresis Sink Current IEN_HYS 25 30 35 µA
Undervoltage Lockout Hysteresis (Note 3) VEN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V
RUP = 53.6kΩ, RDOWN = 5.23kΩ1.5 V
Sink Current IEN_SINK 15 mA
Sink Impedance REN_SINK IEN_SINK = 5mA 65 Ω
ISL8120IR
15 FN6763.2
November 11, 2011
OSCILLATOR
Oscillator Frequency Range 150 1500 kHz
Oscillator Frequency RFS = 100k, Figure 20 344 377 406 kHz
Total Variation VCC = 5V; -40°C < TA <+85°C -9 +9 %
Peak-to-Peak Ramp Amplitude ΔVRAMP VCC = 5V, VEN = 0.8V 1 VP-P
Linear Gain of Ramp Over VEN GRAMP GRAMP = ΔVRAMP/VEN 1.25
Ramp Peak Voltage VRAMP_PEAK VEN = VCC VCC - 1.4 V
Peak-to-Peak Ramp Amplitude ΔVRAMP VEN = VCC = 5.4V, RUP = 2k 3 VP-P
Peak-to-Peak Ramp Amplitude ΔVRAMP VEN = VCC = 3V; RUP = 2k 0.6 VP-P
Ramp Amplitude Upon Disable ΔVRAMP VEN = 0V; VCC = 3.5V to 5.5V 1 VP-P
Ramp Amplitude Upon Disable ΔVRAMP VEN = 0V; VCC < 3.4V VCC - 2.4 VP-P
Ramp DC Offset VRAMP_OS 1V
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP
Synchronization Frequency VCC = 5.4V (3V) 150 1500 kHz
PLL Locking Time VCC = 5.4V (3V); FSW = 400kHz; 105 µs
Input Signal Duty Cycle Range (Note 3) 10 90 %
PWM
Minimum PWM OFF Time tMIN_OFF 310 345 410 ns
Current Sampling Blanking Time (Note 3) tBLANKING 175 ns
REFERENCE
Channel 1 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets) VREF1 0.6 V
-0.7 0.7 %
Channel 2 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets) VREF2 0.6 V
-0.75 0.95 %
ERROR AMPLIFIER
DC Gain (Note 3) RL = 10k, CL = 100p, at COMP Pin 98 dB
Unity Gain-Bandwidth (Note 3) UGBW_EA RL = 10k, CL = 100p, at COMP Pin 80 MHz
Input Common Mode Range (Note 3) -0.2 VCC - 1.8 V
Output Voltage Swing VCC = 5V 0.85 VCC - 1.0 V
Slew Rate (Note 3) SR_EA RL = 10k, CL = 100p, at COMP Pin 20 V/µs
Input Current (Note 3) IFB Positive direction into the FB pin 100 nA
Output Sink Current ICOMP 3mA
Output Source Current ICOMP 6mA
Disable Threshold (Note 3) VVSEN- VCC - 0.4 V
DIFFERENTIAL AMPLIFIER
DC Gain (Note 3) UG_DA Unity Gain Amplifier 0 dB
Unity Gain Bandwidth (Note 3) UGBW_DA 5 MHz
Negative Input Source Current (Note 3) IVSEN- 100 nA
Maximum Source Current for Current
Sharing (Typical Application VIII) (Note 3) IVSEN1- VSEN1- Source Current for Current
Sharing when parallel multiple modules
each of which has its own voltage loop 350 µA
Input Impedance RVSEN+_to
_VSEN- 1MΩ
Output Voltage Swing (Note 3) 0 VCC - 1.8 V
Input Common Mode Range (Note 3) -0.2 VCC - 1.8 V
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL8120IR
16 FN6763.2
November 11, 2011
Disable Threshold (Note3) VVSEN- VMON1,2 = Tri-State VCC - 0.4 V
GATE DRIVERS
Upper Drive Source Resistance RUGATE 45mA Source Current 1.0 Ω
Upper Drive Sink Resistance RUGATE 45mA Sink Current 1.0 Ω
Lower Drive Source Resistance RLGATE 45mA Source Current 1.0 Ω
Lower Drive Sink Resistance RLGATE 45mA Sink Current 0.4 Ω
OVERCURRENT PROTECTION
Channel Overcurrent Limit (Note 3) ISOURCE VCC = 3V to 5.6V 108 µA
Channel Overcurrent Limit ISOURCE VCC = 5V 89 108 122 µA
Share Pin OC Threshold VOC_SET VCC = 3V to 5.6V
(comparator offset included) 1.16 1.20 1.22 V
Share Pin OC Hysteresis (Note 3) VOC_SET_HYS VCC = 3V to 5.6V
(comparator offset included) 50 mV
CURRENT SHARE
Internal Balance Accuracy (Note 3) VCC = 3V and 3.6V, 1% Resistor
Sense, 10mV Signal ±5 %
Internal Balance Accuracy (Note 3) VCC = 4.5V and 5.6V, 1% Resistor
Sense, 10mV Signal ±5 %
External Current Share Accuracy (Note 3) VCC = 3V and 5.6V, 1% Resistor
Sense, 10mV Signal ±5 %
POWER GOOD MONITOR
Undervoltage Falling Trip Point VUVF Percentage Below Reference Point -15 -13 -11 %
Undervoltage Rising Hysteresis VUVR_HYS Percentage Above UV Trip Point 4 %
Overvoltage Rising Trip Point VOVR Percentage Above Reference Point 11 13 15 %
Overvoltage Falling Hysteresis VOVF_HYS Percentage below OV Trip Point 4 %
PGOOD Low Output Voltage IPGOOD = 2mA 0.35 V
Sinking Impedance IPGOOD = 2mA 70 Ω
Maximum Sinking Current (Note 3) VPGOOD < 0.8V 10 mA
OVERVOLTAGE PROTECTION
OV Latching Up Trip Point EN/FF= UGATE = LATCH Low,
LGATE = High 118 120 122 %
OV Non-Latching Up Trip Point (Note 3) EN/FF = Low, UGATE = Low,
LGATE = High 113 %
LGATE Release Trip Point EN/FF = Low/HIGH, UGATE = Low,
LGATE = Low 87 %
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip (Note 3) 150 °C
Over-Temperature Release Threshold
(Note 3) 125 °C
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are
100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are
not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL8120IR
17 FN6763.2
November 11, 2011
Functional Pin Description
GND (Pin 33, Signal and Power Ground Pad)
All voltage levels are referenced to this pad.This pad
provides a return path for the low-side MOSFET drives and
internal power circuitries as well as all analog signals.
Connect this pad to the circuit ground using the shortest
possible path (more than 5 to 6 via to the internal ground
plane, placed on the soldering pad are recommended).
VIN (Pin 16, Internal Linear Regulator Input)
This pin should be tied directly to the input rail when using
the internal linear regulator. It provides power to the internal
linear drive circuitry. When used with an external 5V supply,
this pin should be tied directly to PVCC. The internal lin ear
device is protected against reverse bias generated by the
remaining charge of the decoupling capacitor at PVCC when
losing the input rail.
VCC (Pin 26, Analog Circuit Bias)
This pin provides power for the analog circuitry. A RC filter is
recommended between the connection of this pin to a 3V to
5.6V bias (typically PVCC). R is suggested to be a 5Ω
resistor. And in 3.3V applications, the R could be shorted to
allow the low end input in concerns of the VCC falling
threshold. The VCC decoupling cap C is strongly
recommended to be as large as 10µF ceramic capacitor.
This pin can be powered either by the internal linear
regulator or by an external voltage source.
BOOT1, 2 (Pins 25, 17)
This pin provides the bootstrap bias for the high-side driver.
Internal bootstrap diodes connected to the PVCC pin provide
the necessary bootstrap charge. Its typical operational
voltage range is 2.5V to 5.6V.
UGATE1 , 2 (Pi n 24, 8)
These pins provide the drive for the high-side devices and
should be connected to the MOSFETs’ gates.
PHASE1, 2 (Pins 23,19)
Connect these pins to the source of the high-side MOSFETs
and the drain of the low-side MOSFETs. These pins
represent the return path for the high-side gate drives.
PVCC (Pin 21, Driver Bias Voltage)
This pin is the output of the internal series linear regulator. It
provides the bias for both low-side and high-side drives. Its
operational voltage range is 3V to 5.6V. The decoupling
ceramic capacitor in the PVCC pin is 10µF.
LGATE1, 2 (Pins 22, 20)
These pins provide the drive for the low-side devices and
should be connected to the MOSFETs’ gates.
FSYNC (Pin 5)
The oscillator switching frequency is adjusted by placi ng a
resistor (RFS) from this pin to GND. The internal oscillator
will lock to an external frequency source if this pin is
connected to a switching square pulse waveform, typically
the CLKOUT input signal from another ISL8120IRZEC or an
external clock. The internal oscillator synchronizes with the
leading edge of the input signal.
EN/FF1, 2 (Pins 4, 6)
These are triple function pins. The input voltages to these
pins are compared with a precision 0.8V reference and
enable their digital soft-starts. By pulling this pin to voltage
lower than the threshold, the correspondin g channel can be
disabled independently. Connecting these pins to input bus
through a voltage resistor divider can monitor the input
voltage. The undervoltage lockout and its hysteresis levels
can be programmed by setting the values of the resistor
dividers. The voltages on these pins are also fed into
controller to be used to adjust the amplitud e of each
individual sawtooth indepe ndently.
Furthermore, during fault (such as overvoltage, overcurrent,
and over-temperature) conditions, these pins (EN/FF _) are
used to communicate the information to other cascaded ICs
by pulling low.
PGOOD (Pin 8)
Provides an open drain Power-Good signal when both
channels are within 9% of nomina l output regulation point
with 4% hysteresis (13%/9%) and soft-start is complete.
PGOOD monitors the outputs (VMON1/2) of the internal
differential amplifiers.
ISEN1A, 2A (Pins 27, 15)
These pins ar e th e po si ti ve in pu ts of the current sensi n g
amplifier. Together with ISEN1B,2B, these pins provide
rDS(ON), DCR, or precision resistor current sensing.
ISEN1B, 2B (Pins 28, 14)
These pins are the negative inputs of the current sensing
amplifier. Together with the ISEN1A, 2A pins they provide
rDS(ON), DCR, or precision resistor current sensing. Refer to
“Typical Application III (2-Phase Operation with rDS(ON)
Sensing and Voltage Trimming)” on page 7 for rDS(ON)
sensing set up and “Typical Application V (4 Phase
Operation with DCR Sensing)” on page 9 for DCR sensing
set-up.
ISET (Pin 2)
This pin sources an 15µA offset current plus the average
current of both channels in multiphase mode or only
Channel 1’s current in independent mode. The voltage
(VISET) set by an external resistor (RISET) represents the
average current level of the local active channel(s). VISET is
compared with a 1V threshold for average overcurrent
protections. For full-scale current, RISET should be
1V/120µA = 8.33kΩ. Typically 10kΩ is used for RSET.
ISL8120IR
18 FN6763.2
November 11, 2011
ISHARE (Pin 3)
This pin is used for current sharing purposes and is
configured to current share bus representing all modules’
average current. It sources 15µA offset current plus the
average current of both channels in multiphase mode or
Channel 1’s current in independent mode. The share bus
(ISHARE pins connected together) voltage (VISHARE) set by
an external resistor (RISHARE) represents the average
current level of all active channel(s). The ISHARE bus
voltage compares with each reference voltage set by each
RISET and generates current share error signal for current
correction block of each cascaded controller. The share bus
impedance RISHARE should be set as RISET/NCTRL (RISET
divided by number of active current sharing controllers).
CLKOUT/REFIN (Pin 7)
This pin has a dual function depending on the mode in which
the chip is operating. It provides clock signal to synchronize
with other ISL8120(s) with its VSEN2- pulled within 700mV
of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12-phase)
operation. When the VSEN2- pin is not within 700mV of
VCC, ISL8120 is in dual mode (dual independent PWM
output). The clockout signal of this pin is not available in this
mode, but the ISL8120 can be synchronized to external
clock. In dual mode, this pin works as the following two
functions:
1. An external reference (0.6V target only) can be in place
of the Channel 2’s internal reference through this pin for
DDR/tracking applications (see “Interna l Reference and
System Accuracy” on page 31).
2. The ISL8120 IRZEC operates as a dual-PWM controller
for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on
REFIN (see “DDR and Dual Mode Operation” on
page 30).
FB1, 2 (Pins 32, 10)
These pins are the inverting inp uts of the error amplifiers.
These pins should be connected to VMON1, 2 with the
compensation feedback network. No direct connection
between FB and VMON pins is allowed. With VSEN2- pulled
within 700mV of VCC, the corresponding error amplifier is
disabled and the amplifier’s output is high impedance. FB2 is
one of the two pins to determine the relati ve phase
relationship between the internal clock of both channels and
the CLKOUT signal. See “DDR and Dual Mode Operation”
on page 30.
COMP1, 2 (Pins 1, 9)
These pins are the error amplifier outputs. They should be
connected to FB1, 2 pins through desired compen sation
networks when both channels are operating independently.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier is disabled and its output
(COMP pin) is high impedance. Thus, in multiphase
operations, all other SLAVE phases’ COMP pins can tie to
the MASTER phase’s COMP1 pin (1st phase), which
modulates each phase’s PWM pulse with a single voltage
feedback loop. While the error amplifier is not disabled, an
independent compensation network is required for each
cascaded IC.
VSEN1+, 2+ (Pins 29, 13)
These pins are the positive inputs of the standard unity gain
operational amplifier for differential remote sense for the
corresponding channel (Channe l 1 and 2), and shou ld be
connected to the positive rail of the load/processor. These
pins can also provide precision output voltage trimming
capability by pulling a resistor from this pin to the positive rail
of the load (trimming down) or the return (typical
VSEN1-2-pins) of the load (trimming up). The typical input
impedance of VSEN+ with respect to VSEN- is 500kΩ. By
setting the resistor divider connected from the output voltage
to the input of the differential amplifier, the desired output
voltage can be programmed. To minimize the system
accuracy error introduced by the input impedance of the
diff erential ampli fier , a 100Ω or less resistor is recommended
to be used for the lower leg (ROS) of the feedback resistor
divider.
With VSEN2- pulled within 700mV of VCC, the
corresponding error amplifier is disabled and VSEN2+ is one
of the two pins to determi ne the relative phase relationship
between the internal clock of both channe ls and the
CLKOUT signal. See “DDR and Dual Mode Operati on” on
page 30 for details.
VSEN1-, 2- (Pins 30, 12)
These pins are the negative inputs of standard unity gain
operational amplifier for differential remote sense for the
corresponding regulator (Channel 1 an d 2) , and should be
connected to the negative rail of the load/processor.
When VSEN1-, 2- are pulled within 700mV of VCC, the
corresponding error amplifier and differential amplifi er are
disabled and their outputs are high impedance. Both
VSEN2+ and FB2 input signal levels determine the relative
phases between the internal controllers as well as the
CLKOUT signal. See “DDR and Dual Mode Operati on” on
page 30 for details.
When configured as multiple power modules (with
independent voltage loop) operating in parallel, in order to
implement the current sharing control, a resistor needs to be
inserted between VSEN1- pin and output voltage negative
sense point (between VSEN1- and lower voltage sense
resistor), as shown in the “Typical Application VIII (Multiple
Power Modules in Parallel with Current Sharing Control)” on
page 12. This intro duces a correction voltage for the
modules with lower load current to keep the current
distribution balanced among modules. The module with the
highest load current will automatically become the master
module. The recommended value for the VSEN1- resistor is
ISL8120IR
19 FN6763.2
November 11, 2011
100Ω and it should not be large in order to keep the unit gain
amplifier input impedance compatibility.
VMON1, 2 (Pins 31, 11)
These pins are outputs of the unity gain amplifiers. They are
connected internally to the OV/UV/PGOOD comparators.
These pins should be connected to the FB1, 2 pins by a
standard feedback network when both channels operating
independently. When VSEN1-, 2- are pulled within 700mV of
VCC, the corresponding differential amplifier is disabled and
its output (VMON pin) is high impedance. In such an event,
the VMON pin can be used as an additional monitor of the
output voltage with a resistor divider to protect the system
against single point of failure, which occurs in the system
using the same resisto r di vider for both of the UV/OV
comparator and output voltage feedback.
Modes of Operation
There are 9 typical operation modes depending upon the
signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-, FB2,
and CLKOUT/REFIN.
MODE 1: The IC is completely disabled when EN1/FF1 and
EN2/FF2 are pulled below 0.8V.
MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high
(Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pul led low
(Mode 2B), the ISL8120IRZEC operates as a single phase
regulator. the current sourcing out from the ISHARE pin
represents the first channel current plus 15µA offset current.
MODE 3: When VSEN2- is used as a ne gative sense line,
both channels’ phase shift depends upon the voltage level of
CLKOUT/REFIN. When the CLKOUT/REFIN pin is within
29% to 45% of VCC, Channel 2 delays 0° over Channel 1
(Mode 3A); when within 45% to 62% of VCC, 90°dela y
(Mode 3B); when greater than 62% to VCC, 180° delay
(Mode 3C). Refer to the “DDR and Dual Mode Operation” on
page 30.
MODE 4: When VSEN2- is used as a negative remote sense
line, and CLKOUT/REFIN is connected to a external voltage
ramp lower than the internal soft-start ramp and lower than
0.6V, the external ramp sign al will replaces Channel 2’s
internal soft-start ramp to be tracked at start-up, controller
operating in DDR mode. The controller will use the lowest
voltage among the internal 0.6V reference, the external
voltage in CLKOUT/REFIN pin and the soft-start ramp signal.
Channel 1 is delayed 60° behind Channel 2. Refer to the
“DDR and Dual Mode Operation” on page 30.
MODE 5: With VSEN2- pulled within 700mV of VCC and
FB2 pulled to ground, the internal channels are 180°
out-of-phase and operate in 2-phase single output mode
(5A). The CLKOUT/REFIN pin (rising edge) also signals out
clock with 60° phase shift relative to the Channel 1’s clock
signal (falling edge of PWM) for 6-phase operation with two
other ISL8120IRZECs (5B). When the share Pins are not
connected to each other for the three ICs in sync, two of
which can operate in Mode 5A (3 independent ou tputs can
be generated (Mode 5D)) and Modes 3 and 4 (to generate 4
independent outputs (Mode 5C)) respectively.
MODE 6: With VSEN2- pulled within 700mV of VCC, FB2
pulled high and VSEN2+ pulled low, the internal channels
(as 1st and 3rd Phase, respectively) are 240° out-of-phase
and operate in 3-phase single output mode, combined with
another ISL8120IRZEC at MODE 2B. The CLKOUT/REFIN
pin signals out 120° relative phases to the falling edge of
Channel 1’s clock signal to synchronize with the second
ISL8120IRZEC’s Channel 1 (as 2nd Phase).
MODE 7: With VSEN2- pulled within 700mV of VCC and
FB2 and VSEN2+ pulled high, the internal channels is 180°
out-of-phase. The CLKOUT/REFIN pin (rising edge) signals
out 90° relative phase to the Channel 1’s clock signal (falling
edge of PWM) to synchronize with another ISL8120 IRZEC,
which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single
output converter can be constructed with two
ISL8120IRZECs operating in Mode 5A or 7A (Mode 7A). If
the share bus is not connected between ICs, each IC coul d
generate an independent output (Mode 7B). When the
second ISL8120IRZEC operates as two independent
regulators (Mode 3) or in DDR mode (Mode 4), then three
independent output system is generated (Mode 7C). Both
ICs can also be constructed as a 3-phase converter (0°, 90°,
and 180°, not a equal phase shift for 3-phase) with a single
phase regulator (270°).
MODE 8: The output CLKOUT signal allows expansion for
12-phase operation with the cascaded sequencing as shown
in Table 1. No external clock is required in this mode for the
desired phase shift.
MODE 9: With an external clock, the part can be expanded
for 5, 7, 8, 9 10 and 1 1 phase single output operation with the
desired phase shift.
ISL8120IR
20 FN6763.2
November 11, 2011
TABLE 1.
1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, Bi-DIRECTION) MODES OF OPERATION
OUTPUT (See
Description
for Details)
OPERATION
MODE
of 2ND IC
OPERATION
MODE
of 3RD ICMODE
EN1/
FF1
(I)
EN2/
FF2
(I) VSEN2-
(I) FB2 (I) VSEN2
+ (I)
CLKOUT/REFIN
WRT 1ST
(I or O)
ISHARE (I/O)
REPRESENTS
WHICH
CHANNEL(S)
CURRENT
2ND CHANNEL
WRT 1ST (O)
(Note)
100 - - -- - - - - DISABLED
2A 0 1 ACTIVE ACTIVE ACTIVE - N/A VMON1 =
VMON2 to Keep
PGOOD Valid
--SINGLE
PHASE
2B 1 0 - - - - 1ST CHANNEL VMON1 =
VMON2 to Keep
PGOOD Valid
--SINGLE
PHASE
3A - - <VCC -
0.7V ACTIVE ACTIVE 29% to 45% of
VCC (I) 1ST CHANNEL 0° - - DUAL
REGULATOR
3B - - <VCC -
0.7V ACTIVE ACTIVE 45% to 62% of
VCC (I) 1ST CHANNEL 90° - - DUAL
REGULATOR
3C - - <VCC -
0.7V ACTIVE ACTIVE > 62% of VCC (I) 1ST CHANNEL 180° - - DUAL
REGULATOR
4 - - <VCC-
0.7V ACTIVE ACTIVE < 29% of VCC (I) 1ST CHANNEL -60° - - DDR MODE
5A - - VCC GND - 60° BOTH CHANNELS 180° - - 2-PHASE
5B - - VCC GND - 60° BOTH CHANNELS 180° 5A 5A or 7A 6-PHASE
5C - - VCC GND - 60° BOTH CHANNELS 180° 5A 5A or 7A 3 OUTPUTs
5D - - VCC GND - 60° BOTH CHANNELS 180° 5A 3 or 4 4 OUTPUTs
6 - - VCC VCC GND 120° BOTH CHANNELS 240° 2B - 3-PHASE
7A - - VCC VCC VCC 90° BOTH CHANNELS 180° 5A or 7A - 4-PHASE
7B - - VCC VCC VCC 90° BOTH CHANNELS 180° 5A or 7A - 2 OUTPUTs
(1st IC in Mode
7A)
7C - - VCC VCC VCC 90° BOTH CHANNELS 180° 3, 4 - 3 OUTPUTs
(1st IC in Mode
7A)
8 Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required 12-PHASE
9 External Clock or External Logic Circuits Required for Equal Phase Interval 5, 7, 8, 9, 10,
11, or (PHASE
>12)
NOTE: “2ND CHANNEL WRT 1ST” is referred to as “channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells”.
For example, 90° with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90°; -60° with 2ND CHANNEL WRT 1ST means channel 2 leads
channel 1 by 60°.
ISL8120IR
21 FN6763.2
November 11, 2011
VSEN2- VSEN2+ VMON2
UV/OV
700mV
VCC
FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL
DIFF ERROR
AMP2 COMP2 AMP2
COMP2
CHANNEL 1
PWM CONTROL
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
VREF2 = VREF
FB2
CLOCK GENERATOR
AND
RELATIVE PHASES CONTROL
CLKOUT/REFIN
CH1 UG (1ST IC)
D 1-D
CLKOUT (1ST IC)
CH2 UG (1ST IC)
CH2 UG (2ND IC)
50%
D
D
180°
D
CH1 UG (2ND IC)
90°
180°
CH1 UG (1ST IC)
D 1-D
CLKOUT (1ST IC)
CH2 UG (1ST IC)
CH2 UG(2ND IC, OFF, EN2/FF2 = 0)
50%
D
240°
CH1 UG (2ND IC)
120°
3-PHASE TIMING DIAGRAM (MODE 6)
D 1-D
120°
90°
4-PHASE TIMING DIAGRAM (MODE 7A)
ISL8120IR
22 FN6763.2
November 11, 2011
Functional Description
Initialization
Initially, the ISL8120IRZEC Power-On Reset (POR) circuits
continually monito r the bias voltages (PVCC and VCC) and
the voltage at EN pin. The POR function initiates soft-start
operation 384 clock cycles after the EN pin voltage is pulled
to be above 0.8V, all input supplies exceed their POR
thresholds and the PLL locking time expires, as shown in
Figure 4. The enable pin can be us ed as a voltage monitor
and to set desired hysteresis with an internal 30µA sinking
current going through an external resistor divider. The
sinking current is disengaged after the system is enabled.
This feature is especially designed for applications that
require higher input rail POR for better undervoltage
protection. For example, in 12V applications, RUP = 53.6k
and RDOWN = 5.23k will set the turn-on threshold
(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V,
with 1.6V hysteresis (VEN_HYS).
During shutdow n or fault condition s, the sof t-st art is reset
quickly while UGATE and LGATE changes states immediately
(<100ns) upon the input drop s below fall ing POR.
.
Voltage Feed-forward
Other than used as a voltage monitor described in previous
section, the voltages applied to the EN/FF pins are also fed
to adjust the amplitude of each chann el’s individual
sawtooth. The amplitude of each channel’s sawtooth is set to
1.25 times of the corresponding EN/FF voltage upon its
enable (above 0.8V). This helps to maintain a constant gain
( ) contributed by the modulator
and the input voltage to achieve optimum loop response
over a wide input voltage range. The sawtooth ramp offset
voltage is 1V (equal to 0.8V*1.25), and the peak of the
sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V
(equal to 3V); So the feed-forward voltage effective range is
typically 3x as the ramp amplitude ranges from 1V to 3V.
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at the
EN/FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could cause
the internal ramp amplitude not to synchronize with the input
bus voltage during output start-up or when recovering from
faults. It is recommended to use open drain or open collector
to gate this pin for any system delay, as shown in Figure 5.
The multiphase system can immediately turn off all ICs
under fault conditions of one or more phases by pulling all
EN/FF pins low. Thus, no bouncing occurs among channels
at fault and no single phase could carry all current and be
over stressed.
FIGURE 4. SOFT-START INITIALIZATION LOGIC
VCC POR
PVCC POR
EN1/FF1 POR
SOFT-START
HIGH = ABOVE POR; LOW = BELOW POR
OF CHANNEL 1
AND 384
VCC POR
PVCC POR
EN2/FF2 POR
SOFT-START
OF CHANNEL 2
AND
PLL LOCKING
CYCLES
384
CYCLES
FIGURE 5. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
0.8V
IEN_HYS = 30µA
RUP
RDOWN
SOFT-START
RDOWN
RUP V•EN_REF
VEN_FTH VEN_REF
–
---------------------------------------------------------------
=
VEN_FTH VEN_RTH VEN_HYS
–=
VIN
GRAMP = 1.25
LIMITER SAWTOOTH
AMPLITUDE
VΔRAMP LIMIT(VCC_FF GRAMP, VCC - 1.4V - VRAMP_OFFSET)×=
(ΔVRAMP)
EN/FF
OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1)
RUP VEN_HYS
IEN_HYS
-----------------------------
=
SYSTEM DELAY
VCC_FF
VCC
0.8V
∑
VRAMP_OFFSET = 1.0V
VCC - 1.4V
LOWER LIMIT
UPPER LIMIT
(RAMP OFFSET)
384 CLOCK
CYCLES
GMVIN DMAX ΔVRAMP
⁄⋅=
ISL8120IR
23 FN6763.2
November 11, 2011
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
Since the EN/FF pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no more
than 5mA current from EN/FF pin. Essentially, the EN/FF
pins cannot be directly connected to VCC.
Soft-start
The ISL8120IRZEC has two independent digital pre-charged
soft-start circuitry, which has a rise time inversely
proportional to the switching frequency and is determined by
an digital counter that increments with every pulse of the
phase clock. Refer to Figure 7. The full soft-start time from
0V to 0.6V can be estimated by Equation 1.
The ISL8120IRZEC has the ability to work under a
pre-charged output (see Figure 8). The output voltage would
not be yanked down during pre-charged start-up. If the pre-
charged output voltage is greater than the final target level
but prior to 1 13% setpoint, the switching will not start until the
output voltage reduces to the target voltage and the first
PWM pulse is generated (see Figure 9). The maximum
allowable pre-charged level is 113%. If the pre-charged level
is above 113% but below 120%, the output will hiccup
between 1 13% (LGATE turns on) and 87% (LGA TE turns of f)
while EN/FF is pulled low. If the pre-charged load voltage is
above 120% of the targeted output voltage, then the
controller will be latched off and not be able to power-up.
See “PRE-POR Overvoltage Protection (PRE-POR-OVP)”
on page 24 for details.
For above target pre-charged start-up, the output voltage
would not change until the end of the soft-start. If the initial
dip is below the UV level, the LGATE could be turned off. In
such an event, the body-diode drop of the low-side FET will
be sensed and could potentiali ty cause an OCP event for
rDS(ON) current sensing applications.
Power-Good
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
EN/FF1
EN/FF2
2-PHASE
EN/FF1
EN/FF2
2-PHASE
ISL8120IRZEC ISL8120IRZEC
RUP
RDOWN
VIN
RUP VEN_HYS
IEN_HYS NPHASE
⋅
----------------------------------------------------------
=
tSS 1280
fSW
-------------
=(EQ. 1)
VOUT
0.0V
tSS 1280
FSW
-------------
=
FIRST PWM PULSE
-100mV
tSS_DLY 384
FSW
------------
≈
FIGURE 7. SOFT-START WITH VOUT = 0V
SS SETTLING AT VREF + 100mV
UV VOUT
FIRST PWM PULSE
-100mV
SS SETTLING AT VREF + 100mV
FIGURE 8. SOFT-START WITH VOUT = UV
OV = 113%
VOUT TARGET VOLTAGE
FIRST PWM PULSE
FIGURE 9. SOFT -START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
-13%
-9%
VREF
+9%
+13%
VMON1, 2
UV
UV PRE-OV (NO LATCH)
< +20%
CHANNEL 2 UV/OV
END OF SS1 AND PGOOD
CHANNEL 1 UV/OV
END OF SS2 OR
+20%
GOOD GOOD
ISL8120IR
24 FN6763.2
November 11, 2011
Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulatio n will pull-down the
PGOOD pin. The Power-Good comparators monitor the
voltage on the VMON pins. The trip points are shown in
Figure 10. PGOOD will not be asserted until after the
completion of the soft-start cycle of both channels. If
Channels 1 or 2 are not used, the Power-Good can stay in
operation by connecting 2 channels’ VMON pins together.
The PGOOD pulls low upon both EN/FF’s disabling it if one
of the VMON pins’ voltage is out of the threshold window.
PGOOD will not pull low until the fault presents for three
consecutive clock cycles. In Dual/DDR application, if the
turn-off channel pre-charges its VMON within the PGOOD
threshold window, it could indicate Power-Good, however,
the PGOOD signal can pull low with an external PNP or
PMOS transistor via the EN/FF of the corresponding off
channel.
Undervoltage and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry monitor the voltage on the VMON pins. The UV
functionality is not enabled until the end of soft-start. An OV
condition (>120%) during soft-start would latch IC off.
In an UV event, if the output drops below -13% (-9% is the
hysteresis level) due to some reasons other than OV, OC,
OT, and PLL faults (EN/FF is not pulled low) of the target
level at the output voltage falling edge, the lower MOSFETs
will turn off to avoid any negative voltage ringing.
An OV event (VOUT > 120%) causes the high-side MOSFET
to latch off permanently, while the low-side MOSFET turns
on and then turns off after the output voltage drops below
87%. At the same time, the EN/FF and PGOOD are also
latched low. The latch condition can be reset only by
recycling VCC. In Dual/DDR mode, each channel is
responsible for its own OV event with the corresponding
VMON as the monitor. In multiphase mode, both channels
respond simultaneously when either triggers an OV event.
To protect the overall power trains in case of only one
channel of a multiphase system detecting OV, the low-side
MOSFET always turns on at the conditions of EN/FF = LOW
and the output voltage above 113% (all VMON pins and EN
pins are tied together) and turns off after the output drops
below 87%. Thus, in a high phase count application
(Multiphase Mode), all cascaded ICs can latch off
simultaneously via EN pins, and each IC shares the same
sink current to reduce the stress and eliminate the bouncing
among phases.
PRE-POR Overvoltage Protection (PRE-POR-OVP)
When both the VCC and PVCC are below PORs (not include
EN POR), the UGATE is low and LGATE is floating (high
impedance). EN/FF has no control on LGATE when below
PORs. When above PORs, the LGA TE would not be floating
but toggling with its PWM pulses. An external 10Ω resistor,
connected in between Phase and LGATE nodes, enables
the PRE-POR-OVP circuit. The output of the converter that
is equal to phase node voltage via output inductors is then
effectively clamped to the low-side MOSFET’s gate
threshold voltage, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted during
start-up, shutdown, or normal operations. For complete
protection, the low-side MOSFET should have a gate
threshold that is much smaller than the maximum voltage
rating of the load.
The PRE-POR-OVP works against pre-biased start-up when
pre-charged output voltage is higher than the threshold of
the low-side MOSFET, however, it can be disabled by
placing a 2k resistor from LGATE to ground.
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than
+150°C (typically), both EN/FF pins pull low to inform other
cascaded channels via their EN/FF pins. All connected
EN/FFs stay low and release after the IC’s junction
temperature drops below +125°C (typically), with a +25°C
hysteresis (typical).
FIGURE 11. FORCE LGATE HIGH LOGIC
EN/FF1
FORCE
VMON1
LGATE1
HIGH
113%
87%
EN/FF2
FORCE
VMON2
LGATE2
HIGH
113%
87%
VMON1>120%
VMON2>120%
multiphase
MODE = HIGH
OR
OR
OR
AND
AND
AND
FIGURE 12. UV AND OV TIMING DIAGRAM
UV OV LATCH
3 CYCLES
VOUT
PGOOD
UGATE AND EN/FF LATCH LOW
3 CYCLES
120%
ISL8120IR
25 FN6763.2
November 11, 2011
Current Loop
When the ISL8120IRZ E C operates in 2-phase mode, the
current control loop keeps the channel’s current in balance.
After 175ns blanking period with respect to the falling edge
of the PWM pulse of each channel, the voltage developed
across the DCR of the inductor, rDS(ON) of the low-side
MOSFETs, or a precision resistor, is filtered and sampled for
175ns. The current (ICS1/ICS2) is scaled by the RISEN
resistor and provides feedback proportional to the average
output current of each channel.
For DCR sensing, the ICS can be derived from Equation 2:
where IL is the inductor DC current, and DCR is its DC
resistance.
For low-side MOSFET rDS(ON) sensing, the ICS can be
derived from Equation 3:
In multiphase mode (VSEN2- pulled high), the scaled output
currents from both active channels are combined to create
an average current reference (IAVG) which represents
average current of both channel outputs as calculated in
Equation 4.
ISEN1B
ISEN1A
700mV
VCC DCR1 DCR2
AMP AMP
VSEN2-
∑
+
+
ISHARE
ICS2
ICS1
CURRENT
SHARE
BLOCK
IAVG
CURRENT
CORRECTION
BLOCK
CURRENT
CORRECTION
BLOCK
VSEN2+
∑
2
+
-
CHANNEL 1
PWM CONTROL
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
CHANNEL 1
SOFT-START AND
CHANNEL 2
SOFT-START AND
FAULT LOGIC
AVG_OC
COMP OC2
COMP
FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION
ITRIP = 105µA
ICSH_ERR
--
-
+
IAVG_CS
VISHARE
ISET
1.2V
RISET
ICSH_ERR = (VISARE - VISET)/GCS
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2)/2
7 CYCLES
DELAY
ITRIP=105µA
7 CYCLES
DELAY
E/A
ISEN2B
ISEN2A
RC
RISEN2
VOUT
PHASE2 IOUT2
DCR2 L2
FAULT LOGIC
CHANNEL 1
CHANNEL 2
R
C
RISEN1
VOUT PHASE1
IOUT1
DCR1
L1
VOUT PHASE1
IOUT1
L1
ISEN1A
DCR SENSING
RISEN1
ISEN1B
DCR1
rDS(ON) SENSING
OC1
COMP
IAVG_CS +15µA
IAVG_CS +15µA
ICS IL DCR•
RISEN
-------------------------
=(EQ. 2)
ICS IL rDS ON()
•
RISEN
----------------------------------
=(EQ. 3)
IAVG ICS1 ICS2+
2
-----------------------------------
=(EQ. 4)
ISL8120IR
26 FN6763.2
November 11, 2011
The signal IAVG is then subtracted from the individual
channel’s scaled current (ICS1 or ICS2) to produce a current
correction signal for each channel. The current correction
signal keeps each channel’s output current contribution
balanced relative to the other active channel.
For multiphase operation, th e share bus (VISHARE)
represents the average current of all active channels and
compares with each IC’s average current (IAVG_CS equals to
IAVG or ICS1 depending upon the configuration, represented
by VISET) to generate current share error signal (ICS_ERR)
for each individual channel. Each current correction signal is
then subtracted from the error amplifier output and fed to the
individual channel PWM circuits.
When both channels operate independently, the average
function is disabled and generates zero average current
(IAVG = 0), an d current correction block of Channel 2 is also
disabled. The IAVG_CS is the Channel 1 current ICS1. The
channel 1 makes any necessary current correction by
comparing its channel current (represented by VISET) with
the share bus (VISHARE). When the share bus does not
connect to other ICs, the ISET and ISHARE pins can be
shorted together and grounded via a single resistor to
ensure zero share error.
Note that the common mode input voltage range of the
current sense amplifiers is VCC - 1.8V. Therefore, the
rDS(ON) sensing should be used for applications with output
voltage greater than VCC - 1.8V. For example, application of
3.3V output is suggested to use rDS(ON) sensing.
In addition, the R-C network components (for DCR sensing)
are selected such that the RC time cons tant matches the
inductor L/DCR time constant. Otherwise, it could cause
undershoot/overshoot during load transient and start-up. C is
typically set to 0.1µF or higher, while R is calculated with
Equation 5.
Figure 13 shows a simple and flexible configuration for both
rDS(ON) and DCR sensing.
Current Share Control in Multiphase Single Output
The IAVG_CS is the average current of both channels (I AVG,
2-phase mode) or only Channel 1 (ICS1, any oth er modes).
ISHARE and ISET pins source a copy of IAVG_CS with 15µA
offset, for example, the full-scale will be 120µA. If one single
external resistor is used as RISHARE connecting the
ISHARE bus to ground for all the ICs in parallel, RISHARE
should be set equal to RISET/NCTRL (where NCNTL is the
number of the ISL8120IRZEC controll ers in parallel or
multiphase operations), and the share bus voltage
(VISHARE) set by the RISHARE represents the average
current of all active channels. Another way to set RISHARE is
to put one resistor in each IC’s ISHARE pin and use the
same value with RISET (RISHARE = RISET), in which case
the total equivalent resistance value is also RISET/NCTRL.
The voltage (VISET) set by RISET represents the average
current of the corresponding device and compared with the
share bus (VISHARE). The current share error signal
(ICSH_ERR) is then fed into the current correction block to
adjust each channel’s PWM pulse accordingly.
The current share function prov ides at least 10% overall
accuracy between ICs, 5% within the IC when using a 1%
resistor to sense a 10mV signal. The current share bus
works for up to 12-phase.
For multiphase implementation, one single error amplifier
should be used for the voltage loop. Therefore, all other
RL
CDCR•
------------------------
=(EQ. 5)
FIGURE 14. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION
ISHARE
CURRENT
MIRROR
BLOCK
IAVG_CS
ISET
VERROR1
+
-
ICS1
∑
-
∑
ERROR
AMP 1
VERROR2
+
-
ICS2
∑
-
∑
ERROR
AMP 2
CURRENT
MIRROR
BLOCK
IAVG_CS
700mV
VCC
VSEN2-
--
+
+
I
CSH_ERR
ICSH_ERR
SHARE BUS
RISET
RISHARE
RISHARE = RISET/NCTRL
IDROOP + 15
µ
A = IAVG_CS + 15
µ
A = ISET = ISHARE
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
ISL8120IR
27 FN6763.2
November 11, 2011
channels’ error amplifiers should be disabled with their
corresponding VSEN- pulled to VCC, as shown in Figure 15.
Current Share Control Loop in Multi-Module with
Independent Voltage Loop
The power module controlled by ISL8120IRZEC with its own
voltage loop can be paralleled to supply one common output
load with its integrated Master-Slave current sharing control,
as shown in “Typical Application VIII (Multiple Power
Modules in Parallel with Current Sharing Control)” on
page 12. A resistor RCSR needs to be inserted between
VSEN1- pin and the lower resistor of the voltage sense
resistor divider for each module. With this resistor, the
correction current sourcing from VSEN1- pin will create a
voltage offset to maintain even current sha ri ng among
modules. The recommended value for the VSEN1- resistor
RCSR is 100Ω and it should not be large in order to keep the
unity gain amplifier input pin impe dance compatibility. The
maximum source current from VSEN1- pin is 350µA, which
is combined with RCSR to determine the current sharing
regulation range. The generated correction voltage on RCSR
is suggested to be within 5% of VREF (0.6V) to avoid fault
trigging of UV/OV and PGOOD during dynamic events.
To att ain good current balance in system start up preventing
single module from overcurrent, the paralleled modules are
recommended to be synchronized and the enable pins (EN/FF)
should be tied together to initial start-up at the same instant.
Overcurrent Protection
The OCP function is enabled at start-up. When both
channels operate independently, the average function is
disabled and generates zero average current (IAVG = 0). The
Channel 2 current (ICS2) is compared with ITRIP (105µA)
and has its own independent overcurrent protection; while
the 7 clock cycles delay is bypassed. The Channel 1’s
current (ICS1) plus 15µA offset forms a voltage (VISHARE)
with an external resistor RISHARE and compares with a
precision 1.2V threshold (±1%, 50mV hysteresis); while the
105µA OCP comparator with 7-cycle delay is also activated.
In multiphase operation, the VISHARE repr esents the
average current of all active channels and compares with a
precision 1.2V threshold (±1%, 50mV hysteresis) to
determine the overcurrent condition, while each channel has
additional overcurrent trip point at 105µA with 7-cycle delay.
This scheme helps protect against loss of channel(s) in
multi-phase mode so that no single channel could carry
more than 105µA in such event. See Figure 13. Note that it
is not necessary for the RISHARE to be scaled to trip at t he
same level as the 105µA OCP comparator if the application
allows. For instance, when Channel 1 operates
independently, the OC trip set by 1.2V comparator can be
lower than 105µA trip point as shown in Equation 6.
where N is the number of phases; NCNTL is the number of
the ISL8120IRZEC controllers in parallel or multiphase
operations; ITRIP = 105µA; IOC is the load overcurrent trip
point; tMIN_OFF is the minimum Ugate turn off time that is
350ns; RISHARE in Equation 6 represents the total
equivalent resistance in ISHARE pin bus of all ICs in
multiphase or module parallel operation.
The overcurrent trip current source is trimmed to 105µA
±10% for both channels, while the overcurrent threshold
(represented by VISHARE) for multiphase operation (or
Channel 1 depending upon configuration) is a precision 1.2V
±1% with 50mV hysteresis.
For the RISEN chosen for OCP setting, the final value is
usually higher than the numbe r calculated from Equation 6.
FIGURE 15. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION
ISHARE
ISET
SHARE BUS
RISET1
RISHARE1
ISL8120IRZEC1
VSEN1/2- COM1/2
ISHARE
ISET
RISET3
RISHARE3
ISL8120IRZEC3
VSEN1/2- COM1/2
ISHARE
ISET
RISET2
RISHARE2
ISL8120IRZEC2
VSEN2- COM1/2
VCC
VSEN1+
VSEN1-
RISHARE_ = RISET_
RISEN1
IOC
N
----------VOUT
L
----------------1D–
2FSW
---------------- tMIN_OFF
–
⎝⎠
⎛⎞
•+
⎝⎠
⎜⎟
⎛⎞
DCR•
ITRIP
----------------------------------------------------------------------------------------------------------------------
=
RISHARE 1V
ITRIP
---------------
=RISET RISHARE NCNTL
⋅=
(EQ. 6)
ISL8120IR
28 FN6763.2
November 11, 2011
The reason of which is practical especially for low DCR
applications the PCB and inductor pad soldering resistance
would have large effects in total impedance affecting the
DCR voltage to be sensed.
When OCP is triggered, the controller pulls EN/FF low
immediately to turn off UGATE and LGATE. However, if the
output overshoot is greater than 113% at EN/FF = LOW,
LGATE turn s ON until the output voltage drops below 87%.
A delay time, equal to 3 soft-start intervals, is entered to
allow the disturbance to clear. After the delay time, the
controller then initiates a soft-start interval. If the output
voltage comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-st art interval, the controller pulls EN/VFF low again. The
PGOOD signal will remain low and th e soft-start interval will
be allowed to expire. Another soft-start interval will be
initiated after the delay interval. If an overcurrent trip occurs
again, this same cycle repeats until the fault is removed.
There is a100ns delay to prevent any fault triggering durin g
start-up or load transient. For a hard short of the output, the
overcurrent protection reduces the regulator RMS output
current much less than 60% of the full load current by putting
the controller into hiccup mode.
Internal Seri es Lin e ar and Power Dissipation
The VIN pin is connected to PVCC with an internal series
linear regulator (1W Typical), which is internally
compensated. The PVCC and VIN pins should have the
recommended bypasses connected to GND for proper
operation. The internal serie s linear regulator’s input (VIN)
can range between 3V to 22V. The internal linear regulator is
to provide power for both the internal MOSFET drivers
through the PVCC pin and the analog circuitry through the
VCC pin. The VCC pin should be connected to the PVCC pin
with an RC filter to prevent high frequency driver switching
noise from entering the analog circuitry. When VIN drops
below 5.0V, the pass element will saturate; PVC C will track
VIN, minus the dropout of the linear regulator. When used
with an external 5V supply, VIN pin is recommended to be
tied directly to PVCC.
The LDO is capable to supply 250mA with regulated 5.4V
output. In 3.3V input applications, when the VIN pin voltage
is 3V, the LDO still can supply 150mA while maintaining LDO
output voltage higher than VCC falling threshold to keep IC
operating. Figure 17 shows the LDO voltage drop under
different load current. However, its thermal capability should
not be exceeded. The power dissipation inside the IC could
be estimated with Equation 7.
FIGURE 16. INTERNAL REGULATOR IMPLEMENTATION
5V
Z1
3V TO 26.4V
2.65V TO 5.6V
PVCC VINVCC
Z2
2Ω
1µF
10µF
PIC VIN PVCC–()IVIN
⋅PDR
+= (EQ. 7)
IVIN QG1 NQ1
•
VGS1
------------------------------QG2 NQ2
•
VGS2
------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PVCC F•SW IQ_VIN
+•=
FIGURE 17. PVCC vs VIN VOLTAGE
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VIN PIN VOLTAGE (V)
PVCC (V)
Iq IS AROUND 15mA
PVCC @ 250mA + Iq PVCC @ 100mA + Iq
PVCC @ 140mA + Iq
ISL8120IR
29 FN6763.2
November 11, 2011
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ_VIN is the driver’s
total quiescent current with no load at drive outputs; NQ1 and
NQ2 are number of upper and lower MOSFETs, respectively.
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offs e t of 1. 0V.
Each channel’s peak-to-peak of the ramp amplitude is set to
proportional the voltage applied to its corresponding EN/FF
pin. See “Voltage Feed-forward” on page 22.
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchroni zed frequency operation. By tying a
resistor (RFSYNC) to GND from FSYNC pin, the switching
frequency can be set at any frequency between 150kHz and
1.5MHz. Frequency setting curve shown in Figure 20 are
provided to assist in selecting the correct value for RFSYNC.
By connecting the FSYNC pin to an external square pulse
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120IRZEC), the ISL8120IRZEC will
synchronize its switching frequency to the fundamental
frequency of the input waveform. The maximum voltage to
FSYNC pin is VCC + 0.3V. The Frequency Synchronization
feature will synchronize the leading edg e of CLKOUT signal
with the falling edge of Channel 1’s PWM clock signal. The
CLKOUT is not available until the PLL locks.
The locking time is typically 130µs for FSW = 500kH z.
EN/VFF1 is released for a soft-start cycle until the FSYNC
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles, the
IC is disabled until the PLL returns locking, at which point a
soft-start cycle is initiated and normal operation resumes.
Holding FSYNC low will disable the IC.
FIGURE 18. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 19. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
PDR PDR_UP PDR_LOW
+= (EQ. 8)
PDR_UP RHI1
RHI1 REXT1
+
-------------------------------------- RLO1
RLO1 REXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q1
2
---------------------
•=
PDR_LOW RHI2
RHI2 REXT2
+
-------------------------------------- RLO2
RLO2 REXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q2
2
---------------------
•=
REXT2 RG1 RGI1
NQ1
-------------
+= REXT2 RG2 RGI2
NQ2
-------------
+=
PQg_Q1 QG1 PVCC2
•
VGS1
---------------------------------------FSW
•NQ1
•=
PQg_Q2 QG2 PVCC2
•
VGS2
---------------------------------------FSW
•NQ2
•=
Q1
D
S
G
RGI1
RG1
BOOT
RHI1 CDS
CGS
CGD
RLO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
RGI2
RG2
RHI2 CDS
CGS
CGD
RLO2
GND
LGATE
FIGURE 20. RFS vs SWITCHING FREQUENCY
0
200
400
600
800
1,000
1,200
1,400
1,600
20 40 60 80 100 120 140 160 180 200 220 240 260
R_FS (kΩ)
SWITCHING FREQUENCY (kHz)
ISL8120IR
30 FN6763.2
November 11, 2011
Differential Amplifier for Remote Sense
The differential remote sense buffer has a precision unity
gain resistor matching network, which has a ultra low offset
of 1mV. This true remote sensing scheme helps compensate
the droop due to load on the positive and negative rails and
maintain the high system accuracy of ±0.6%.
The output of the remote sense buffer is connected directly
to the internal OV/UV comparator. As a result, a resistor
divider should be placed on the input of the buffer for proper
regulation, as shown in Figure 24. The VMON pin should be
connected to the FB pin by a standard feedback network.
Since the input impedance of VSEN+ pin in respect to
VSEN- pin is about 500kΩ, it is highly recommended to
include this impedance into calculation and use 100Ω or less
for the lower leg (ROS) of the feedback resistor divider to
optimize system accuracy. Note that any RC filter at the
inputs of differential amplifier will contribute as a pole to the
overall loop compensation.
As some applications will not need the differential remote
sense, the output of the remote sense buffer can be disabled
and be placed in high impedance by pulling VSEN- within
700mV of VCC. In such an event, the VMON pin can be
used as an additional monitor of the output voltage with a
resistor divider to protect the system against single point of
failure, which occurs in the system using the same resistor
divider for the UV/OV comparator and the output regulation.
The resistor divider ratio should be the same as the one for
the output regulation so that the correct voltage information
is provided to the OV/UV comparator. Figure 22 shows the
differential sense amplifier can directly used as a monitor
without pulling VSEN- high.
DDR and Dual Mode Operation
If the CLKOUT/REFIN is less than 800mV, an external
soft-s t art ramp (0.6V) can be in p arallel with the C hannel 2’s
internal soft -sta rt ramp for DDR/tracking applicati ons (DDR
Mode). The output voltage (typical VTT output) of Channel 2
tracks with the input voltage (typi cal VDDQ*(1 + k) from
Channel 1) at the CLKOUT/REFIN pin. As for the externa l
input signal and internal reference signal (ramp and 0.6V), the
one with the lowest volt age will be the one to be used as the
reference comparing with FB signal. Since the UV/OV
comparator uses the same internal reference 0.6V, to
guarantee UV/OV and Pre-charged start-up functions of
Channel 2, the target volt age derived from Channel 1 (VDDQ)
should be scaled close to 0.6V, and it is suggested to be
slightly above (+2%) 0.6V with an external resistor divi der,
which will have the Channel 2 use the internal 0.6V reference
after sof t-st art. Any cap a citive load at REFIN pin shou ld not
slow down the ramping of this input 150mV lower than the
Channel 2 internal ramp. Otherwise, the UV protection co uld
be fault triggered prior to the end of the soft-st art. The start-u p
of Channel 2 can be dela yed to avoid su ch situatio n
happening, if high cap aciti ve load presents at REFIN pin for
noise decoupli ng. During shut d own, Channel 2 will fo llow
Channel 1 until both channe ls drops below 87%, at which both
channels enter UV protection zone. Depending on the
FIGURE 21. EQUIVALENT DIFFERENTIAL AMPLIFER
20k
20k
20k
20k
RDIF = 500k
VSEN-
VSEN+
GND
VSEN+ VSEN- FB
VMON
RFB
ROS
OV/UV ERROR AMP
COMP
700mV
VCC
FIGURE 22. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION
VREF
VOUT
GAIN=1
PGOOD
PGOOD
ZCOMP
ROS
COMP
RFB
ISL8120IR
31 FN6763.2
November 11, 2011
loading, Channel 1 mi ght drop faster than Channel 2. To solve
this race condition, Channel 2 ca n either power u p from
Channel 1 or bridge the Channe l 1 with a high curren t
Schottky diode. If the system requires to shutdo wn both
channels when either has a fault, tying EN /FF1 and EN/FF2
will do the job. In DDR mode, Cha nnel 1 delays 6 0° over
Channel 2.
In Dual mode, depending up on the resistor divider level of
REFIN from VCC, the ISL8120IRZEC operates as a dual
PWM controller for two independent regulators with a phase
shift as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on-the-fly.
Internal Referen c e and Syst em Accu ra cy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differenti al and error amplifiers, it has
an accuracy of 0.9% over industrial temperature range.
While the remote sense is not used, its offset (VOS_DA)
should be included in the tolerance calculation. Equations 9
and 10 show the worst case of system accuracy calculation.
VOS_DA should set to zero when the differential amplifier is
in the loop, the differential amplifier’s input impedance
(RDIF) is typically 500kΩ with a tolerance of 20% (RDIF%)
and can be neglected when ROS is less than 100Ω. To set a
precision setpoint, ROS can be scaled by two paralleled
resistors.
TABLE 2.
MODE DECODING
REFIN RANGE PHASE for CHANNEL
2 WRT CHANNEL 1 REQUIRED
REFIN
DDR <29% of VCC -60° 0.6V
Dual 29% to 45% of
VCC 0° 37% VCC
Dual 45% to 62% of
VCC 90° 53% VCC
Dual 62% to VCC 180° VCC
700mV
FIGURE 23. SIMPLIFIED DDR IMPLEMENTAION
PHASE-SHIFTED
CLOCK
VCC
CLKOUT/REFIN
VSEN2-
VDDQ
R
kVDDQ
0.6V
------------------ 1–=
k*R
INTERNAL SS
ISL8120IRZEC
STATE
MACHINE
E/A2
0.6V
FB2
VSEN- VSEN+ COMP
FB
VMON
RFB
ROS
ZFB ZCOMP
OV/UV ERROR AMP
COMP
CSEN
700mV
VCC
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
VREF
10Ω
10Ω
VOUT (LOCAL)
GND (LOCAL)
VSENSE+ (REMOTE)
GAIN=1
VSENSE- (REMOTE)
PGOOD
PGOOD
ISL8120IR
32
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6763.2
November 11, 2011
Figure 25 shows the tolerance of various output voltage
regulation for 1%, 0.5%, and 0.1% feedback resistor
dividers. Note that the farther the output voltage setpoint
away from the internal reference voltage, the larger the
tolerance; the lower the resisto r tolerance (R%), the tighter
the regulation.
%min Vref 1 Ref%–()⋅VOS_DA
–()1RFB 1R%–()⋅
ROSMAX
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=
(EQ. 9)
ROSMAX 1
1
ROS 1R%+()⋅
----------------------------------------- 1
RDIF 1R
DIF%+()⋅
----------------------------------------------------
+
-----------------------------------------------------------------------------------------------------
=
%max Vref 1 Ref%–()⋅VOS_DA
–()1RFB 1R%–()⋅
ROSMIN
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=
(EQ. 10)
ROSMIN 1
1
ROS 1R–%()⋅
---------------------------------------1
RDIF 1R
DIF
–%()⋅
-------------------------------------------------
+
-----------------------------------------------------------------------------------------------
=FIGURE 25. OUTPUT REGULA TION WITH DIFFERENT
RESISTOR TOLERANCE FOR REF% = ±0.6%
OUTPUT REGULATION (%)
OUTPUT VOLTAGE (V)
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
1%
0.5%
0.5%
0.1%
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
R% = 1%
0.1%
ISL8120IR
33 FN6763.2
November 11, 2011
ISL8120IR
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
located within the zone indicated . Th e pin #1 identifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
5.00 A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
32X 0.40 ± 0.10 4
A
32X 0.23
M0.10 C B
16 9
4X
0.50
28X
3.5
6
PIN #1 INDEX AREA
3 .30 ± 0 . 15
0 . 90 ± 0.1 BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10 C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 30 )
( 4. 80 TYP ) ( 28X 0 . 5 )
(32X 0 . 23 )
( 32X 0 . 60)
+ 0.07
- 0.05
17
25
24
8
1
32
