High Reliability Series Serial EEPROM Series I2C BUS Serial EEPROMs BR24G -3A Series BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A, BR24G16-3A, BR24G32-3A, BR24G64-3A, BR24G128-3A, BR24G256-3A, BR24G512-3A, BR24G1M-3A :BR24G01/02/04/08/16/32/64/512/1M-3A are model, the description matters are target all specifications because of the model under development. ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a failsafe method of data reliability, while a double reset function prevents data miswriting, pushing the boundaries of reliability to the limit. Contents BR24G -3A Series BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A, BR24G16-3A, BR24G32-3A, BR24G64-3A, BR24G128-3A, BR24G256-3A, BR24G512-3A, BR24G1M-3A www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 1/20 2012.2 - Rev.C BR24G -3A Series Technical Note I2C BUS Serial EEPROMs BR24G -3A Series BR24G01-3A, BR24G02-3A, BR24G04-3A, BR24G08-3A, BR24G16-3A, BR24G32-3A, BR24G64-3A, BR24G128-3A, BR24G256-3A, BR24G512-3A, BR24G1M-3A Description 2 BR24G-3A series is a serial EEPROM of I C BUS interface method Features All controls available by 2 ports of serial clock(SCL) and serial data(SDA) Other devices than EEPROM can be connected to the same port, saving microcontroller port 1.7V5.5V single power source action most suitable for battery use 1.7V5.5wide limit of action voltage, possible 1MHz action Page write mode useful for initial value write at factory shipment Auto erase and auto end function at data write Low current consumption Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various package Data rewrite up to 1,000,000 times Data kept for 40 years Noise filter built in SCL / SDA terminal Shipment data all address FFh BR24G series Capacity Bit format 1Kbit 2Kbit 4Kbit 8Kbit 16Kbit 32Kbit 64Kbit 128Kbit 256Kbit 512Kbit 1024Kbit 128x8 256x8 512x8 1Kx8 2Kx8 4Kx8 8Kx8 16Kx8 32Kx8 64Kx8 128Kx8 Type BR24G01-3A BR24G02-3A BR24G04-3A BR24G08-3A BR24G16-3A BR24G32-3A BR24G64-3A BR24G128-3A BR24G256-3A BR24G512-3A BR24G1M-3A Power source Voltage 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V 1.75.5V VSON008 DIP-T8 SOP8 SOP-J8 SSOP-B8 TSSOP-B8 TSSOP-B8J MSOP8 X2030 :Developing www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 2/20 2012.2 - Rev.C BR24G -3A Series Technical Note Absolute maximum ratings (Ta=25) Parameter symbol Impressed voltage VCC Memory cell characteristics (Ta=25, Vcc=1.75.5V) Limits Unit -0.3+6.5 V 450 (SOP8) 450 (SOP-J8) *2 330 (TSSOP-B8) Pd 310 (MSOP8) Data hold years *4 310 (TSSOP-B8J) 800 (DIP-T8) 65+150 Topr 40+85 Terminal voltage 0.3Vcc+1.0*9 V Parameter Symbol Limits Vcc 1.75.5 Input voltage VIN 0Vcc VIH1 0.7Vcc Vcc+1.0 V VIL1 0.3*1 0.3Vcc V "L" output voltage 1 VOL1 0.4 V "L" output voltage 2 VOL2 0.2 Parameter SDA and SCL rise time Typ. fSCL Max. 1000 kHz tHIGH s 0.3 tLOW 0.5 s tR 0.12 s Data clock "LOW" time IOL=0.7mA, 1.7VVcc2.5V (SDA) Unit Min. *1 Data clock "HIGH" time IOL=3.0mA, 2.5VVcc5.5V (SDA) Limit Symbol SCL frequency V V (Unless otherwise specified, Ta=40+85, VCC=1.75.5V) Conditions Unit Unit AC OPERATING CHARACTERISTICS (Unless otherwise specified, Ta=40+85VCC=1.75.5V) "L" input voltage 1 Years Not 100% TESTED Power source voltage Electrical characteristics "H" input voltage 1 Times Recommended operating conditions Junction Temperature Tjmax 150 When using at Ta=25 or higher, 8.0mW(*8), 4.5mW(*1,*2), 3.0mW(*3,*7), 3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1. *9 The Max value of Terminal Voltage is not over 6.5V. When the pulse width is 50ns or less, the Min value of Terminal Voltage is not under -1.0V. (BR24G16/32/64/128/256/512/1M-3A) the Min value of Terminal Voltage is not under -0.8V. (BR24G01/02/04/08-3A) *10 Junction temperature at the storage condition. Max. *1 *10 Typ. 40 *7 Action temperature range Min. 1,000,000 *1 *8 Tstg Symbol Unit Max *6 Storage temperature range Parameter *1 Typ. mW *5 300 (VSON008X2030) Limits Min. Number of data rewrite times 300 (SSOP-B8) *3 Permissible dissipation Limits Parameter *1 Input leak current ILI 1 1 A VIN=0Vcc SDA and SCL fall time *1 tF1 0.12 s Output leak current ILO 1 1 A VOUT =0Vcc (SDA) SDA (OUT) fall time *1 tF2 0.12 s 2.0 mA Vcc=5.5V,f SCL=400kHz, tWR=5ms, Start condition hold time tHD:STA 0.25 s Byte write, Page write Start condition setup time tSU:STA 0.25 s Input data hold time tHD:DAT 0 s Input data setup time tSU:DAT 50 ns tPD 0.05 0.45 s BR24G01/02/04/08/16/32/64-3A Vcc=5.5V,f SCL=400kHz, tWR=5ms, ICC1 2.5 mA Byte write, Page write Output data delay time BR24G128/256-3A tDH 0.05 s tSU:STO 0.25 s Bus release time before transfer start tBUF 0.5 s Vcc=5.5V,f SCL=1MHz Internal write cycle time tWR 5 ms Random read, current read, Noise removal valid period (SDA, SCL terminal) tI 0.05 s sequential read WP hold time tHD:WP 1.0 s BR24G01/02/04/08/16/32/64-3A WP setup time tSU:WP 0.1 s Vcc=5.5V,f SCL=1MHz WP valid time tHIGH:WP 1.0 s Output data hold time Vcc=5.5V,f SCL=400kHz, tWR=5ms, Byte write, Page write Stop condition setup time Current consumption BR24G512/1M-3A at action 4.5 0.5 mA *1 mA ICC2 2.0 mA Random read, current read, *1 Not 100% TESTED. sequential read BR24G128/256/512/1M-3A AC TIMING CHARACTERISTICS CONDITION Vcc=5.5V, SDASCL=Vcc Standby current 2.0 A0,A1,A2=GND,WP=GND A Parameter Symbol Condition Unit pF BR24G01/02/04/08/16/32/64/128/256-3A ISB 3.0 A Vcc=5.5V, SDASCL=Vcc Load Capacitance CL 100 A0,A1,A2=GND,WP=GND SDA and SCL rise time tR 20 ns BR24G512/1M-3A SDA and SCL fall time tF1 20 ns VIL/VIH 0.2Vcc/0.8Vcc V 0.3Vcc/0.7Vcc V Radiation resistance design is not made. *1 When the pulse width is 50ns or less, it is -1.0V. (BR24G16/32/64/128/256/512/1M-3A) When the pulse width is 50ns or less, it is -0.8V. (BR24G01/02/04/08-3A) Input Data Level Input/Output Data Timing Refence Level Sync data input / output timing tR SCL tF1 tHIGH 30% 70% 70% 70% 70% 70% tLOW tHD:DAT tSU:DAT 70% 70% 70% 70% ACK ACK tWR 70% 70% SDA (output) D0 D1 tDH tPD tBUF DATA(n) DATA(1) 70% 30% 30% SDA (input) 70% 30% 30% 30% tHD:STA 30% 30% 30% 30% 30% tF2 tSU:WP Input read at the rise edge of SCL Data output in sync with the fall of SCL Fig.1-(a) Sync data input / output timing tHD:WP STOP CONDITION Fig.1-(d) WP timing at write execution 70% 70% 70% tSU:STA tHD:STA D1 30% write data ACK ACK 70% ACK 70% 70% Fig.1-(e) WP timing at write cancel 70% 70% tWR tHIGH:WP STOP CONDITION START CONDITION (n-th address) D0 30% Fig.1-(b) Start-stop bit timing D0 DATA(n) DATA(1) tSU:STO 70% tWR STOP CONDITION START CONDITION Fig.1-(c) Write cycle timing www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 3/20 2012.2 - Rev.C BR24G -3A Series Technical Note Block diagram *2 A0 1 1Kbit1024 Kbit 8 EEPROM array Vcc *1 A0 1 A1 2 A2 3 GND 4 BR24G 01-3A BR 24G02-3A BR 24G04-3A BR 24G08-3A BR 24G16-3A BR 24G32-3A BR 24G 64-3A BR24G128-3A BR 24G 256 -3A BR24G 512 -3A BR24G 1M -3A 8bit *17bit *2 A1 8bit 9 bit 10 bit 11bit 12 bit Address decoder 2 13bit 14bit 15bit 16bit 17bit Word address register START *2 A2 3 Data register 7 WP STOP 6 Control circuit SCL ACK GND High voltage generating circuit 4 1 7bit: BR24G01-3A 8bit: BR24G02-3A 9bit: BR24G04-3A 10bit: BR24G08-3A 11bit: BR24G16-3A 12bit: BR24G32-3A Power source voltage detection 5 13bit: BR24G64-3A 14bit: BR24G128-3A 15bit: BR24G256-3A 16bit: BR24G512-3A 17bit: BR24G1M-3A 8 Vcc 7 WP 6 SCL 5 SDA SDA *2 A0= Don't use : BR24G04/1M-3A A0, A1=Don't use : BR24G08-3A A0, A1, A2=Don't use : BR24G16-3A Fig.2 Block diagram Pin assignment and description Terminal Input/ Name Output A0 BR24G01-3A BR24G02-3A BR24G04-3A BR24G08-3A Slave address setting Input BR24G16-3A Slave address setting Don't use BR24G1M-3A Don't use Slave address setting Don't use Slave address setting Slave address setting BR24G32/64/128/256/512-3A A1 Input A2 Input GND SDA Input/ output SCL Input Serial clock input WP Input Vcc Write protect terminal Connect the power source. Don't use Slave address setting Reference voltage of all input / output, 0V Serial data input serial data output Pins not used as device address may be set to any of `H', 'L', and 'Hi-Z'. Characteristic data (The following values are Typ. ones.) 4 L INPUT VOLTAGE : VIL1(V) Ta=-40 Ta=25 Ta=85 3 SPEC 2 1 Ta=-40 Ta=25 Ta=85 5 4 L OUTPUT VOLTAGE : VOL1(V) 5 H INPUT VOLTAGE : VIH1(V) 1 6 6 3 2 1 SPEC 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 0 6 1 2 3 4 5 6 0.6 SPEC 0.4 0.2 1 0.8 0.6 Ta=-40 Ta=25 Ta=85 0.4 0.2 0 0 3 4 5 6 L OUTPUT CURRENT : IOL(mA) Fig.6 'L' output voltage VOL2-IOL(Vcc=2.5V) www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 2 3 4 5 L OUTPUT CURRENT : IOL(mA) 6 1.2 OUTPUT LEAK CURRENT : I LO(uA) INPUT LEAK CURRENT : ILI(uA) Ta=-40 Ta=25 Ta=85 2 1 Fig.5 'L' output voltage VOL1-IOL(Vcc=1.7V) SPEC L OUTPUT VOLTAGE : VOL2(V) 0 1.2 1 0.2 Fig.4 'L' input voltage VIL1 (A0,A1,A2,SCL,SDA,WP) 1 0 SPEC 0.4 SUPPLY VOLTAGE : Vcc(V) Fig.3 'H' input voltage VIH1 (A0,A1,A2,SCL,SDA,WP) 0.8 0.6 0 0 0 Ta=-40 Ta=25 Ta=85 0.8 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc(V) Fig.7 Input leak current ILI (A0,A1,A2,SCL,WP) 4/20 6 SPEC 1 0.8 0.6 Ta=-40 Ta=25 Ta=85 0.4 0.2 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 Fig.8 Output leak current ILO(SDA) 2012.2 - Rev.C BR24G -3A Series Technical Note Characteristic data (The following values are Typ. ones.) 3.5 2.5 2 Ta=-40 Ta=25 Ta=85 1 0.5 Ta=-40 Ta=25 Ta=85 2 1.5 1 0.5 3 2 1 0 0 0 1 2 3 4 5 0 6 1 2 SUPPLY VOLTAGE : Vcc(V) 3 4 5 0 6 0 0.2 0.1 The plan for inserting data. (BR24G128/256/512/ 1M-3A) 0.4 0.3 0.2 0.1 1.5 1 2 3 4 5 6 0 0 2.5 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 1 0 1 2 3 4 5 The plan for inserting data. 100 10 1 0 1 2 SUPPLY VOLTAGE : Vcc(V) Fig.15 Standby operation ISB (BR24G512/1M-3A) START CONDITION HOLD TIME : tHD : STA(us) 0.6 0.3 0 0 1 2 3 4 3 4 5 5 0.9 The plan for inserting data. 0.8 0.6 0.4 0.2 -100 -150 -200 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc(V) Fig.21 Input Data Hold Time tHD : DATHIGH www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. INPUT DATA HOLD TIME : tHD :DAT(ns) -50 4 5 6 The plan for inserting data. 0.7 0.5 0.3 0.1 -0.1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc(V) Fig.20 Start Condition Setup Time tSU : STA 50 The plan for inserting data. 3 Fig.17 Data clock High Period tHIGH Fig.19 Start Condition Hold Time tHD : STA 50 2 SUPPLY VOLTAGE : Vcc(V) SUPPLY VOLTAGE : Vcc(V) Fig.18 Data clock Low Period tLOW 0 1 1.1 SUPPLY VOLTAGE : VccV 0 0.2 0 1 0 6 6 0.4 6 300 The plan for inserting data. 0 -50 -100 -150 -200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc(V) Fig.22 Input Data Hold Time HD : DAT(LOW 5/20 INPUT DATA SET UP TIME : tSU: DAT(ns) CLK L TIME : tLOW(us) 0.9 5 The plan for inserting data. 0.6 Fig.16 SCL frequency fSCL The plan for inserting data. 1.2 0.8 SUPPLY VOLTAGE : Vcc(V) 1.5 4 0 0.1 6 3 1 1000 0 2 Fig.14 Standby operation ISB (BR24G01/02/04/08/16/32/64/128/256-3A) START CONDITION SET UP TIME : tSU:STA(us) 1.5 1 SUPPLY VOLTAGE : Vcc(V) DATA CLK H TIME : tHIGH(us) The plan for inserting data. (BR24G512/1M-3A) 0.5 INPUT DATA HOLD TIME : tHD: STA(ns) 0 6 10000 SCL FREQUENCY : fHZ STANBY CURRENT : ISB(uA) 1 Fig.13 Current consumption at READ operation ICC2 (fscl=1MHz BR24G128/256/512/1M-W) Fig.12 Current consumption at READ operation ICC2 (fscl=1MHz BR24G01/02/04/08/16/32/64/-3A) 2 Ta=-40 Ta=25 Ta=85 0.5 0 SUPPLY VOLTAGE : Vcc(V) 6 1 0 0 5 SPEC 2 STANBY CURRENT : ISB(uA) 0.3 4 2.5 0.5 CURRENT CONSUMPTION AT READING : Icc2(mA) The plan for inserting data. (BR24G01/02/08/16/ 32/64-3A) 3 Fig.11 Current consumption at WRITE operation Icc1 (fscl=1MHz BR24G512/1M-3A) 0.6 0.4 2 SUPPLY VOLTAGE : Vcc(V) Fig.10 Current consumption at WRITE operation Icc1 (fscl=1MHz BR24G128/256-3A) 0.6 0.5 1 SUPPLY VOLTAGE : Vcc(V) Fig.9 Current consumption at WRITE operation ICC1 (fscl=1MHz BR24G01/02/04/08/16/32/64-3A) CURRENT CONSUMPTION AT READING : Icc2(mA) 4 CURRENT CONSUMPTION AT WRITING : Icc1(mA) 1.5 The plan for inserting data. (BR24G512/1M-3A) 5 SPEC 2.5 CURRENT CONSUMPTION AT WRITING : Icc1(mA) CURRENT CONSUMPTION AT WRITING : Icc1(mA) 6 3 SPEC The plan for inserting data. 200 100 0 -100 -200 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc(V) Fig.23 Input Data Setup Time SU: DAT(HIGH) 2012.2 - Rev.C BR24G -3A Series Technical Note Characteristic data (The following values are Typ. ones.) 2.0 The plan for inserting data. 200 100 0 -100 -200 0 1 2 3 4 5 6 The plan for inserting data. 1.5 SPEC 1.0 0.5 0.0 0 1 2 SUPPLY VOLTAGE : Vcc(V) 3 4 5 6 0.5 0.0 -0.5 1 2 3 4 5 0.0 0 1 1 0.5 3 2 Ta=-40 Ta=25 Ta=85 1 0 0 1 2 3 4 5 0 6 0 1 2 0.5 0.5 0.1 0 1 2 3 4 5 The plan for inserting data. 0.3 0.2 0.1 0 0 1 0.5 1.0 WP DATA HOLD TIME : tHD : WP(us) NOISE REDUCTION EFFECTIVE TIME : tl(SAD L)(us) 1.2 The plan for inserting data. 0.3 0.2 0.1 0 0 1 2 3 4 3 4 5 5 6 SUPPLY VOLTAGE : Vcc(V) 0.3 0.2 0.1 0 0 1 2 3 4 5 6 SUPPLY VOLATGE : Vcc(V) Fig.32 Noise resuction efecctive time SDA H 0.2 0.1 The plan for inserting data. 0.8 0.6 0.4 0.2 The plan for inserting data. 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 0.0 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc(V) Fig.33 Noise reduction efective time tlSDA L 6 The plan for inserting data. 0.4 6 Fig.31 Noise reduction efective time tlSCL L 0.6 0.4 2 0.5 SUPPLY VOLTAGE : Vcc(V) SUPPLY VOLTAGE : Vcc(V) Fig.30 Noise reduction efection time tlSCL H 5 0.6 0.4 6 4 Fig.29 Internal writing cycle time WR WP SET UP TIME : tSU : WP(us) 0 3 SUPPLY VOLTAGE : Vcc(V) NOISE REDUCTION EFECTIVE TIME : tl(SDA H)(us) 0.6 NOISE REDUCTION EFECTIVE TIME : tl(SCL L)(us) NOISE REDUCTION EFECTIVE TIME : tl(SCL H) (us) 0.6 0.2 6 4 Fig.28 BUS open time before transmission BUF 0.3 5 SPEC SUPPLY VOLTAGE : Vcc(V) The plan for inserting data. 4 5 The plan for inserting data. 1.5 6 Fig.27 Stop condition setup time SU:STO 3 6 SUPPLY VOLTAGE : Vcc(V) 0.4 2 Fig.26 'H' Data output delay time PD1 INTERNAL WRITING CYCLE TIME : tWR(ms) BUS OPEN TIME BEFORE TRANSMISSION : tBUF(us) The plan for inserting data. 0 0.5 SUPPLY VOLTAGE : Vcc(V) 2 1.0 1.0 SUPPLY VOLTAGE : Vcc(V) 2.0 1.5 The plan for inserting data. 1.5 Fig.25 'L' Data output delay time tPD0 Fig.24 Input Data setup time tSU : DAT(LOW) STOP CONDITION SETUP TIME : tsu:STO(us) OUTPUT DATA DELAY TIME : tPD(us) 2.0 OUTPUT DATA DELAY TIME : tPD(us) INPUT DATA SET UP TIME : tSU : DAT(ns) 300 Fig.34 WP data hold time tHD:WP 1 2 3 4 5 6 6 SUPPLY VOLTAGE : Vcc(V) Fig.35 WP setup time tSU : WP WP EFFECTIVE TIME : tHIGH : WP(us) 1.2 SPEC 1.0 0.8 Ta=-40 Ta=25 Ta=85 0.6 0.4 0.2 0.0 0 1 2 3 4 5 6 SUPPLYVOLTAGE : Vcc(V) Fig.36 WP efective time tHIGH : WP www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 6/20 2012.2 - Rev.C BR24G -3A Series Technical Note 2 I C BUS communication 2 I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and 2 acknowledge is always required after each byte. I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by address peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver". SDA 1-7 SCL S START ADDRESS condition 8 9 R/W ACK 1-7 8 DATA 9 ACK 1-7 8 9 DATA ACK Fig.37 Data transfer timing P STOP condition Start condition (Start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. Stop condition (stop bit recongnition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in status. Device addressing Output slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'. Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R / Setting R / W W to 0 ------- write (setting 0 to word address setting of random read) to 1 ------- read Type Maximum number of Connected buses Slave address BR24G01-3A,BR24G02-3A 1 0 1 0 A2 A1 A0 R/W BR24G04-3A 1 0 1 0 A2 A1 P0 R/W BR24G08-3A 1 0 1 0 A2 P1 P0 R/W BR24G16-3A BR24G32-3A, BR24G64-3A, BR24G128-3A,BR24G256-3A, BR24G512-3A BR24G1M-3A 1 0 1 0 P2 P1 P0 R/W 1 0 1 0 A2 A1 A0 R/W 1 0 1 0 A2 A1 P0 R/W 8 4 2 1 8 4 P0P2 are page select bits. www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 7/20 2012.2 - Rev.C BR24G -3A Series Technical Note Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is specified per device of each capacity. up to 256 arbitrary bytes can be written. (In the case of BR24G1M-3A) S T A R T SDA LINE W R I T E SLAVE ADDRESS WORD ADDRESS WA 7 1 0 1 0 A2 A1 A0 DATA As for WA7, BR24G01-3A becomes Don't care. WA 0 D7 D0 A C K R A / C W K Note) S T O P A C K Fig.38 Byte write cycle (BR24G01/02/04/08/16-3A) S T A R T SDA LINE W R I T E SLAVE ADDRESS 1st WORD ADDRESS DATA WAWA WA WAWA 15 14 13 12 11 1 0 1 0 A2 A1 A0 R A / C W K Note) 2nd WORD ADDRESS WA 0 A C K *1 S T O P D7 *1 As for WA12, BR24G32-3A becomes Don't care. As for WA13, BR24G32/64-3A becomes Don't care. As for WA14, BR24G32/64/128-3A becomes Don't care. As for WA15, BR24G32/64/128/256-3A becomes Don't care. D0 A C K A C K Fig.39 Byte write cycle (BR24G32/64/128/256/512/1M -3A) S T A R T SDA LINE W R I T E SLAVE ADDRESS WA 7 1 0 1 0 A2 A1 A0 0 0 DATA(n) WA 0 R A / C *1 W K Note) S T O P *2 WORD ADDRESS(n) D7 DATA(n+15) D0 *1 As for WA7, BR24G01-3A becomes Don't care. *2 As for BR24G01/02-3A becomes (n+7) D0 A C K A C K A C K Fig.40 Page write cycle (BR24G01/02/04/08/16-3A) S T A R T SDA LINE SLAVE ADDRESS 1 0 1 0 0 W R I T E 1st WORD ADDRESS(n) WA WA WA WA WA A2 A1 A0 15 14 DATA(n) WA D7 0 13 12 11 DATA(n+31) D0 Note) *1 A C K A C K *1 As for WA12, BR24G32-3A becomes Don't care. As for WA13, BR24G32/64-3A becomes Don't care. As for WA14, BR24G32/64/128-3A becomes Don't care. As for WA15, BR24G32/64/128/256-3A becomes Don't care. D0 0 R A / C W K S T O P *2 2nd WORD ADDRESS(n) A C K A C K *2 As for BR24G128/256-3A becomes (n+63) As for BR24G128/256-3A becomes (n+127) As for BR24G128/256-3A becomes (n+255) Fig.41 Page write cycle (BR24G32/64/128/256/512/1M -3A) Note) *1 *2 *3 *1 *2 *3 1 0 1 0 A 2A 1A 0 In BR24G16-3A, A2 becomes P2. In BR24G08/16-3A, A1 becomes P1. In BR24G04/08/16/1M-3A A0 becomes P0. Fig.42 Difference of slave address of each type www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 8/20 2012.2 - Rev.C BR24G -3A Series Technical Note During internal write execution, all input commands are ignored, therefore ACK is not sent back. Data is written to the address designated by word address (n-th address) By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk : Up to 8Byte (BR24G01-3A, BR24G02-3A Up to 16Byte (BR24G04-3A, BR24G08-3A, BR24G16-3A Up to 32Byte (BR24G32-3A, BR24G64-3A Up to 64Byte (BR24G128-3A, BR24G256-3A Up to 128Byte (BR24G512 -3A Up to 256Byte (BR24G1M-3A And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment" of "Notes on page write cycle" in P10.) As for page write cycle of BR24G01-3A and BR24G02-3A, after the significant 4 bits (in the case of BR24G01-3A) of word address, or the significant 5 bits (in the case of BR24G02-3A) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be written. As for page write command of BR24G04-3A, BR24G08-3A and BR24G16-3A, after page select bit 'P0'(in the case of BR24G04-3A), after page select bit 'P0,P1'(in the case of BR24G08-3A), after page select bit 'P0,P1,P2'(in the case of BR24G16-3A) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. As for page write cycle of BR24G32-3A and BR24G64-3A, after the significant 7 bits (in the case of BR24G32-3A) of word address, or the significant 8 bits (in the case of BR24G64-3A) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written. As for page write cycle of BR24G128-3A and BR24G256-3A, after the significant 8 bits (in the case of BR24G128-3) of word address, or the significant 9 bits (in the case of BR24G256-3A) of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64 bytes can be written. As for page write cycle of BR24G512-3A after the significant 9 bits of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 128 bytes can be written. As for page write cycle of BR24G1M-3A after page select bit `P0' and the significant 8 bits of word address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and data up to 256 bytes can be written. www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 9/20 2012.2 - Rev.C BR24G -3A Series Technical Note Notes on page write cycle List of numbers of page write Number of 8Byte Pages 16Byte 32Byte BR24G04-3A BR24G32-3A BR24G08-3A BR24G64-3A BR24G16-3A The above numbers are maximum bytes for respective types. Any bytes below these can be written. Product number BR24G01-3A BR24G02-3A 64Byte 128Byte 256Byte BR24G128-3A BR24G256-3A BR24G512-3A BR24G1M-3A In the case BR24G256-3A, 1 page=64bytes, but the page write cycle time is 5ms at maximum for 64byte bulk write. It does not stand 5ms at maximum x 64byte=320ms(Max.) Internal address increment Page write mode (in the case of BR24G16-3A 0Eh WA7 WA4 WA3 WA2 WA1 WA0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up Increment For example, when it is started from address 0Eh, therefore, increment is made as below, 0Eh0Fh00h01h which please note. 0Eh0E in hexadecimal, therefore, 00001110 becomes a binary number. Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented. www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 10/20 2012.2 - Rev.C BR24G -3A Series Technical Note Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession. S T A R T SDA L IN E W R I T E SLAVE ADDRE SS W ORD A D D R E S S (n) WA 7 1 0 1 0 A 2 A 1A 0 WA 0 R A *1 R E A D SLAVE ADDRESS S T O P D A TA (n ) 1 0 1 0 A 2 A 1A 0 A C K / C W K N o te ) S T A R T D7 *1 D0 As for WA7,BR24G01-3A become Don't care. A C K R A / C W K Fig.43 Random read cycle (BR24G01/02/04/08/16-3A) S T A R T SDA LINE W R I T E SLAVE ADDRESS R A / C W K S T A R T 2nd WORD ADDRESS WA 0 WAWA WA WAWA 15 14 13 12 11 1 0 1 0 A2A1A0 Note) 1st WORD ADDRESS A C K *1 R E A D SLAVE ADDRESS 1 0 1 0 A2 A1A0 A C K S T O P DATA(n) D7 D0 R A / C W K A C K *1 As for WA12, BR24G32-3A become Don't care. As for WA13, BR24G32/64-3A become Don't care. As for WA14, BR24G32/64/128-3A become Don't care. As for WA15, BR24G32/64/128/256-3A become Don't care. Fig.44 Random read cycle (BR24G32/64/128/256/512/1M-3A) S T A R T R E A D SLAVE ADDRESS SDA LIN E S T O P D A TA (n) 1 0 1 0 A 2 A 1A 0 D7 D0 A C K R A / C W K N ote) Fig.45 Current read cycle S T A R T SDA LINE R E A D SLAVE ADDRESS 1 0 1 0 A2 A1A0 DATA(n) D7 DATA(n+x) D0 R A / C W K Note S T O P D7 A C K D0 A C K A C K Fig.46 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' . When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'. Note) *1 In BR24G16-3A, A2 becomes P2. *2 In BR24G08/16-3A, A1 becomes P1. *3 In BR24G08/16/1M-3A, A0 becomes P0. *1 *2 *3 1 0 1 0 A2 A1A0 Fig.47 Difference of slave address of each type www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 11/20 2012.2 - Rev.C BR24G -3A Series Technical Note Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.45-(a), Fig.45-(b), Fig.45-(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clockx14 SCL 1 2 Startx2 13 Normal command 14 SDA Normal command Fig.48-(a) The case of dummy clock +START+START+ command input SCL Start Dummy clockx9 Start 1 2 8 Normal command 9 SDA Normal command Fig.48-(b) The case of START +9 dummy clocks +START+ command input Startx9 SCL 1 2 3 7 8 Normal command 9 SDA Normal command SD Fig.48-(c) STARTx9+ command input Start command from START input. Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data output and so forth. During internal write, ACK = HIGH is sent back. First write command S T A R T Write command S T O P S T Slave A R address T A C K H tWR S T Slave A R address T A C K H ... Second write command ... S T Slave A R address T A C K H S T Slave A R address T A C K L Word address A C K L Data A C K L S T O P tWR After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession. Fig.49 Case to continuously write by acknowledge polling www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 12/20 2012.2 - Rev.C BR24G -3A Series Technical Note WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel valid area. And, after execution of forced end by WP, standby status gets in. Rise of SDA Rise of D0 taken clock SCL SCL SDA D1 D0 ACK SDA Enlarged view SDA S T Slave A R address T A C Word K address L D0 ACK Enlarged view A C D7 D6 D5 D4 D3 D2 D1 D0 K L WP cancel invalid area A C K L Data A C K L S T O P WP cancel valid area tWR WP cancel invalid area WP Data is not written. Fig.50 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Fig.51 Case of cancel by start, stop condition during slave address input www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 13/20 2012.2 - Rev.C BR24G -3A Series Technical Note I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. The bus electric potential A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. VCCILRPU0.2 VCC VIH 0.8VCCVIH IL RPU Microcontroller BR24GXX Ex.) VCC =3V IL=10A VIH=0.7 VCC from RPU RPU SDA terminal A 0.8x30.7x3 10x10-6 IL 300 k Minimum value of RPU The minimum value of RPU is determined by the following factors. When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA. IL Bus line capacity CBUS Fig.52 I/O circuit diagram VCCVOL IOL RPU RPU VCCVOL IOL VOLMAX= should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL0.1 VCC Ex.) VCC =3VVOL=0.4VIOL=3mAmicrocontroller, EEPROM VIL=0.3Vcc from RPU 30.4 3x10 -3 867 And VOL=0.4V VIL=0.3x3 =0.9V Therefore, the condition is satisfied. Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 14/20 2012.2 - Rev.C BR24G -3A Series Technical Note Cautions on microcontroller connection RS In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when using CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used. ACK SCL RPU RS SDA 'H' output of microcontroller 'L' output of EEPROM Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM. EEPROM Microcontroller Fig.53 I/O circuit diagram Fig.54 Input / output collision timing Maximum value of Rs The maximum value of Rs is determined by the following relations. SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. The bus electric potential A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc. (VCCVOL)xRS RPU+RS VCC RPU RS A VOL RS + VOL+0.1VCCVIL VILVOL0.1VCC 1.1VCC-VIL x RPU IOL Ex.VCC=3V VIL=0.3VCC VOL=0.4V RPU=20k Bus line capacity CBUS VIL Micro controller RS EEPROM Fig.55 I/O Circuit Diagram 0.3x30.40.1x3 1.1x30.3x3 x 20x103 1.67k Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. VCC RS RPU 'L'output RS RS Over current I I VCC I Ex.) VCC=3V, I=10mA 'H' output RS Microcontroller EEPROM 3 -3 10x10 300 Fig.56 I/O circuit diagram www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 15/20 2012.2 - Rev.C BR24G -3A Series Technical Note I2C BUS input / output circuit Input (A0, A1, A2, SCL, WP) Fig.57 Input pin circuit diagram Input / output (SDA) Fig.58 Input / output pin circuit diagram www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 16/20 2012.2 - Rev.C BR24G -3A Series Technical Note Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. tR Recommended conditions of tR, tOFF,Vbot tR tOFF Vbot VCC tOFF 10ms or below 10ms or larger 0.3V or below Vbot 100 or below 10ms or larger 0.2V or below 0 Fig.59 Rise waveform diagram 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. Fig.60 When SCL='H' and SDA='L' Fig.61 When SCL='L' and SDA='L' ) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P12). ) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b). Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite. Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. Cautions on use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 17/20 2012.2 - Rev.C BR24G -3A Series Technical Note Order part number B R ROHM type name 2 4 BUS type 2 24I C G Operating temperature/ Power source Voltage G:-40+85/ 1.7V5.5V White Reel 2 5 6 Capacity 01=1K 02=2K 04=4K 08=8K 16=16K 3232K 6464K 128=128K 256=256K 512=512K 1M=1024K 3 F Package Blank :DIP-T8 F FJ FV FVT FVJ FVM NUX A Revision G T E 2 100% Sn :SOP8 Process Code Halogen free :SOP-J8 : SSOP-B8 : TSSOP-B8 Package specifications : TSSOP-B8J E2reel shape emboss taping : MSOP8 : VSON008X2030 TRreel shape emboss taping Package specifications www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. 18/20 2012.2 - Rev.C BR24G -3A Series www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. Technical Note 19/20 2012.2 - Rev.C BR24G -3A Series www.rohm.com (c) 2012 ROHM Co., Ltd. All rights reserved. Technical Note 20/20 2012.2 - Rev.C