IRFBA1404P
HEXFET® Power MOSFET
PD - 93806
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFETs utilizes the latest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this MOSFET are a 175oC junction operating
temperature, fast switching speed and improved ruggedness in
single and repetitive avalanche. The Super-220 TM is a package that
has been designed to have the same mechanical outline and pinout
as the industry standard TO-220 but can house a considerably
larger silicon die. The result is significantly increased current
handling capability over both the TO-220 and the much larger TO-
247 package. The combination of extremely low on-resistance
silicon and the Super-220 TM package makes it ideal to reduce the
component count in multiparalled TO-220 applications, reduce
system power dissipation, upgrade existing designs or have TO-247
performance in a TO-220 outline. This package has been designed
to meet automotive, Q101, qualification standard.
These benefits make this design an extremely efficient and reliable
device for use in Automotive applications and a wide variety of other
applications.
Description
S
D
G
10/24/00
www.irf.com 1
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 206
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 145A
IDM Pulsed Drain Current 650
PD @TC = 25°C Power Dissipation 300 W
Linear Derating Factor 2.0 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche EnergySee Fig.12a, 12b, 15, 16 mJ
IAR Avalanche CurrentA
EAR Repetitive Avalanche Energy30 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -40 to + 175
TSTG Storage Temperature Range -55 to + 175
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Recommended clip force 20 N
°C
lAnti-lock Braking Systems (ABS)
lElectric Power Steering (EPS)
lElectric Braking
lRadiator Fan Control VDSS = 40V
RDS(on) = 3.7mΩ
ID = 206A
Super-220™
Typical Applications
Benefits
lAdvanced Process Technology
lUltra Low On-Resistance
lIncrease Current Handling Capability
l175°C Operating Temperature
lFast Switching
lDynamic dv/dt Rating
lRepetitive Avalanche Allowed up to Tjmax
AUTOMOTIVE MOSFET
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Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 –– – –– – V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.036 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 3.7 mΩVGS = 10V, ID = 95A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 106 ––– ––– S VDS = 25V, ID = 60A
––– ––– 20 µA VDS = 40V, VGS = 0V
––– ––– 250 VDS = 32V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 nA VGS = -20V
QgTotal Gate Charge –– – 1 60 2 0 0 ID = 95A
Qgs Gate-to-Source Charge ––– 35 –– – nC VDS = 32V
Qgd Gate-to-Drain ("Miller") Charge ––– 42 60 VGS = 10V
td(on) Turn-On Delay Time ––– 17 – –– VDD = 20V
trRise Time ––– 140 ––– ID = 95A
td(off) Turn-Off Delay Time ––– 72 – –– RG = 2.5Ω
tfFall Time ––– 26 ––– RD = 0.21Ω
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 7360 ––– VGS = 0V
Coss Output Capacitance ––– 1680 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 240 ––– pF ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 6630 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 1490 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 1540 ––– VGS = 0V, VDS = 0V to 32V
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
2.0
5.0
IDSS Drain-to-Source Leakage Current
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 95A, VGS = 0V
trr Reverse Recovery Time ––– 71 110 ns TJ = 25°C, IF = 95A
Qrr Reverse Recovery Charge ––– 180 270 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
206
650 A
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.50
RθCS Case-to-Sink, Flat, Greased Surface 0. 5 –– – °C/W
RθJA Junction-to-Ambient ––– 58
Thermal Resistance
IRFBA1404P
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
10
100
1000
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
10
100
1000
0.1 1 10 100
20
µ
s PULSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Volta
g
e (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
10
100
1000
4.0 5.0 6.0 7.0 8.0 9.0
V = 25V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 25 C
J°
T = 175 C
J°
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
159A
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
1 10 100
0
2000
4000
6000
8000
10000
12000
V , Drain-to-Source Volta
g
e (V)
C, Capacitance (pF)
DS
V
C
C
C
=
=
=
=
0V,
C
C
C
f = 1MHz
+ C
+ C
C SHORTED
GS
iss
g
s
g
d , ds
rss
g
d
oss ds
g
d
Ciss
Coss
Crss
040 80 120 160 200 240
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
95A
V = 20V
DS
V = 32V
DS
1
10
100
1000
0.4 0.8 1.2 1.6 2.0 2.4
V ,Source-to-Drain Volta
g
e (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
1
10
100
1000
10000
1 10 100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Volta
g
e (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
IRFBA1404P
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
10V
+
-
VDD
25 50 75 100 125 150 175
0
60
120
180
240
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.001
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFBA1404P
6www.irf.com
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
020 40 60 80 100
IAV , Avalanche Current ( A)
40
42
44
46
48
50
V DSav , Avalanche Voltage ( V )
25 50 75 100 125 150 175
0
200
400
600
800
1000
Starting T , Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
J
AS
°
ID
TOP
BOTTOM
39A
67A
95A
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆∆
∆∆
∆T/ ZthJC
Iav = 2∆∆
∆∆
∆T/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 95A
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming
∆Tj = 25°C due to
avalanche losses
0.01
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
Fig 17. For N-Channel HEXFET Power MOSFETs
IRFBA1404P
www.irf.com 9
Super-220™ Package Outline
2X
A
123
3X
0.2 5 [. 01 0] B A
B
4X
4
0.2 5 [. 01 0] B A
3.0 0 [. 11 8]
2.5 0 [. 09 9]
14 . 50 [.570]
13 . 00 [.512]
4.0 0 [. 15 7]
3.5 0 [. 13 8]
1.30 [.051]
0.90 [.036]
2.5 5 [. 10 0]
1.0 0 [. 03 9]
0.7 0 [. 02 8]
5.0 0 [. 19 6]
4.0 0 [. 15 8]
11 . 00 [.433]
10 . 00 [.394]
1.5 0 [. 05 9]
0.5 0 [. 02 0]
15 . 00 [.590]
14 . 00 [.552]
9.0 0 [. 35 4]
8.0 0 [. 31 5]
13 . 50 [.531]
12 . 50 [.493]
L EAD ASSIGNMENTS
2 - DRAIN
1 - GATE
MOS F ET
4 - DRAIN
3 - SOURCE 4 - COLLECT OR
3 - EMITTER
2 - COLLECT OR
1 - GATE
IGBT
1. DIMENSIONING & TOLERANCI NG PER ASME Y14.5M-1994.
2. CONT ROLLING DIM E NS ION: MILLIMET E R.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES] .
NOTES:
4. OUT LINE CONFORMS TO JE DE C OUT LINE T O-273AA.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000
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IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630
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Data and specifications subject to change without notice. 10/00
Repetitive rating; pulse width limited by
max. junction temperature.
ISD ≤ 95A, di/dt ≤ 150A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Notes:
Starting TJ = 25°C, L = 0.12mH
RG = 25Ω, IAS = 95A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while V DS is rising from 0 to 80% VDSS . Refer to AN-1001
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 95A.
