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ADS7822
ADS7822
1
FEATURES
DESCRIPTION
APPLICATIONS
SAR Control
Serial
Interface
DOUT
Comparator
S/HAmp CS/SHDN
DCLOCK
+In
VREF
-In
CDAC
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
12-Bit, 200kHz, microPower SamplingANALOG-TO-DIGITAL CONVERTER
2
•200kHz Sampling Rate•microPower:
The ADS7822 is a 12-bit sampling analog-to-digital(A/D) converter with ensured specifications over a1.6mW at 200kHz
2.7V to 5.25V supply range. It requires very little0.54mW at 75kHz
power even when operating at the full 200kHz rate. At0.06mW at 7.5kHz
lower conversion rates, the high speed of the device•Power Down: 3 μA max
enables it to spend most of its time in the•Mini-DIP-8, SO-8, and MSOP-8 Packages
power-down mode — the power dissipation is lessthan 60 μW at 7.5kHz.•Pseudo-Differential Input•Serial Interface
The ADS7822 also features operation from 2.0V to5V, a synchronous serial interface, and apseudo-differential input. The reference voltage canbe set to any level within the range of 50mV to V
CC
.•Battery-Operated Systems
Ultra low power and small size make the ADS7822•Remote Data Acquisition
ideal for battery-operated systems. It is also a perfect•Isolated Data Acquisition
fit for remote data-acquisition modules, simultaneous•Simultaneous Sampling, Multichannel Systems
multichannel systems, and isolated data acquisition.The ADS7822 is available in a plastic mini-DIP-8, anSO-8, or an MSOP-8 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
MAXIMUM MAXIMUMINTEGRAL DIFFERENTIAL SPECIFIED TRANSPORTPACKAGE- PACKAGE PACKAGE ORDERINGPRODUCT LINEARITY LINEARITY TEMPERATURE MEDIA,LEAD DESIGNATOR MARKING
(2)
NUMBERERROR ERROR RANGE QUANTITY(LSB) (LSB)
Tape and Reel,ADS7822E/250
250ADS7822E ± 2 ± 2 MSOP-8 DGK – 40 °C to +85 °C A22
Tape and Reel,ADS7822E/2K5
2500
Tape and Reel,ADS7822EB/250
250ADS7822EB ± 1 ± 1 MSOP-8 DGK – 40 °C to +85 °C A22
Tape and Reel,ADS7822EB/2K5
2500
Tape and Reel,ADS7822EC/250
250ADS7822EC ± 0.75 ± 0.75 MSOP-8 DGK – 40 °C to +85 °C A22
Tape and Reel,ADS7822EC/2K5
2500
PlasticADS7822P ± 2 ± 2 P – 40 °C to +85 °C ADS7822P ADS7822P Rails, 50DIP-8
PlasticADS7822PB ± 1 ± 1 P – 40 °C to +85 °C ADS7822PB ADS7822PB Rails, 50DIP-8
PlasticADS7822PC ± 0.75 ± 0.75 P – 40 °C to +85 °C ADS7822PC ADS7822PC Rails, 50DIP-8
ADS7822U Rails, 100ADS7822U ± 2 ± 2 SO-8 D – 40 °C to +85 °C ADS7822U
Tape and Reel,ADS7822U/2K5
2500
ADS7822UB Rails, 100ADS7822UB ± 1 ± 1 SO-8 D – 40 °C to +85 °C ADS7822UB
Tape and Reel,ADS7822UB/2K5
2500
ADS7822UC Rails, 100ADS7822UC ± 0.75 ± 0.75 SO-8 D – 40 °C to +85 °C ADS7822UC
Tape and Reel,ADS7822UC/2K5
2500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or seethe TI website at www.ti.com.(2) Performance grade information is marked on the reel.
over operating free-air temperature range (unless otherwise noted)
ADS7822 UNIT
V
CC
+6 VAnalog input – 0.3 to V
CC
+ 0.3 VLogic input – 0.3 to 6 VCase temperature +100 °CJunction temperature +150 °CStorage temperature +125 °CExternal reference voltage +5.5 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
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ELECTRICAL CHARACTERISTICS: +V
CC
= +2.7V
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
At – 40 °C to +85 °C, +V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 75kHz, and f
CLK
= 16 ×f
SAMPLE
, unless otherwise noted.
ADS7822 ADS7822B ADS7822CPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale input span +In – ( – In) 0 V
REF
0 V
REF
0 V
REF
V
+In – GND – 0.2 V
CC
+ 0.2 – 0.2 V
CC
+ 0.2 – 0.2 V
CC
+ 0.2 VAbsolute input range
– In – GND – 0.2 +1.0 – 0.2 +1.0 – 0.2 +1.0 V
Capacitance 25 25 25 pF
Leakage current ± 1 ± 1 ± 1 μA
SYSTEM PERFORMANCE
Resolution 12 12 12 Bits
No missing codes 11 12 11 Bits
Integral linearity error – 2 ± 0.5 +2 – 1 ± 0.5 +1 – 0.75 ± 0.25 +0.75 LSB
(1)
Differential linearity error – 2 ± 0.5 +2 – 1 ± 0.5 +1 – 0.75 ± 0.25 +0.75 LSB
Offset error – 3 +3 – 3 +3 – 1 +1 LSB
Gain error – 3 +3 – 3 +3 – 1 +1 LSB
Noise 33 33 33 μVrms
Power-supply rejection 82 82 82 dB
SAMPLING DYNAMICS
Conversion time 12 12 12 Clk Cycles
Acquisition time 1.5 1.5 1.5 Clk Cycles
Throughput rate 75 75 75 kHz
DYNAMIC CHARACTERISTICS
Total harmonic distortion V
IN
= 2.5V
PP
at 1kHz – 82 – 82 – 82 dB
SINAD V
IN
= 2.5V
PP
at 1kHz 71 71 71 dB
Spurious-free dynamic range V
IN
= 2.5V
PP
at 1kHz 86 86 86 dB
REFERENCE OUTPUT
Voltage range 0.05 V
CC
0.05 V
CC
0.05 V
CC
V
CS = GND, f
SAMPLE
= 0Hz 5 5 5 G ΩResistance
CS = V
CC
5 5 5 G Ω
At code 710h 8 40 8 40 8 40 μA
Current drain f
SAMPLE
= 7.5kHz 0.8 0.8 0.8 μA
CS = V
CC
0.001 3 0.001 3 0.001 3 μA
DIGITAL INPUT/OUTPUT
Logic family CMOS CMOS CMOS
V
IH
I
IH
= +5 μA 2.0 5.5 2.0 5.5 2.0 5.5 V
V
IL
I
IL
= +5 μA – 0.3 0.8 – 0.3 0.8 – 0.3 0.8 VLogic levels
V
OH
I
OH
= – 250 μA 2.1 2.1 2.1 V
V
OL
I
OL
= 250 μA 0.4 0.4 0.4 V
Data format Straight Binary Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
Specified performance 2.7 3.6 2.7 3.6 2.7 3.6 V
V
CC
See Notes
(2)
and
(3)
2.0 2.7 2.0 2.7 2.0 2.7 V
See Note
(3)
2.7 3.6 2.7 3.6 2.7 3.6 V
f
SAMPLE
= 7.5kHz
(4) (5)
20 20 20 μAQuienscent current
f
SAMPLE
= 75kHz
(5)
200 325 200 325 200 325 μA
Power down CS = V
CC
333μA
TEMPERATURE RANGE
Specified performance – 40 +85 – 40 +85 – 40 +85 °C
(1) LSB means least significant bit. With V
REF
equal to +2.5V, one LSB is 0.61mV.(2) The maximum clock rate of the ADS7822 is less than 1.2MHz in this power-supply range.(3) See the Typical Characteristics for more information.(4) f
CLK
= 1.2MHz, CS = V
CC
for 145 clock cycles out of every 160.(5) See the Power Dissipation section for more information regarding lower sample rates.
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ELECTRICAL CHARACTERISTICS: +V
CC
= +5V
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
At – 40 °C to +85 °C, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 200kHz, and f
CLK
= 16 ×f
SAMPLE
, unless otherwise noted.
ADS7822 ADS7822BPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
ANALOG INPUT
Full-scale input span +In – ( – In) 0 V
REF
0 V
REF
V
+In – GND – 0.2 V
CC
+ 0.2 – 0.2 V
CC
+ 0.2 VAbsolute input range
– In – GND – 0.2 +1.0 – 0.2 +1.0 V
Capacitance 25 25 pF
Leakage current ± 1 ± 1 μA
SYSTEM PERFORMANCE
Resolution 12 12 Bits
No missing codes 11 12 Bits
Integral linearity error – 2 +2 – 1 +1 LSB
(1)
Differential linearity error ± 0.8 – 1 ± 0.5 +1 LSB
Offset error – 3 +3 – 3 +3 LSB
Gain error – 4 +4 – 3 +3 LSB
Noise 33 33 μVrms
Power-supply rejection 70 70 dB
SAMPLING DYNAMICS
Conversion time 12 12 Clk Cycles
Acquisition time 1.5 1.5 Clk Cycles
Throughput rate 200 200 kHz
DYNAMIC CHARACTERISTICS
Total harmonic distortion V
IN
= 5V
PP
at 10kHz – 78 – 78 dB
SINAD V
IN
= 5V
PP
at 10kHz 71 71 dB
Spurious-free dynamic range V
IN
= 5V
PP
at 10kHz 79 79 dB
REFERENCE OUTPUT
Voltage range 0.05 V
CC
0.05 V
CC
V
CS = GND, f
SAMPLE
= 0Hz 5 5 G ΩResistance
CS = V
CC
5 5 G Ω
At code 710h 40 100 40 100 μA
Current drain f
SAMPLE
= 12.5kHz 2.5 2.5 μA
CS = V
CC
0.001 3 0.001 3 μA
DIGITAL INPUT/OUTPUT
Logic family CMOS CMOS
V
IH
I
IH
= +5 μA 3.0 5.5 3.0 5.5 V
V
IL
I
IL
= +5 μA – 0.3 0.8 – 0.3 0.8 VLogic levels
V
OH
I
OH
= – 250 μA 3.5 3.5 V
V
OL
I
OL
= 250 μA 0.4 0.4 V
Data format Straight Binary Straight Binary
POWER-SUPPLY REQUIREMENTS
V
CC
Specified performance 4.75 5.25 4.75 5.25 V
Quienscent current f
SAMPLE
= 200kHz 320 550 320 550 μA
Power down CS = V
CC
3 3 μA
TEMPERATURE RANGE
Specified performance – 40 +85 – 40 +85 °C
(1) LSB means least significant bit. With V
REF
equal to +5V, one LSB is 1.22mV.
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PIN CONFIGURATION
1
2
3
4
8
7
6
5
+VCC
DCLOCK
DOUT
CS/SHDN
VREF
+In
-In
GND
ADS7822
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
D, DGK, OR P PACKAGESO, MSOP, or DIP(TOP VIEW)
PIN ASSIGNMENTSPIN
DESCRIPTIONNAME NO.
V
REF
1 Reference input
+In 2 Noninverting input
– In 3 Inverting input. Connect to ground or to remote ground sense point.
GND 4 Ground
CS/SHDN 5 Chip select when low; Shutdown mode when high.
The serial output data word is comprised of 12 bits of data. In operation, the data are valid on the falling edge of DCLOCK. TheD
OUT
6
second clock pulse after the falling edge of CS enables the serial output. After one null bit, the data are valid for the next edges.
DCLOCK 7 Data clock synchronizes the serial data transfer and determines conversion speed.
+V
CC
8 Power supply
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TYPICAL CHARACTERISTICS
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
IntegralLinearityError(LSB)
0 2048 4095
Code
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
DifferentialLinearityError(LSB)
0 2048 4095
Code
350
300
250
200
150
100
50
SupplyCurrent( A)
m
-50 -25 0 25 50 75 100
Temperature( C)°
400
350
300
250
200
150
100
QuiescentCurrent( A)m
12345
V (V)
CC
1000
100
10
1
SampleRate(kHz)
12345
V (V)
CC
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
At T
A
= +25 °C, V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 75kHz, f
CLK
= 16 ×f
SAMPLE
, unless otherwise specified.
INTEGRAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs CODE vs CODE
Figure 1. Figure 2.
SUPPLY CURRENT POWER-DOWN SUPPLY CURRENTvs TEMPERATURE vs TEMPERATURE
Figure 3. Figure 4.
QUIESCENT CURRENT MAXIMUM SAMPLE RATEvs V
CC
vs V
CC
Figure 5. Figure 6.
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0.6
0.4
0.2
0
-0.2
-0.4
-0.6
Deltafrom25°C(LSB)
-50
-25 0 25 50 75 100
Temperature(°C)
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
Deltafrom25 C(LSB)°
-50 -25 0 25 50 75 100
Temperature( C)°
12.00
11.75
11.50
11.25
11.00
10.75
10.50
10.25
10.00
EffectiveNumberofBits(rms)
0.1 1 10
ReferenceVoltage(V)
V =5V
CC
10
9
8
7
6
5
4
3
2
1
0
Peak-to-PeakNoise(LSB)
0.1 1 10
ReferenceVoltage(V)
V =5V
CC
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 75kHz, f
CLK
= 16 ×f
SAMPLE
, unless otherwise specified.
CHANGE IN OFFSET CHANGE IN OFFSETvs REFERENCE VOLTAGE vs TEMPERATURE
Figure 7. Figure 8.
CHANGE IN GAIN CHANGE IN GAINvs REFERENCE VOLTAGE vs TEMPERATURE
Figure 9. Figure 10.
EFFECTIVE NUMBER OF BITS PEAK-TO-PEAK NOISEvs REFERENCE VOLTAGE vs REFERENCE VOLTAGE
Figure 11. Figure 12.
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0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
TotalHarmonicDistortion(dB)
1 10 100
Frequency(kHz)
80
70
60
50
40
30
20
10
0
Signal-to-(NoiseRatio+Distortion)(dB)
-40 -35 -30 -25 -20 -15 -10 -5 0
InputLevel(dB)
14
12
10
8
6
4
2
0
ReferenceCurrent( A)m
0 15 30 45 60 75
SampleRate(kHz)
14
12
10
8
6
4
2
ReferenceCurrent(A)
-50 -25 0 25 50 75 100
Temperature( C)°
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 75kHz, f
CLK
= 16 ×f
SAMPLE
, unless otherwise specified.
SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTIONSIGNAL-TO-NOISE RATIO vs FREQUENCY vs FREQUENCY
Figure 13. Figure 14.
SIGNAL-TO-(NOISE+DISTORTION) SIGNAL-TO-(NOISE+DISTORTION)vs FREQUENCY vs INPUT LEVEL
Figure 15. Figure 16.
REFERENCE CURRENT REFERENCE CURRENT vs TEMPERATUREvs SAMPLE RATE (Code = 710h)
Figure 17. Figure 18.
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0
-10
-20
-30
-40
-50
-60
-70
-80
-90
PSR(dB)
1k 10k 100k 1M 10M
RippleFrequency(Hz)
V =2.7V
CC
Ripple=500mVPP
V =1.25VDC
IN
V =2.5V
REF
PSR(dB)=20log(500mV/DV )
O
where DV =changeindigitalresult
O
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
PSR(dB)
1k10 10k1 100k 1M 10M
RippleFrequency(Hz)
V =5V
CC
Ripple=500mVPP
V =2.5VDC
IN
V =5V
REF
PSR(dB)=20log(500mV/DV )
O
where DV =changeindigitalresult
O
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
Deltafrom+2.5VReference(LSB)
12345
ReferenceVoltage(V)
V =5V
CC
ChangeinIntegral
Linearity(LSB)
ChangeinDifferential
Linearity(LSB)
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
TYPICAL CHARACTERISTICS (continued)At T
A
= +25 °C, V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 75kHz, f
CLK
= 16 ×f
SAMPLE
, unless otherwise specified.
POWER-SUPPLY REJECTION POWER-SUPPLY REJECTIONvs RIPPLE FREQUENCY vs RIPPLE FREQUENCY
Figure 19. Figure 20.
CHANGE IN INTEGRAL LINEARITYAND DIFFERENTIAL LINEARITYvs REFERENCE VOLTAGE
Figure 21.
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THEORY OF OPERATION
REFERENCE INPUT
ANALOG INPUT
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
The ADS7822 is a classic successive approximation The range of the – In input is limited to – 0.2V to +1V.register (SAR) A/D converter. The architecture is Because of this, the differential input can be used tobased on capacitive redistribution that inherently reject only small signals that are common to bothincludes a sample/hold function. The converter is inputs. Thus, the – In input is best used to sense afabricated on a 0.6 μCMOS process. The architecture remote signal ground that may move slightly withand process allow the ADS7822 to acquire and respect to the local ground potential.convert an analog signal at up to 200,000
The input current on the analog inputs depends on aconversions per second while consuming very little
number of factors: sample rate, input voltage, sourcepower.
impedance, and power-down mode. Essentially, theThe ADS7822 requires an external reference, an current into the ADS7822 charges the internalexternal clock, and a single power source (V
CC
). The capacitor array during the sample period. After thisexternal reference can be any voltage between 50mV capacitance has been fully charged, there is noand V
CC
. The value of the reference voltage directly further input current. The source of the analog inputsets the range of the analog input. The reference voltage must be able to charge the input capacitanceinput current depends on the conversion rate of the (25pF) to a 12-bit settling level within 1.5 clockADS7822. cycles. When the converter goes into the hold modeor while it is in the power-down mode, the inputThe external clock can vary between 10kHz (625Hz
impedance is greater than 1G Ω.throughput) and 3.2MHz (200kHz throughput). Theduty cycle of the clock is essentially unimportant as Care must be taken regarding the absolute analoglong as the minimum high and low times are at least input voltage. To maintain the linearity of the400ns for a supply range between 2.7V to 3.6V, or converter, the – In input should not drop below GND –125ns for a supply range between 4.75V to 5.25V. 200mV or exceed GND + 1V. The +In input shouldThe minimum clock frequency is set by the leakage always remain within the range of GND – 200mV toon the capacitors internal to the ADS7822. V
CC
+ 200mV. Outside of these ranges, the converterlinearity may not meet specifications.The analog input is provided to two input pins: +Inand – In. When a conversion is initiated, thedifferential input on these pins is sampled on theinternal capacitor array. While a conversion is in
The external reference sets the analog input range.progress, both inputs are disconnected from any
The ADS7822 operates with a reference in the rangeinternal function.
of 50mV to V
CC
. There are several importantimplications of this.The digital result of the conversion is clocked out bythe DCLOCK input and is provided serially, most
As the reference voltage is reduced, the analogsignificant bit first, on the D
OUT
pin. The digital data
voltage weight of each digital output code is reduced.that is provided on the D
OUT
pin is for the conversion
This is often referred to as the LSB (least significantcurrently in progress — there is no pipeline delay. It is
bit) size and is equal to the reference voltage dividedpossible to continue to clock the ADS7822 after the
by 4096. This means that any offset or gain errorconversion is complete and to obtain the serial data
inherent in the A/D converter will appear to increase,least significant bit first. See the Digital Interface
in terms of LSB size, as the reference voltage issection for more information.
reduced.
The +In and – In input pins allow for apseudo-differential input signal. Unlike someconverters of this type, the – In input is not resampledlater in the conversion cycle. When the convertergoes into the hold mode, the voltage differencebetween +In and – In is captured on the internalcapacitor array.
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DIGITAL INTERFACE
Signal Levels
Serial Interface
CS/SHDN
DOUT
DCLOCK
tDATA
tSUCS
tCYC
tCONV
Power
Down
tSMPL
Note:(1)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith CS LOW,
theA/DwilloutputLSB-Firstdatathenfollowedwithzeroesindefinitely.
B11
(MSB)
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
Null
Bit
Hi-ZHi-Z
B11 B10 B9 B8
Null
Bit
CS/SHDN
DOUT
DCLOCK
tCONV tDATA
tSUCS
tCSD
tCYC
PowerDown
tSMPL
Note:(1)Aftercompletingthedatatransfer,iffurtherclocksareappliedwith CS LOW,
theA/Dwilloutputzeroesindefinitely.
t enceinput:Duringthistime,thebiascurrentandthecomparatorpowerdownandtherefer
DATA
becomesahighimpedancenode,leavingtheCLKrunningtoclockoutLSB-firstdataorzeroes.
B11
(MSB)
B10 B9 B8 B7 B6 B5 B4 B4B3 B3B2 B2B1 B1B0
Null
Bit
Hi-Z Hi-Z
B5 B6 B7 B8 B9 B10 B11
(1)
tCSD
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
The noise inherent in the converter will also appear toincrease with lower LSB size. With a 2.5V reference,the internal noise of the converter typically contributesonly 0.32 LSB peak-to-peak of potential error to the
The digital inputs of the ADS7822 can accommodateoutput code. When the external reference is 50mV,
logic levels up to 6V regardless of the value of V
CC
.the potential error contribution from the internal noise
Thus, the ADS7822 can be powered at 3V and stillwill be 50 times larger — 16 LSBs. The errors due to
accept inputs from logic powered at 5V.the internal noise are gaussian in nature and can bereduced by averaging consecutive conversion results.
The CMOS digital output (D
OUT
) will swing 0V to V
CC
.If V
CC
is 3V and this output is connected to a 5VFor more information regarding noise, consult the
CMOS logic input, then that IC may require moretypical characteristic curves Effective Number of Bits
supply current than normal and may have a slightlyvs Reference Voltage and Peak-to-Peak Noise vs
longer propagation delay.Reference Voltage . Note that the effective number ofbits (ENOB) figure is calculated based on theconverter signal-to-(noise + distortion) ratio with a1kHz, 0dB input signal. SINAD is related to ENOB as
The ADS7822 communicates with microprocessorsfollows:
and other digital systems via a synchronous 3-wireserial interface, as shown in Figure 22 and Table 1 .SINAD = 6.02 • ENOB + 1.76
The DCLOCK signal synchronizes the data transferWith lower reference voltages, extra care should be with each bit being transmitted on the falling edge oftaken to provide a clean layout including adequate DCLOCK. Most receiving systems will capture thebypassing, a clean power supply, a low-noise bitstream on the rising edge of DCLOCK. However, ifreference, and a low-noise input signal. Because the the minimum hold time for D
OUT
is acceptable, theLSB size is lower, the converter will also be more system can use the falling edge of DCLOCK tosensitive to external sources of error such as nearby capture each bit.digital signals and electromagnetic interference.
Figure 22. Basic Timing Diagrams
Copyright © 1996 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): ADS7822
www.ti.com
DOUT
1.4V
TestPoint
3kW
100pF
CLOAD
LoadCircuitfort ,t ,andt
dDO r f
VoltageWaveformsforD RiseandFallTimes,t ,t
OUT r f
VoltageWaveformsforD DelayTimes,t
OUT dDO
VoltageWaveformsfortdis VoltageWaveformsforten
LoadCircuitfort andt
dis en
tr
DOUT
VOH
VOL
tf
DOUT
TestPoint
t Waveform2,t
dis en
VCC
t Waveform1
dis
100pF
CLOAD
3kW
tdis
CS/SHDN
DOUT
Waveform1(1)
DOUT
Waveform2(2)
90%
10%
VIH
1
B11
2
ten
CS/SHDN
DCLOCK
VOL
DOUT
tdDO
DOUT
DCLOCK
VOH
VOL
VIL
thDO
NOTES:(1)Waveform1isforanoutputwithinternalconditionssuchthattheoutput
isHIGHunlessdisabledbytheoutputcontrol.
(2)Waveform2isforanoutputwithinternalconditionssuchthattheoutput
isLOWunlessdisabledbytheoutputcontrol.
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
Table 1. Timing Specifications ( – 40 °C to +85 °C)V
CC
= 2.7V V
CC
= 5VSYMBOL DESCRIPTION UNITSMIN TYP MAX MIN TYP MAX
t
SMPL
Analog input sample time 1.5 2.0 1.5 2.0 Clk Cycles
t
CONV
Conversion time 12 12 Clk Cycles
t
CYC
Cycle time 16 16 Clk Cycles
t
CSD
CS falling to DCLOCK low 0 0 ns
t
SUCS
CS falling to DCLOCK rising 0.03 1000 0.03 1000 μs
t
hDO
DCLOCK falling to current D
OUT
not valid 15 15 ns
t
dDO
DCLOCK falling to next D
OUT
valid 130 200 85 150 ns
t
dis
CS rising to D
OUT
tri-state 40 80 25 50 ns
t
en
DCLOCK falling to D
OUT
enabled 75 175 50 100 ns
t
f
D
OUT
fall time 90 200 70 100 ns
t
r
D
OUT
rise time 110 200 60 100 ns
Figure 23. Timing Diagrams and Test Circuits for the Parameters in Table 1
12 Submit Documentation Feedback Copyright © 1996 – 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS7822
www.ti.com
Data Format
1000
100
10
1
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
V =5.0V
CC
V =5.0V
REF
V =2.7V
CC
V =2.5V
REF
T =25 C°
A
f =1.2MHz
CLK
POWER DISSIPATION
1000
100
10
1
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
T =25 C°
A
V =2.7V
CC
V =2.5V
REF
f =16 f·
CLK SAMPLE
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
A falling CS signal initiates the conversion and data transition (as is typical for digital CMOS components),transfer. The first 1.5 to 2.0 clock periods of the but also uses some current for the analog circuitry,conversion cycle are used to sample the input signal. such as the comparator. The analog sectionAfter the second falling DCLOCK edge, D
OUT
is dissipates power continuously, until the power-downenabled and outputs a low value for one clock period. mode is entered.For the next 12 DCLOCK periods, D
OUT
outputs the
Figure 24 shows the current consumption of theconversion result, most significant bit first.
ADS7822 versus sample rate. For this graph, theAfter the least significant bit (B0) has been output, converter is clocked at 1.2MHz regardless of thesubsequent clocks repeat the output data, but in a sample rate — CS is high for the remaining sampleleast significant bit first format. After the most period. Figure 25 also shows current consumptionsignificant bit (B11) has been repeated, DOUT will versus sample rate. However, in this case, thetri-state. Subsequent clocks have no effect on the DCLOCK period is 1/16th of the sample period — CSconverter. A new conversion is initiated only when CS is high for one DCLOCK cycle out of every 16.is taken high and returned low.
The output data from the ADS7822 is in straightbinary format, as shown in Table 2 . This tablerepresents the ideal output code for the given inputvoltage and does not include the effects of offset,gain error, or noise.
Table 2. Ideal Input Voltages and Output CodesDIGITAL OUTPUTDESCRIPTION ANALOG VALUE
STRAIGHT BINARY
Full-Scale range V
REF
Least significant
V
REF
/4096bit (LSB) BINARY CODE HEX CODE
Full-Scale V
REF
– 1 LSB 1111 1111 1111 FFF
Figure 24. Maintaining f
CLK
at the HighestMidscale V
REF
/2 1000 0000 0000 800
Possible Rate Allows the Supply Current to DropMidscale – 1 LSB V
REF
/2 – 1 LSB 0111 1111 1111 7FF
Linearly with the Sample RateZero 0V 0000 0000 0000 000
The architecture of the converter, the semiconductorfabrication process, and a careful design allow theADS7822 to convert at up to a 75kHz rate whilerequiring very little power. Still, for the absolutelowest power dissipation, there are several things tokeep in mind.
The power dissipation of the ADS7822 scales directlywith conversion rate. So, the first step to achievingthe lowest power dissipation is to find the lowestconversion rate that will satisfy the requirements ofthe system.
In addition, the ADS7822 goes into power-downmode under two conditions: when the conversion iscomplete and whenever CS is high (see Figure 22 ).
Figure 25. Scaling f
CLK
Reduces the SupplyCurrent Only Slightly with the Sample RateIdeally, each conversion should occur as quickly aspossible; preferably, at a 1.2MHz clock rate. Thisway, the converter spends the longest possible timein the power-down mode. This is very important sincethe converter not only uses power on each DCLOCK
Copyright © 1996 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): ADS7822
www.ti.com
Short Cycling
10.0
8.0
6.0
4.0
2.0
0.0
0.00
SupplyCurrent( A)m
0.1 1 10 100
SampleRate(kHz)
0.050
T =25 C°
A
V =2.7V
CC
V =2.5V
REF
f =16 f·
CLK SAMPLE
CS LOW(GND)
CS HIGH(V )CC
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
There is an important distinction between thepower-down mode that is entered after a conversion
Power dissipation can also be reduced by loweringis complete and the full power-down mode that is
the power-supply voltage and the reference voltage.enabled when CS is high. While both shutdown the
The ADS7822 operates over a V
CC
range of 2.0V toanalog section, the digital section is completely
5.25V. It will run up to a 200kHz throughput rate overshutdown only when CS is high. Thus, if CS is left
a supply range of 4.75V to 5.25V; therefore, it can below at the end of a conversion and the converter is
clocked at up to 3.2MHz. However, at voltages belowcontinually clocked, the power consumption will not
2.7V, the converter does not run at a 75kHz samplebe as low as when CS is high; see Figure 26 for more
rate. See the Typical Characteristic curves for moreinformation.
information regarding power-supply voltage andmaximum sample rate.
Another way of saving power is to use the CS signalto short-cycle the conversion. Because the ADS7822places the latest data bit on the D
OUT
line as it isgenerated, the converter can easily be short-cycled.This term means that the conversion can beterminated at any time. For example, if only eight bitsof the conversion result are needed, then theconversion can be terminated (by pulling CS high)after the eighth bit has been clocked out.
This technique can be used to lower the powerdissipation (or to increase the conversion rate) inthose applications where an analog signal is beingmonitored until some condition becomes true. ForFigure 26. Shutdown Current with CS High isTypically 50nA, Regardless of the Clock. example, if the signal is outside a predeterminedShutdown Current with CS Low varies with
range, the full 12-bit conversion result may not beSample Rate.
needed. If so, the conversion can be terminated afterthe first n-bits, where nmight be as low as 3 or 4.This results in lower power dissipation in both theconverter and the rest of the system, because theyspend more time in the power-down mode.
14 Submit Documentation Feedback Copyright © 1996 – 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS7822
www.ti.com
LAYOUT
APPLICATION CIRCUITS
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
Also, keep in mind that the ADS7822 offers noinherent rejection of noise or voltage variation inFor optimum performance, care should be taken with
regards to the reference input. This is of particularthe physical layout of the ADS7822 circuitry. This is
concern when the reference input is tied to the powerparticularly true if the reference voltage is low and/or
supply. Any noise and ripple from the supply willthe conversion rate is high. At a 75kHz conversion
appear directly in the digital results. Whilerate, the ADS7822 makes a bit decision every 830ns.
high-frequency noise can be filtered out as describedIf the supply range is limited to 4.75V to 5.25V, then
in the previous paragraph, voltage variation due toup to a 200kHz conversion rate can be used, which
the line frequency (50Hz or 60Hz), can be difficult toreduces the bit decision time to 312ns. That is, for
remove.each subsequent bit decision, the digital output mustbe updated with the results of the last bit decision, The GND pin on the ADS7822 should be placed on athe capacitor array appropriately switched and clean ground point. In many cases, this will be thecharged, and the input to the comparator settled to a analog ground. Avoid connecting the GND pin too12-bit level all within one clock cycle. close to the grounding point for a microprocessor,microcontroller, or digital signal processor. If needed,The basic SAR architecture is sensitive to spikes on
run a ground trace directly from the converter to thethe power supply, reference, and ground connections
power-supply connection point. The ideal layout willthat occur just prior to latching the comparator output.
include an analog ground plane for the converter andThus, during any single conversion for an n-bit SAR
associated analog circuitry.converter, there are nwindows in which largeexternal transient voltages can easily affect theconversion result. Such spikes might originate fromswitching power supplies, digital logic, and
Figure 27 and Figure 28 show some typicalhigh-power devices, to name a few. This particular
application circuits for the ADS7822. Figure 27 usessource of error can be very difficult to track down if
an ADS7822 and a multiplexer to provide for athe glitch is almost synchronous to the converter
flexible data acquisition circuit. A resistor stringDCLOCK signal because the phase difference
provides for various voltages at the multiplexer input.between the two changes with time and temperature,
The selected voltage is buffered and driven into V
REF
.causing sporadic misoperation.
As shown in Figure 27 , the input range of theADS7822 is programmable to 100mV, 200mV,With this in mind, power to the ADS7822 should be
300mV, or 400mV. The 100mV range would beclean and well-bypassed. A 0.1 μF ceramic bypass
useful for sensors such as the thermocouple shown.capacitor should be placed as close to the ADS7822package as possible. In addition, a 1 μF to 10 μF
Figure 28 shows a basic data acquisition system. Thecapacitor and a 5 Ωor 10 Ωseries resistor can be
ADS7822 input range is 0V to V
CC
, as the referenceused to lowpass filter a noisy supply.
input is connected directly to the power supply. The5Ωresistor and 1 μF to 10 μF capacitor filter theThe reference should be similarly bypassed with a
microcontroller noise on the supply, as well as any0.1 μF capacitor. Again, a series resistor and large
high-frequency noise from the supply itself. The exactcapacitor can be used to lowpass filter the reference
values should be picked such that the filter providesvoltage. If the reference voltage originates from an op
adequate rejection of the noise.amp, be careful that the op amp can drive the bypasscapacitor without oscillation (the series resistor canhelp in this case). Keep in mind that while theADS7822 draws very little current from the referenceon average, there are still instantaneous currentdemands placed on the external reference circuitry.
Copyright © 1996 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS7822
www.ti.com
ADS7822
P
DCLOCK
DOUT
CS/SHDN
A0
A1
U3
U4
U1
U2
Thermocouple
ISOThermalBlock
Mux
OPA237 0.3V
0.4V
0.2V
0.1V
+3V
R2
59kW
R4
1kW
R3
500kW
R5
500W
R7
5W
C3
0.1mF
C4
10mFC5
0.1mF
R6
1MW
R1
150kW
D1
TC2
TC1
TC3
+3V
C2
0.1mFC1
10mF
+3V
R8
26kW
R9
1kW
R10
1kW
R11
1kW
R12
1kW
VREF
3-Wire
Interface
ADS7822
VCC
CS
DOUT
DCLOCK
VREF
+In
-In
GND
+
+
5W
1mFto
10mF
1mFto
10mF
0.1mF
Microcontroller
+2.7Vto+3.6V
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
Figure 27. Thermocouple Application Using a Mux to Scale the Input Range of the ADS7822
Figure 28. Basic Data Acquisition System
16 Submit Documentation Feedback Copyright © 1996 – 2007, Texas Instruments Incorporated
Product Folder Link(s): ADS7822
www.ti.com
ADS7822
SBAS062C – JANUARY 1996 – REVISED AUGUST 2007
Revision History
Changes from Revision B (May 2006) to Revision C ...................................................................................................... Page
•Added – GND to absolute input range test conditions .......................................................................................................... 3•Added – GND to absolute input range test conditions .......................................................................................................... 3•Changed V
CC
min from 3.6 V to 2.7 V ................................................................................................................................... 3•Changed V
CC
max from 5.25 V to 3.6 V ................................................................................................................................ 3•Changed V
CC
min from 3.6 V to 2.7 V ................................................................................................................................... 3•Changed V
CC
max from 5.25 V to 3.6 V ................................................................................................................................ 3•Changed V
CC
min from 3.6 V to 2.7 V ................................................................................................................................... 3•Changed V
CC
max from 5.25 V to 3.6 V ................................................................................................................................ 3•Added – GND to absolute input range test conditions .......................................................................................................... 4•Added – GND to absolute input range test conditions .......................................................................................................... 4
Copyright © 1996 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS7822
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7822E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EC/250 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EC/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EC/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822EC/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-2-260C-1 YEAR
ADS7822P ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS7822PB ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS7822PBG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS7822PC ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS7822PCG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS7822PG4 ACTIVE PDIP P 8 50 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
ADS7822U ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UB ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UBG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UC ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UC/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UC/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UCG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7822UG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS7822 :
•Automotive: ADS7822-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7822E/250 VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822EB/250 VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822EC/250 VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822EC/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
ADS7822U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7822UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
ADS7822UC/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7822E/250 VSSOP DGK 8 250 367.0 367.0 35.0
ADS7822E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0
ADS7822EB/250 VSSOP DGK 8 250 367.0 367.0 35.0
ADS7822EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0
ADS7822EC/250 VSSOP DGK 8 250 367.0 367.0 35.0
ADS7822EC/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0
ADS7822U/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS7822UB/2K5 SOIC D 8 2500 367.0 367.0 35.0
ADS7822UC/2K5 SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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