TPS51200DRCRG4 - Texas Instruments

FEATURES APPLICATIONS

DESCRIPTION

STANDARD DDR APPLICATION

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

3.3 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VLDOIN

VTT

VDDQ

UDG-08025

TPS51200

SLUS812 – FEBRUARY 2008www.ti.com

SINK/SOURCE DDR TERMINATION REGULATOR

•Memory Termination Regulator for DDR,2

•Input Voltage: Supports 2.5-V Rail and 3.3-V

DDR2, DDR3, and Low Power DDR3/DDR4Rail

•Notebook/Desktop/Server•VLDOIN Voltage Range: 1.1 V to 3.5 V

•Telecom/Datacom, GSM Base Station,•Sink/Source Termination Regulator Includes

LCD-TV/PDP-TV, Copier/Printer, Set-Top BoxDroop Compensation

•Requires Minimum Output Capacitance of20- µF (typically 3 ×10- µF MLCCs) for Memory

The TPS51200 is a sink/source Double Data RateTermination Applications (DDR)

(DDR) termination regulator specifically designed for•PGOOD to Monitor Output Regulation

low input voltage, low-cost, low-noise systems where•EN Input

space is a key consideration.•REFIN Input Allows for Flexible Input Tracking

The TPS51200 maintains a fast transient responseEither Directly or Through Resistor Divider

and only requires a minimum output capacitance of•Remote Sensing (VOSNS) 20 µF. The TPS51200 supports a remote sensingfunction and all power requirements for DDR, DDR2,•± 10-mA Buffered Reference (REFOUT)

DDR3, and Low Power DDR3/DDR4 VTT bus•Built-in Soft Start, UVLO and OCL

termination.•Thermal Shutdown

In addition, the TPS51200 provides an open-drain•Meets DDR, DDR2 JEDEC Specifications;

PGOOD signal to monitor the output regulation andSupports DDR3 and Low-Power DDR3/DDR4

an EN signal that can be used to discharge VTTVTT Applications

during S3 (suspend to RAM) for DDR applications.•SON-10 PowerPAD™Package

The TPS51200 is available in the thermally-efficientSON-10 PowerPAD package, and is rated bothGreen and Pb-free. It is specified from -40 °C to+85 °C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

(1)

DISSIPATION RATINGS TABLE

(1)

RECOMMENDED OPERATING CONDITIONS

TPS51200

SLUS812 – FEBRUARY 2008

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

PACKAGE DEVICE NUMBER PINS MEDIUM MINIMUM

QUANTITY

TPS51200DRCT 250– 40 °C to 85 °C DRC Plastic Small Outline 10 Tape and ReelTPS51200DRCR 3000

Over operating free-air temperature range, unless otherwise noted.

VALUE UNIT

VIN, VLDOIN, VOSNS, REFIN – 0.3 to 3.6Input voltage range

(2)

EN – 0.3 to 6.5 VPGND to GND – 0.3 to 0.3VO, REFOUT – 0.3 to 3.6Output voltage range

(2)

VPGOOD – 0.3 to 6.5T

stg

Storage temperature – 55 to 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

DERATING FACTOR T

= 85 °CT

= 25 °CPACKAGE POWER RATING ABOVE T

= 25 °C POWER RATING

10-Pin SON 1.92 W 19 mW/ °C 0.79 W

(1) PowerPAD size: 3.0 ×1.9 mm, 4 standard thermal vias. Based on the above environment, junction to thermal pad resistance θ

is10.24 °C/W. Junction to ambient thermal resistance θ

is 52.06 °C/W.

PARAMETER MIN TYP MAX UNIT

Supply voltages VIN 2.375 3.500EN, VLDOIN, VOSNS – 0.1 3.5REFIN 0.5 1.8

VVoltage range VO, PGOOD – 0.1 3.5REFOUT – 0.1 1.8PGND – 0.1 0.1Operating free-air temperature, T

– 40 85 °C

Product Folder Link(s): TPS51200

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ELECTRICAL CHARACTERISTICS

TPS51200

SLUS812 – FEBRUARY 2008

Over recommended free-air temperature range, V

VIN

= 3.3 V,V

VLDOIN

= 1.8 V, V

REFIN

= 0.9 V, V

VOSNS

= 0.9 V, V

= V

VIN

, C

OUT= 3 ×10 µF and circuit shown in Section 1 . (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

Supply current T

= 25 °C, V

= 3.3 V, No Load 0.7 1 mA

= 25 °C, V

= 0 V, V

REFIN

= 0, No Load 65 80I

IN(SDN)

Shutdown current µAT

= 25 °C, V

= 0 V, V

REFIN

> 0.4 V, No Load 200 400

LDOIN

Supply current ofVLDOIN T

= 25 °C, V

= 3.3 V, No Load 1 50 µA

LDOIN(SDN)

Shutdown current of VLDOIN T

= 25 °C, V

= 0 V, No Load 0.1 50 µA

INPUT CURRENT

REFIN

Input current, REFIN V

= 3.3 V 1 µA

VO OUTPUT

1.25 VV

REFOUT

= 1.25 V (DDR1), I

= 0 A

– 15 15 mV

0.9 VV

VOSNS

Output DC voltage, VO V

REFOUT

= 0.9 V (DDR2), I

= 0 A

– 15 15 mV

0.75 VV

LDOIN

= 1.5 V, V

REFOUT

= 0.75 V (DDR3), I

= 0 A

– 15 15 mV

Output voltage tolerance toV

VOTOL

– 2A < I

< 2A – 25 25 mVREFOUT

VOSRCL

VO source vurrent Limit With reference to REFOUT, V

OSNS

= 90% ×V

REFOUT

3 4.5 A

VOSNCL

VO sink current Limit With reference to REFOUT, V

OSNS

= 110% ×V

REFOUT

3.5 5.5 A

DSCHRG

Discharge current, VO V

REFIN

= 0 V, V

= 0.3 V, V

= 0 V, T

= 25 °C 18 25 Ω

POWERGOOD COMPARATOR

PGOOD window lower threshold with respect to REFOUT – 23.5% – 20% – 17.5%

TH(PG)

VO PGOOD threshold PGOOD window upper threshold with respect to REFOUT 17.5% 20% 23.5%

PGOOD hysteresis 5%

PGSTUPDLY

PGOOD startup delay Startup rising edge, VOSNS within 15% of REFOUT 2 ms

PGOODLOW

Output low voltage I

SINK

= 4 mA 0.4 V

PBADDLY

PGOOD bad delay VOSNS is outside of the ± 20% PGOOD window 10 µs

OSNS

= V

REFIN

(PGOOD high impedance),I

PGOODLK

Leakage current

(1)

1µAPGOOD = V

+ 0.2 V

REFIN AND REFOUT

REFIN

REFIN voltage range 0.5 1.8 V

REFINUVLO

REFIN undervoltage lockout REFIN rising 360 390 420 mV

REFIN undervoltage lockoutV

REFINUVHYS

20 mVhysteresis

REFOUT

REFOUT voltage REFIN V

– 10 mA < I

REFOUT

< 10 mA, V

REFIN

= 1.25 V – 15 15

– 10 mA < I

REFOUT

< 10 mA, V

VREFIN

= 0.9 V – 15 15 mVREFOUT voltage tolerance toV

REFOUTTOL

REFIN

– 10 mA < I

REFOUT

< 10 mA, V

REFIN

= 0.75V – 15 15

– 10 mA < I

REFOUT

< 10 mA, V

REFIN

= 0.6 V – 15 15

REFOUTSRCL

REFOUT source current limit V

REFOUT

= 0 V 10 40 mA

REFOUTSNCL

REFOUT sink current limit V

REFOUT

= 0 V 10 40 mA

(1) Ensured by design. Not production tested.

Product Folder Link(s): TPS51200

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TPS51200

SLUS812 – FEBRUARY 2008

ELECTRICAL CHARACTERISTICS (continued)Over recommended free-air temperature range, V

VIN

= 3.3 V,V

VLDOIN

= 1.8 V, V

REFIN

= 0.9 V, V

VOSNS

= 0.9 V, V

= V

VIN

, C

OUT= 3 ×10 µF and circuit shown in Section 1 . (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UVLO / EN LOGIC THRESHOLD

Wake up, T

= 25 °C 2.2 2.3 2.375 VV

VINUVVIN

UVLO threshold

Hysteresis 50 mV

ENIH

High-level input voltage Enable 1.7

ENIL

Low-level input voltage Enable 0.3 V

ENYST

Hysteresis voltage Enable 0.5

ENLEAK

Logic input leakage current EN, T

= 25 °C – 1 1 µA

THERMAL SHUTDOWN

Shutdown temperature 150T

SON

Thermal shutdown threshold

(2)

°CHysteresis 25

(2) Ensured by design. Not production tested.

Product Folder Link(s): TPS51200

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DEVICE INFORMATION

DRC PACKAGE

6VOSNS

PGND

VLDOIN

REFIN

REFOUT

GND

PGOOD

VIN

TPS51200

(Bottom View)

TPS51200

SLUS812 – FEBRUARY 2008

TERMINAL FUNCTIONS

TERMINAL

NAME NO. I/O DESCRIPTION

EN 7 I For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFFfunction.GND 8 – Ground.Signal ground. Connect to negative terminal of the output capacitor.PGND 4 – Power ground output for the LDOPGOOD 9 O PGOOD output. Indicates regulation.REFIN 1 I Reference inputREFOUT 6 O Reference output. Connect to GND through 0.1- µF ceramic capacitor.VIN 10 I 2.5-V or 3.3-V power supply A ceramic decoupling capacitor with a value between 1- µF and 4.7- µF isrequired.VLDOIN 2 I Supply voltage for the LDOVO 3 O Power output for the LDOVOSNS 5 I Voltage sense output for the LDO. Connect to positive terminal of the output capacitor or the load.

Product Folder Link(s): TPS51200

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FUNCTIONAL BLOCK DIAGRAM

1REFIN

10VIN

7EN

5VOSNS

8GND

2.3 V

REFINOK

ENVTT

2 VLDOIN

6 REFOUT

4 PGND

3 VO

9 PGOOD

Startup

Delay

DchgREF

DchgVTT

UVLO

UDG-08019

TPS51200

SLUS812 – FEBRUARY 2008

Product Folder Link(s): TPS51200

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DETAILED DESCRIPTION

VO SINK/SOURCE REGULATOR

REFERENCE INPUT (REFIN)

REFERENCE OUTPUT (REFOUT)

SOFT-START

EN CONTROL (EN)

POWERGOOD FUNCTION (PGOOD)

VO CURRENT PROTECTION

VIN UVLO PROTECTION

TPS51200

SLUS812 – FEBRUARY 2008

The TPS51200 is a sink/source tracking termination regulator specifically designed for low input voltage,low-cost, and low external component count systems where space is a key application parameter. TheTPS51200 integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcingand sinking current. The LDO regulator employs a fast feedback loop so that small ceramic capacitors can beused to support the fast load transient response. To achieve tight regulation with minimum effect of traceresistance, a remote sensing terminal, VOSNS, should be connected to the positive terminal of the outputcapacitor(s) as a separate trace from the high current path from VO.

The output voltage, VO, is regulated to REFOUT. When REFIN is configured for standard DDR terminationapplications, REFIN can be set by an external equivalent ratio voltage divider connected to the memory supplybus (VDDQ). The TPS51200 supports REFIN voltage from 0.5 V to 1.8 V, making it versatile and ideal for manytypes of low-power LDO applications.

When it is configured for DDR termination applications, REFOUT generates the DDR VTT reference voltage forthe memory application. It is capable of supporting both a sourcing and sinking load of 10 mA. REFOUTbecomes active when REFIN voltage rises to 0.390 V and VIN is above the UVLO threshold. When REFOUT isless than 0.375 V, it is disabled and subsequently discharges to GND through an internal 10-k ΩMOSFET.REFOUT is independent of the EN pin state.

The soft-start function of the VO pin is achieved via a current clamp. The current clamp allows the outputcapacitors to be charged with low and constant current, providing a linear ramp-up of the output voltage. WhenVO is outside of the powergood window, the current clamp level is one-half of the full overcurrent limit (OCL)level. When VO rises or falls within the PGOOD window, the current clamp level switches to the full OCL level.The soft-start function is completely symmetrical; it works not only from GND to the REFOUT voltage, but alsofrom VLDOIN to the REFOUT voltage.

When EN is driven high, the TPS51200 VO regulator begins normal operation. When EN is driven low, VO isdischarges to GND through an internal 18- ΩMOSFET. REFOUT remains on when EN is driven low.

The TPS51200 provides an open-drain PGOOD output that goes high when the VO output is within ± 20% ofREFOUT. PGOOD de-asserts within 10 µs after the output exceeds the size of the powergood window. Duringinitial VO startup, PGOOD asserts high 2 ms (typ) after the VO enters power good window. Because PGOOD isan open-drain output, a 100-k Ω, pull-up resistor between PGOOD and a stable active supply voltage rail isrequired.

The LDO has a constant overcurrent limit (OCL). Note that the OCL level reduces by one-half when the outputvoltage is not within the powergood window. This reduction is a non-latch protection.

For VIN undervoltage lockout (UVLO) protection, the TPS51200 monitors VIN voltage. When the VIN voltage islower than the UVLO threshold voltage, both the VO and REFOUT regulators are powered off. This shutdown isa non-latch protection.

Product Folder Link(s): TPS51200

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THERMAL SHUTDOWN

TPS51200

SLUS812 – FEBRUARY 2008

The TPS51200 monitors the its junction temperature. If the device junction temperature exceeds its thresholdvalue, (typically 150 °C), the VO and REFOUT regulators are both shut off, discharged by the internal dischargeMOSFETs. This shutdown is a non-latch protection.

Product Folder Link(s): TPS51200

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APPLICATION INFORMATION

VIN CAPACITOR

VLDO INPUT CAPACITOR

OUTPUT CAPACITOR

Low VIN Applications

S3 and Pseudo-S5 Support

Tracking Startup and Shutdown

TPS51200

SLUS812 – FEBRUARY 2008

Add a ceramic capacitor, with a value between 1.0- µF and 4.7- µF, placed close to the VIN pin, to stabilize thebias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply.

Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase ofsource current is supplied mostly by the charge from the VLDOIN input capacitor. Use a 10- µF (or greater)ceramic capacitor to supply this transient charge. Provide more input capacitance as more output capacitance isused at VO. In general, use one-half of the C

OUT

value for input.

For stable operation, the total capacitance of the VO output terminal must be greater than 20 µF. Attach three,10- µF ceramic capacitors in parallel to minimize the effect of equivalent series resistance (ESR) and equivalentseries inductance (ESL). If the ESR is greater than 2 m Ω, insert an R-C filter between the output and the VOSNSinput to achieve loop stability. The R-C filter time constant should be almost the same as or slightly lower thanthe time constant of the output capacitor and its ESR.

TPS51200 can be used in an application system where either a 2.5-V rail or a 3.3-V rail is available. If only a 5-Vrail is available, TPS51100 can be used instead. The TPS51200 minimum input voltage requirement is 2.375 V.If a 2.5-V rail is used, ensure that the absolute minimum voltage (both DC and transient) at the device pin is be2.375 V or greater. The voltage tolerance for a 2.5-V rail input is between – 5% and 5% accuracy, or better.

The TPS51200 provides S3 support by an EN function. The EN pin could be connected to an SLP_S3 signal inthe end application. Both REFOUT and VO are on when EN = high (S0 state). REFOUT is maintained while VOis turned off and discharged via an internal discharge MOSFET when EN = low (S3 state). When EN = low andthe REFIN voltage is less than 0.390 V, TPS51200 enters pseudo-S5 state. Both VO and REFOUT outputs areturned off and discharged to GND through internal MOSFETs when pseudo-S5 support is engaged (S4/S5state). Figure 1 shows a typical startup and shutdown timing diagram for an application that uses S3 andpseudo-S5 support.

The TPS51200 also supports tracking startup and shutdown when EN is tied directly to the system bus and notused to turn on or turn off the device. During tracking startup, VO follows REFOUT once REFIN voltage isgreater than 0.39 V. REFIN follows the rise of VDDQ rail via a voltage divider. The typical soft-start time for theVDDQ rail is approximately 3 ms, however it may vary depending on the system configuration. The SS time ofthe VO output no longer depends on the OCL setting, but it is a function of the SS time of the VDDQ rail.PGOOD is asserted 2 ms after VO is within ± 20% of REFOUT. During tracking shutdown, VO falls followingREFOUT until REFOUT reaches 0.37 V. Once REFOUT falls below 0.37 V, the internal discharge MOSFETs areturned on and quickly discharge both REFOUT and VO to GND. PGOOD is deasserted once VO is beyond the± 20% range of REFOUT. Figure 2 shows the typical timing diagram for an application that uses tracking startupand shutdown.

Product Folder Link(s): TPS51200

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PGOOD

2 ms

REFIN

REFOUT

(VTTREF)

VLDOIN

VVDDQ = 1.5 V

3.3VIN

(S3_SLP)

Tss

TSS =

COx VO

IOOCL

VVO = 0.75 V

UDG-08021

0.390 V 0.370 V

PGOOD

tSS determined

by the SS time

of VLDOIN

2ms

VVO = 0.75 V

REFOUT

(VTTREF)

REFIN

VLDOIN

3.3VIN

UDG-08020

TPS51200

SLUS812 – FEBRUARY 2008

Figure 1. Typical Timing Diagram for S3 and pseudo-S5 Support

Figure 2. Typical Timing Diagram of Tracking Startup and Shutdown

Product Folder Link(s): TPS51200

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Output Tolerance Consideration for VTT DIMM Applications

DDR3 240 Pin Socket

TPS51200

10 mF 10 mF 10 mF

SPD

Vtt

Vdd

Vtt

Vdd

UDG-08022

20 W

VOUT VIN

25 W

VTT

VDDQ

Ouput

Buffer

(Driver)

Receiver

VSS

UDG-08023

TPS51200

SLUS812 – FEBRUARY 2008

The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 3 ). The DDRmemory termination structure determines the main characteristics of the VTT rail, which is to be able to sink andsource current while maintaining acceptable VTT tolerance. See Figure 4 for typical characteristics for a singlememory cell.

Figure 3. Typical Application Diagram for DDR3 VTT DIMM using TPS51200

Figure 4. DDR Physical Signal System Bi-Directional SSTL Signaling

In Figure 4 , when Q1 is on and Q2 is off:

•Current flows from VDDQ via the termination resistor to VTT•VTT sinks currentIn Figure 4 , when Q2 is on and Q1 is off:

•Current flows from VTT via the termination resistor to GND•VTT sources current

Product Folder Link(s): TPS51200

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UGBW

OUT

F2 C

=´ p ´

(1)

TPS51200

SLUS812 – FEBRUARY 2008

Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand thetolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDRJESD8-9B May 2002; DDR2 JESD8-15A Sept 2003).VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions

The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.

The TPS51200 ensures the regulator output voltage to be:VTTREF – 25 mV < VTT < VTTREF + 25mV, for both DC and AC conditions and – 2 A < I

VTT

< 2 A

The regulator output voltage is measured at the regulator side, not the load side. The tolerance is applicable toDDR, DDR2, DDR3 and Low Power DDR3/DDR4 applications (see Table 1 for detailed information). To meet thestability requirement, a minimum output capacitance of 20 µF is needed. Considering the actual tolerance on theMLCC capacitors, three 10- µF ceramic capacitors are sufficient to meet the above requirement.

Table 1. DDR, DDR2, DDR3 and LP DDR3 Termination Technology and Their Differences

Low PowerDDR DDR2 DR3 DDR3

FSB Data Rates 200, 266, 333 and 400 MHz 400, 533, 677 and 800 MHz 800, 1066, 1330 and 1600 MHz Same as DDR3On-die termination for data group. On-die termination for data group.Motherboard termination toTermination VTT termination for address, VTT termination for address, Same as DDR3VTT for all signals

command and control signals command and control signalsNot as demanding Not as demanding Same as DDR3Only 34 signals (address, Only 34 signals (address,Max source/sink transient

• command, control) tied to • command, control) tied toTermination

currents of up to 2.6A to

VTT VTTCurrent Demand

2.9A

• ODT handles data signals • ODT handles data signalsLess than 1A of burst current Less than 1A of burst current2.5V Core and I/O 1.25V 1.2V Core andVoltage Level 1.8V Core and I/O 0.9V VTT 1.5V Core and I/O 0.75V VTTVTT I/O 0.6V VTT

The TPS51200 is designed as a Gm driven LDO. The voltage droop between the reference input and the outputregulator is determined by the transconductance and output current of the device. The typical Gm is 250 S at 2 Aand changes with respect to the load in order to conserve the quiescent current (that is, the Gm is very low at noload condition). The Gm LDO regulator is a single pole system. Its unity gain bandwidth for the voltage loop isonly determined by the output capacitance, as a result of the bandwidth nature of the Gm (see Equation 1 ) .

where

•F

UGBW

is the unity gain bandwidth•Gm is transconductance

•C

OUT

is the output capacitance

There are two limitations to this type of regulator when it comes to the output bulk capacitor requirement. In orderto maintain stablility, the zero location contributed by the ESR of the output capacitors should be greater than the-3-dB point of the current loop. This constraint means that higher ESR capacitors should not be used in thedesign. In addition, the impedance characteristics of the ceramic capacitor should be well understood in order toprevent the gain peaking effect around the Gm – 3-dB point because of the large ESL, the output capacitor andparasitic inductance of the VO trace.

Product Folder Link(s): TPS51200

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TPS51200

SLUS812 – FEBRUARY 2008

Figure 5. Bode Plot for a Typical DDR3 Configuration

Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where:

•V

= 3.3 V•V

VLDOIN

= 1.5 V•V

= 0.75 V•I

= 2 A•3×10- µF capacitors included•ESR = 2.5 m Ω

•ESL = 800 pH

The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52 °. The 0-dB level is crossed, thegain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.

Figure 6 shows the load regulation and Figure 7 shows the transient response for a typical DDR3 configuration.When the regulator is subjected to ± 1.5-A load step and release, the output voltage measurement shows nodifference between the dc and ac conditions.

Product Folder Link(s): TPS51200

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-3 -1-2 0 1 2 3

IOUT – Output Current – A

730

700

720

760

740

750

790

770

780

VOUT – Output Voltage – mV

85°C

VIN = 3.3 V

0°C

-40°C

25°C

710 0°C

25°C

85°C

DDR3

-40°C

LDO Design Guidelines

TPS51200

SLUS812 – FEBRUARY 2008

OUTPUT VOLTAGE

vsOUTPUT CURRENT

Figure 6. DC Regulaltion Figure 7. Transient

The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage Gm-drivento drive a certain load. For TPS51200, a minimum of 300 mV (VLDOIN

MIIN

– VO

MAX

) is needed in order tosupport a Gm driven sourcing current of 2 A based on a design of V

= 3.3 V and C

OUT

= 3 ×10 µF. Because theTPS51200 is essentially a Gm driven LDO, its impedance characteristics are both a function of the 1/Gm andR

DS(on)

of the sourcing MOSFET (see Figure 8 ). The current inflection point of the design is between 2 A and 3 A.When I

SRC

is less than the inflection point, the LDO is considered to be operating in the Gm region; when I

SRC

isgreater than the inflection point but less than the overcurrent limit point, the LDO is operating in the R

DS(on)region. The maximum sourcing R

DS(on)

is 0.144 Ωwith V

= 3.0 V and T

= 125 °C.

Product Folder Link(s): TPS51200

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ISRC - Source Current - A

Overcurrent

Limit

Inflection

Point

(between

2 A and 3 A)

UDG-08026

1/Gm

1/RDS(on)

VVO – Output Voltage – V

TPS51200

SLUS812 – FEBRUARY 2008

Figure 8. TPS51200 Impedance Characteristics

Product Folder Link(s): TPS51200

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THERMAL DESIGN

( )

DISS _ SRC VLDOIN VO O _ SRC

P V - V x I=

(2)

DISS _ SNK VO O _ SNK

P V I= ´

(3)

( )

J(max) A(max)

PKG

T T

(4)

Land Pad

3 mm x 1.9 mm

Exposed Thermal

Die Pad,

2.48 mm x 1.74 mm

UDG-08018

TPS51200

SLUS812 – FEBRUARY 2008

Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, therebydissipating power from the device. When the device is sourcing current, the voltage difference between VLDOINand VO times IO (I

) current becomes the power dissipation as shown in Equation 2 .

In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall powerloss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the powerdissipation, P

DISS_SNK

can be calculated by Equation 3 .

Because the device does not sink and source current at the same time and the IO current may vary rapidly withtime, the actual power dissipation should be the time average of the above dissipations over the thermalrelaxation duration of the system. Another source of power consumption is the current used for the internalcurrent control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or lessduring normal operatiing conditions. This power must be effectively dissipated from the package.

Maximum power dissipation allowed by the package is calculated by Equation 4 .P

PKG

= [T

J(MAX)

– T

A(MAX)

]/ θ

where

•T

J(MAX)

is +125 °C•T

A(MAX)

is the maximum ambient temperature in the system• θ

is the thermal resistance from junction to ambient

The thermal performance of an LDO is greatly depends on the printed circuit board (PCB) layout. The TPS51200is housed in a thermally-enhanced PowerPAD™ package that has an exposed die pad underneath the body. Forimproved thermal performance, this die pad must be attached to ground via thermal land on the PCB. Thisground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, θ

, 52.06 °C/W, isachieved based on a land pattern of 3 mm ×1.9 mm with four vias (0.33-mm via diameter, the standard thermalvia size) without air flow (see Figure 9 ).

Figure 9. Recommend Land Pad Pattern for TPS51200

To further improve the thermal performance of this device, using a larger than recommended thermal land aswell as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typicalthermal resistance from junction to thermal pad, θ

, is 10.24 °C/W (based on the recommend land pad and fourstandard thermal vias).

Product Folder Link(s): TPS51200

www.ti.com

LAYOUT CONSIDERATIONS

TPS51200

SLUS812 – FEBRUARY 2008

For further information regarding the PowerPAD™ package and the recommended board layout, refer to thePowerPAD™ package application note (SLMA002 ). This document is available at www.ti.com .

Consider the following points before starting the TPS51200 layout design.•The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wideconnections.

•The output capacitor for VO should be placed close to the pin with short and wide connection in order toavoid additional ESR and/or ESL trace inductance.•VOSNS should be connected to the positive node of VO output capacitor(s) as a separate trace from the highcurrent power line. This configuration is strongly recommended to avoid additional ESR and/or ESL. Ifsensing the voltage at the point of the load is required, it is recommended to attach the output capacitor(s) atthat point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between theGND pin and the output capacitor(s).•Consider adding low-pass filter at VOSNS if the ESR of the VO output capacitor(s) is larger than 2 m Ω.•REFIN can be connected separately from VLDOIN. Remember that this sensing potential is the referencevoltage of REFOUT. Avoid any noise-generating lines.•The negative node of the VO output capacitor(s) and the REFOUT capacitor should be tied together byavoiding common impedance to the high current path of the VO source/sink current.•The GND and PGND pins should be connected to the thermal land underneath the die pad with multiple viasconnecting to the internal system ground planes (for better result, use at least two internal ground planes).Use as many vias as possible to reduce the impedance between PGND/GND and the system ground plane.Also, place bulk caps close to the DIMM load point, route the VOSNS to the DIMM load sense point.•In order to effectively remove heat from the package, properly prepare the thermal land. Apply solder directlyto the package ’ s thermal pad. The wide traces of the component and the side copper connected to thethermal land pad help to dissipate heat. Numerous vias 0,33 mm in diameter connected from the thermal landto the internal/solder side ground plane(s) should also be used to help dissipation.•Please consult the TPS51200-EVM User's Guide (SLUUxxx) for detailed layout recommendations.

Product Folder Link(s): TPS51200

www.ti.com

TYPICAL CHARACTERISTICS

-3

1.18

-1-2 0 1 2 3

IOUT – Output Current – A

1.20

1.26

1.22

1.24

1.30

1.28

VOUT– Output Voltage – V

0°C

25°C

85°C

DDR

-40°C

0°C

25°C

-40°C

VIN = 3.3 V

85°C

890

870

880

920

900

910

940

930

-3 -1-2 0 1 2 3

IOUT – Output Current – A

25°C

85°C

VIN = 3.3 V

0°C

-40°C

0°C

25°C

85°C

DDR2

-40°C

VOUT – Output Voltage – mV

-3 -1-2 0 1 2 3

IOUT – Output Current – A

730

700

720

760

740

750

790

770

780

VOUT – Output Voltage – mV

85°C

VIN = 3.3 V

0°C

-40°C

25°C

710 0°C

25°C

85°C

DDR3

-40°C

590

550

570

630

610

670

650

VOUT – Output Voltage – mV

VIN = 3.3 V

85°C

-40°C

0°C

25°C

-3 -1-2 0 1 2 3

IOUT – Output Current – A

0°C

25°C

85°C

DDR3

-40°C

TPS51200

SLUS812 – FEBRUARY 2008

For Figure 10 through Figure 24 , 3 ×10- µF MLCCs (0805) are used on the output.

OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT

Figure 10. Figure 11.

OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT

Figure 12. Figure 13.

Product Folder Link(s): TPS51200

www.ti.com

1.00

0.90

0.95

1.15

1.05

1.10

1.30

1.20

1.25

VOUT– Output Voltage – V

VIN = 2.5 V

85°C -40°C

0°C

25°C

-3 -1-2 0 1 2 3

IOUT – Output Current – A

0°C

25°C

85°C

DDR

-40°C

-3 -1-2 0 1 2 3

IOUT – Output Current – A

0.80

0.70

0.75

0.90

0.85

0.95

VOUT – Output Voltage – V

1.00

0°C

25°C

85°C

DDR2

-40°C

VIN = 2.5 V

85°C

-40°C

25°C

0°C

-3

650

-1-2 0 1 2 3

IOUT – Output Current – A

750

700

800

VOUT– Output Voltage – V

0°C

85°C VIN = 2.5 V

25°C

-40°C

0°C

25°C

85°C

DDR3

-40°C

500

550

600

650

750

700

VOUT – Output Voltage – mV

-3 -1-2 0 1 2 3

IOUT – Output Current – A

0°C

25°C

85°C

LP DDR3

-40°C

VIN = 2.5 V

85°C

-40°C

25°C

0°C

TPS51200

SLUS812 – FEBRUARY 2008

TYPICAL CHARACTERISTICS (continued)For Figure 10 through Figure 24 , 3 ×10- µF MLCCs (0805) are used on the output.

OUTPUT VOLTAGE OUTPUT CURRENTvs vsOUTPUT CURRENT OUTPUT VOLTAGE

Figure 14. Figure 15.

OUTPUT VOLTAGE OUTPUT VOLTAGEvs vsOUTPUT CURRENT OUTPUT CURRENT

Figure 16. Figure 17.

Product Folder Link(s): TPS51200

www.ti.com

-15

1.249

1.247

-5-10 0 5 10 15

IREFOUT – Output Current – mA

1.248

1.252

1.250

1.251

1.255

1.253

1.254

VREFOUT – Output Voltage – V

-40°C

25°C

85°C

DDR

-40°C

25°C

85°C

-15 -5-10 0 5 10 15

IREFOUT – Output Current – mA

899

897

898

902

900

901

905

903

904

VREFOUT – Output Voltage – mV

-40°C

25°C

85°C

LP DDR3

-40°C

25°C

85°C

-15

599

598

-5

-40°C

25°C

85°C

-10 0 5 10 15

IREFOUT – Output Current – mA

598

602

600

601

605

603

604

VREFOUT – Output Voltage – mV

LP DDR3

-40°C

25°C

85°C

-40°C

25°C

85°C

-15

749

747

-5-10 0 5

IREFOUT – Output Current – mA

748

752

750

751

755

753

754

VREFOUT – Output Voltage – mV

-40°C

25°C

85°C

DDR3

TPS51200

SLUS812 – FEBRUARY 2008

TYPICAL CHARACTERISTICS (continued)For Figure 10 through Figure 24 , 3 ×10- µF MLCCs (0805) are used on the output.

REFOUT VOLTAGE REFOUT VOLTAGEvs vsREFOUT CURRENT REFOUT CURRENT

Figure 18. Figure 19.

REFOUT VOLTAGE REFOUT VOLTAGEvs vsREFOUT CURRENT REFOUT CURRENT

Figure 20. Figure 21.

Product Folder Link(s): TPS51200

www.ti.com

-10

-30

-20

-100

-200

-150

-50

200

100

150

Gain – dB

Phase – Degrees

Gain

Phase

Gain

Phase

DDR2

1 k 10 k 100 k 1 M 10 M

f – Frequency - Hz

0 1.00.5 2.0 2.5 3.0 3.5

IOUT – Output Current – A

0.6

0.4

1.2

0.8

1.0

1.8

1.4

1.6

VDRPOUT – Output Voltage – V

0.2

1.5

0.90 V

1.25 V

0.75

0.90

1.25

VOUT(V)

0.60

0.6 V

0.75 V

-10

-30

-20

-100

-200

-150

-50

200

100

150

Phase

Gain – dB

Gain

Phase

DDR3

1 k 10 k 100 k 1 M 10 M

f – Frequency - Hz

TPS51200

SLUS812 – FEBRUARY 2008

TYPICAL CHARACTERISTICS (continued)For Figure 10 through Figure 24 , 3 ×10- µF MLCCs (0805) are used on the output.

DROPOUT VOLTAGE GAIN AND PHASEvs vsOUTPUT CURRENT FREQUENCY

Figure 22. Figure 23.

GAIN AND PHASE

vsFREQUENCY

Figure 24.

Product Folder Link(s): TPS51200

www.ti.com

DESIGN EXAMPLES

Design Example 1

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.8 V

VVTT = 0.9 V

1000 pF

10 kW

VVDDQ = 1.8 V

10 kW

UDG-08028

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, DDR2 Configuration

Figure 25. 3.3-V

, DDR2 Configuration

Design Example 1 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k ΩResistorR3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 2

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.5 V

VVTT = 0.75 V

1000 pF

10 kW

VVDDQ = 1.5 V

10 kW

UDG-08029

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, DDR3 Configuration

Figure 26. 3.3-V

, DDR3 Configuration

Design Example 2 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k ΩResistorR3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 3

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

2.5 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.5 V

VVTT = 0.75 V

1000 pF

10 kW

VVDDQ = 1.5 V

10 kW

UDG-08030

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 2.5-V

, DDR3 Configuration

Figure 27. 2.5-V

, DDR3 Configuration

Design Example 3 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k ΩResistorR3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 4

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.2 V

VVTT = 0.6 V

1000 pF

10 kW

VVDDQ = 1.2 V

10 kW

UDG-08031

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, LP DDR3 Configuration

Figure 28. 3.3-V

, LP DDR3 Configuration

Design Example 4 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k ΩResistorR3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 5

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.5 V

VVTT = 0.75 V

1000 pF

10 kW

VVDDQ = 1.5 V

10 kW

UDG-08032

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, DDR3 Tracking Configuration

Figure 29. 3.3-V

, DDR3 Tracking Configuration

Design Example 5 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k ΩResistorR3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 6

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

ENABLE

0.1 mF

REFOUT

VVLDOIN = VVLDOREF = 2.5 V

VVLDO = 1.8 V

1000 pF

10 kW

2.5 V

3.86 kW

UDG-08033

4.7 mF

10 mF

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, LDO Configuration.

Figure 30. 3.3-V

, LDO Configuration

Design Example 6 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1 10 k Ω

R2 Resistor 3.86 k Ω

R3 100 k Ω

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 Capacitor 0.1 µFC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L Murata

Product Folder Link(s): TPS51200

www.ti.com

Design Example 7

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

100 kW

3.3 VIN

PGOOD

SLP_S3

0.1 mF

VTTREF

VVLDOIN = VVDDQ = 1.5 V

VVTT = 0.75 V

1000 pF

10 kW

VVDDQ = 1.5 V

10 kW

UDG-08034

4.7 mF

10 mF

R4(1)

C9(1)

TPS51200

SLUS812 – FEBRUARY 2008

This design example describes a 3.3-V

, DDR3 Configuration with LFP.

Figure 31. 3.3-V

, DDR3 Configuration with LFP

Design Example 7 List of Materials

REFERENCE

DESCRIPTION SPECIFICATION PART NUMBER MANUFACTURERDESIGNATOR

R1, R2 10 k Ω

R3 Resistor 100 k Ω

(1)

C1, C2, C3 10 µF, 6.3 V GRM21BR70J106KE76L MurataC4 1000 pFC5 0.1 µFCapacitorC6 4.7 µF, 6.3 V GRM21BR60J475KA11L MurataC7, C8 10 µF, 6.3 V GRM21BR70J106KE76L MurataC9

(1)

(1) The values of R4 and C9 should be chosen to reduce the parasitic effect of the trace (between VO and the output MLCCs) and theoutput capacitors (ESR and ESL).

Product Folder Link(s): TPS51200

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TPS51200DRCR ACTIVE SON DRC 10 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS51200DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS51200DRCT ACTIVE SON DRC 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS51200DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS51200 :

•Automotive: TPS51200-Q1

NOTE: Qualified Version Definitions:

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

PACKAGE OPTION ADDENDUM

www.ti.com 24-Mar-2010

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS51200DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS51200DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS51200DRCR SON DRC 10 3000 367.0 367.0 35.0

TPS51200DRCT SON DRC 10 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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