SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DUndershoot Protection for Off-Isolation on
A and B Ports Up To −2 V
DBidirectional Data Flow, With Near-Zero
Propagation Delay
DLow ON-State Resistance (ron)
Characteristics (ron = 3 Ω Typical)
DLow Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5 pF Typical)
DData and Control Inputs Provide
Undershoot Clamp Diodes
DLow Power Consumption
(ICC = 3 µA Max)
DVCC Operating Range From 4 V to 5.5 V
DData I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
DControl Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
DSupports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
VCC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
description/ordering information
The SN74CBT3384C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT3384C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT3384C is organized as two 5-bit bus switches with separate output-enable (1OE, 2OE) inputs.
It can be used as two 5-bit bus switches or as one 10-bit bus switch. When OE is low, the associated 5-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 5-bit bus switch is OFF, and the high-impedance state exists between the A and B
ports.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$ % &'!!($ #% )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
SOIC − DW
Tube SN74CBT3384CDW
CBT3384C
SOIC − DW Tape and reel SN74CBT3384CDWR CBT3384C
SSOP − DB
Tube SN74CBT3384CDB
CBT3384C
−40°C to 85°C
SSOP − DB Tape and reel SN74CBT3384CDBR CBT3384C
−40
°
C to 85
°
C
SSOP (QSOP) − DBQ Tape and reel SN74CBT3384CDBQR CBT3384C
TSSOP − PW
Tube SN74CBT3384CPW
CU384C
TSSOP − PW Tape and reel SN74CBT3384CPWR CU384C
TVSOP − DGV Tape and reel SN74CBT3384CDGVR CU384C
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 5-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L B A port = B port
H Z Disconnect
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1A1 SW 1B1
1A5
1OE
SW 1B5
2A1 SW 2B1
2A5
2OE
SW 2B5
3
11
1
14
22
13
2
10
15
23
simplified schematic, each FET switch (SW)
A
EN†
B
†EN is the internal enable signal applied to the switch.
Undershoot
Protection Circuit
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, VIN (see Notes 1 and 2) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, IIK (VIN < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, II/OK (VI/O < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, II/O (see Note 4) ±128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND terminals ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 5): DB package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for VI/O.
4. II and IO are used to denote specific conditions for II/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN MAX UNIT
VCC Supply voltage 4 5.5 V
VIH High-level control input voltage 2 5.5 V
VIL Low-level control input voltage 0 0.8 V
VI/O Data input/output voltage 0 5.5 V
TAOperating free-air temperature −40 85 °C
NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Control inputs VCC = 4.5 V, IIN = −18 mA −1.8 V
VIKU Data inputs VCC = 5 V, 0 mA > II ≥ −50 mA,
VIN = VCC or GND, Switch OFF −2 V
IIN Control inputs VCC = 5.5 V, VIN = VCC or GND ±1µA
IOZ‡VCC = 5.5 V, VO = 0 to 5.5 V,
VI = 0, Switch OFF,
VIN = VCC or GND ±10 µA
Ioff VCC = 0, VO = 0 to 5.5 V, VI = 0 10 µA
ICC VCC = 5.5 V, II/O = 0,
VIN = VCC or GND, Switch ON or OFF 3µA
∆ICC§Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA
Cin Control inputs VIN = 3 V or 0 3.5 pF
Cio(OFF) VI/O = 3 V or 0, Switch OFF, VIN = VCC or GND 5 pF
Cio(ON) VI/O = 3 V or 0, Switch ON, VIN = VCC or GND 12.5 pF
VCC = 4 V,
TYP at VCC = 4 V VI = 2.4 V, IO = −15 mA 8 12
r
on
¶
VI = 0
IO = 64 mA 3 6 Ω
ron¶
V
CC
= 4.5 V VI = 0 IO = 30 mA 3 6
Ω
VCC = 4.5 V
VI = 2.4 V, IO = −15 mA 5 10
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
†All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡For I/O ports, the parameter IOZ includes the input leakage current.
§This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
¶Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX
UNIT
tpd#A or B B or A 0.24 0.15 ns
ten OE A or B 5 1.5 4.2 ns
tdis OE A or B 5 1.5 4.5 ns
#The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,
when driven by an ideal voltage source (zero output impedance).
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
undershoot characteristics (see Figures 1 and 2)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOUTU VCC = 5.5 V, Switch OFF, VIN = VCC or GND 2 VOH−0.3 V
†All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
Figure 1. Device Test Setup
50 Ω
VS
VCC 11 V
100 kΩ
100 kΩ10 pF
DUT
Input
Generator Ax Bx
Figure 2. Transient Input Voltage (VI) and Output
Voltage (VOUTU) Waveforms
(Switch OFF)
−2 V
5.5 V
10 %
20 ns
10 %
90 % 90 %
2 ns 2 ns
VOH − 0.3
VOH
Output
(VOUTU)
Input
(Open
Socket)
SCDS132A − SEPTEMBER 2003 − REVISED OCT OBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
CL
(see Note A)
TEST CIRCUIT
S1 7 V
Open
GND
RL
RL
tPLH tPHL
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + V∆
VOH − V∆
0 V
Output
Control
(VIN)
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns
.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state
resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
50 Ω
VG1
V
CC
DUT
50 Ω
VIN
50 Ω
VG2 50 Ω
VI
TEST RL
S1 V∆
CL
5 V ±0.5 V
4 V
VCC VI
tPHZ/tPZH
tPLZ/tPZL
tpd(s)
5 V ±0.5 V
4 V
5 V ±0.5 V
4 V
Open
Open
7 V
7 V
Open
Open
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
VCC or GND
VCC or GND
GND
GND
VCC
VCC
50 pF
50 pF
50 pF
50 pF
50 pF
50 pF
0.3 V
0.3 V
0.3 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator VO
Figure 3. Test Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
SN74CBT3384CDBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CBT3384C
SN74CBT3384CDBQRE4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CBT3384C
SN74CBT3384CDBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CBT3384C
SN74CBT3384CDGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CDGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CDGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CDW ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CDWE4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CDWG4 ACTIVE SOIC DW 24 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CDWR ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CDWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CDWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBT3384C
SN74CBT3384CPW ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CPWE4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CPWG4 ACTIVE TSSOP PW 24 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CPWR ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
SN74CBT3384CPWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
SN74CBT3384CPWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CU384C
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CBT3384CDBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74CBT3384CDGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74CBT3384CDWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
SN74CBT3384CPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CBT3384CDBQR SSOP DBQ 24 2500 367.0 367.0 38.0
SN74CBT3384CDGVR TVSOP DGV 24 2000 367.0 367.0 35.0
SN74CBT3384CDWR SOIC DW 24 2000 367.0 367.0 45.0
SN74CBT3384CPWR TSSOP PW 24 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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