K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 1 - July 2004
Document Title
1Mx4 Bit High Speed Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev No.
Rev. 0.0
Rev. 0.1
Rev. 1.0
Rev. 0.3
Rev. 1.0
Rev. 2.0
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
History
Initial release with Preliminary.
Add Low Ver.
Change Icc, Isb and Isb1
1. Correct AC parameters : Read & Write Cycle mA
2. Delete Low Ver.
3. Delete Data Retention Characteristics
1. Delete 12ns,15ns speed bin.
2. Change Icc for Industrial mode.
1. Add the Lead Free Package type.
Item Previous Current
ICC(Commercial)
8ns 110mA 80mA
10ns 90mA 65mA
12ns 80mA 55mA
15ns 70mA 45mA
ICC(Industrial)
8ns 130mA 100mA
10ns 115mA 85mA
12ns 100mA 75mA
15ns 85mA 65mA
ISB 30mA 20mA
ISB1(L-ver.) 0.5mA 1.2mA
Item Previous Current
ICC(Industrial) 8ns 100mA 90mA
10ns 85mA 75mA
Draft Data
Aug. 20. 2001
Sep. 19. 2001
Nov. 3. 2001
Nov.23. 2001
Dec.18. 2001
July. 26, 2004
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 2 - July 2004
4Mb Async. Fast SRAM Ordering Information
Org. Part Number VDD(V) Speed ( ns ) PKG Temp. & Power
1M x4
K6R4004C1D-J(K)C(I) 10 5 10 J : 32-SOJ
K : 32-SOJ(LF) C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
L : Commercial Temperature
,Low Power Range
P : Industrial Temperature
,Low Power Range
K6R4004V1D-J(K)C(I) 08/10 3.3 8/10
512K x8
K6R4008C1D-J(K,T,U)C(I) 10 5 10 J : 36-SOJ
K : 36-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
K6R4008V1D-J(K,T,U)C(I) 08/10 3.3 8/10
256K x16
K6R4016C1D-J(K,T,U,E)C(I) 10 5 10 J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10 3.3 8/10
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 3 - July 2004
1M x 4 Bit (with OE)High-Speed CMOS Static RAM
GENERAL DESCRIPTION
FEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
Standby (TTL) :20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4004V1D-08: 80mA(Max.)
K6R4004V1D-10: 65mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004V1D-J: 32-SOJ-400
K6R4004V1D-K: 32-SOJ-400(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
PIN FUNCTION
Pin Name Pin Function
A0 - A19 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O4Data Inputs/Outputs
VCC Power(+3.3V)
VSS Ground
N.C No Connection
The K6R4004V1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004V1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004V1D is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A18
A17
A16
A15
OE
I/O4
Vss
Vcc
I/O3
A14
A13
A12
A11
A10
N.C
A0
A1
A2
A3
A4
CS
I/O1
Vcc
Vss
I/O2
WE
A5
A6
A7
A8
A9
Clk Gen.
I/O1~I/O4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont. Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
1024 Rows
1024 x 4 Columns
I/O Circuit
A10 A12 A14 A16 A18
A11 A13 A15 A17 A19
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 4 - July 2004
CAPACITANCE*(TA=25°C, f=1.0MHz)
* Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions TYP Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN VIN=0V - 6 pF
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 4.6 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 4.6 V
Power Dissipation PD1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA0 to 70 °C
Industrial TA-40 to 85 °C
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 000V
Input High Voltage VIH 2.0 - VCC+0.3** V
Input Low Voltage VIL -0.3* - 0.8 V
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN=VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2 2 µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
Com. 8ns - 80 mA
10ns - 65
Ind. 8ns - 90
10ns - 75
Standby Current ISB Min. Cycle, CS=VIH -20mA
ISB1 f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-5
Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 5 - July 2004
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
Output Loads(B)
DOUT
5pF*
319Ω
353Ω
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
DOUT RL = 50Ω
ZO = 50Ω
VL = 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R4004V1D-08 K6R4004V1D-10 Unit
Min Max Min Max
Read Cycle Time tRC 8-10-ns
Address Access Time tAA -8-10ns
Chip Select to Output tCO -8-10ns
Output Enable to Valid Output tOE -4-5ns
Chip Enable to Low-Z Output tLZ 3-3-ns
Output Enable to Low-Z Output tOLZ 0-0-ns
Chip Disable to High-Z Output tHZ 0405ns
Output Disable to High-Z Output tOHZ 0405
ns
Output Hold from Address Change tOH 3-3-
ns
Chip Selection to Power Up Time tPU 0-0-
ns
Chip Selection to Power DownTime tPD -8-10ns
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 6 - July 2004
Address
Data Out Previous Valid Data Valid Data
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
WRITE CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter Symbol K6R4004V1D-08 K6R4004V1D-10 Unit
Min Max Min Max
Write Cycle Time tWC 8-10-
ns
Chip Select to End of Write tCW 6-7-
ns
Address Set-up Time tAS 0-0-
ns
Address Valid to End of Write tAW 6-7-
ns
Write Pulse Width(OE High) tWP 6-7-
ns
Write Pulse Width(OE Low) tWP1 8-10-ns
Write Recovery Time tWR 0-0-
ns
Write to Output High-Z tWHZ 0405
ns
Data to Write Time Overlap tDW 4-5-
ns
Data Hold from Write Time tDH 0-0-ns
End of Write to Output Low-Z tOW 3-3-ns
Valid Data
High-Z
tRC
CS
Address
OE
Data out
tHZ(3,4,5)
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tOHZ
tPU tPD
50%
50%
VCC
Current
ICC
ISB
tDH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 7 - July 2004
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
CS
tWP(2)
tDW tDH
Valid Data
WE
Data in
Data out
tWC
tWR(5)
tAW
tCW(3)
High-Z(8)
High-Z
OE
tOHZ(6)
tAS(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
tWP1(2)
tDW tDH
tOW
tWHZ(6)
Valid Data
WE
Data in
Data out
tWC
tAS(4)
tWR(5)
tAW
tCW(3)
(10) (9)
High-Z(8)
High-Z
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
tAW
tDW tDH
Valid Data
WE
Data in
Data out High-Z High-Z(8)
tCW(3)
tWP(2)
tAS(4)
tWC
tWR(5)
High-Z
High-Z
tLZ tWHZ(6)
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 8 - July 2004
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
* X means Don′t Care.
CS WE OE Mode I/O Pin Supply Current
H X X* Not Select High-Z ISB, ISB1
L H H Output Disable High-Z ICC
L H L Read DOUT ICC
LLX Write DIN ICC
K6R4004V1D CMOS SRAM
PRELIMINARY
Rev 2.0
- 9 - July 2004
PACKAGE DIMENSIONS Units:millimeters/Inches
#1
32-SOJ-400
#32
20.95 ±0.12
0.825 ±0.005
10.16
0.400
+0.10
MAX
21.36
0.841
0.20 -0.05
+0.004
0.008 -0.002
9.40 ±0.25
0.370 ±0.010
MAX
0.148
3.76
MIN
0.69
0.027
1.30
( )
0.051
1.30
( )
0.051
0.95
( )
0.0375
+0.10
0.43 -0.05
+0.004
0.017 -0.002
+0.10
0.71 -0.05
+0.004
0.028 -0.002
1.27
0.050
#16
#17
0.004
0.10 MAX
11.18 ±0.12
0.440 ±0.005
