Publication Date : August 2018
1
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
OUTLINE
MAIN FUNCTION AND RATINGS
3 phase DC/AC i nverter
600V / 30A (CSTBT)
N-side IGBT open emitter
Built-in b oot st ra p dio des w ith curren t limiting resistor
APPLICATION
AC 100~240Vrms(DC voltage:400V or below) class
low pow er motor contr ol
TYPE NAME
PSS30S71F6
With t emperat ur e output function
INT EGRATED DRIVE, PROTECTION AND SY STEM CONTROL FUNCTIO NS
● For P-side : Dr i ve circuit, High voltage high-speed lev el s hifting, Control supply under-voltage (UV) protection
● For N-side : Drive circui t, Co ntrol su pply u nder-voltage protect ion (UV), Short circuit protec tion (SC),
● Fault signaling : Corresponding to S C faul t (N-sid e IGBT) , UV fault (N-side suppl y)
● Temperature output : Outputting LVIC temperature by analog signal
● Input interface : 3, 5V line, Schmitt trigger receiver circ uit (Hig h Ac tive)
● UL Recognized : UL1557 File E80276
INTERNAL CIRCUIT
V
UFS
(1)
V
VFS
(7)
V
WFS
(13)
W(34)
P
W
P
(18)
U
P
(6)
V
P1
(4)
U
N
(21)
V
N
(22)
W
N
(23)
F
O
(24)
V
N1
(28)
V
NC
(27)
NW(31)
CIN(26)
NU(33)
NV(32)
V(35)
U(36)
P(37)
V
OT
(20)
V
UFB
(3)
V
VFB
(9)
V
WFB
(15)
V
P1
(10)
V
P1
(16)
CFO(25)
DIPIPM
HVIC1
HVIC2
HVIC3
HO
HO
HO
WOUT
VOUT
UOUT
IGBT1
Di1
IGBT2
Di2
IGBT3
Di3
IGBT4
Di4
IGBT5
Di5
IGBT6
Di6
LVIC
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
2
MAXIMUM RATINGS
(Tj = 25°C, unless otherwise noted)
INVE RTER PART
Symbol
Parameter
Condition
Ratings
Unit
VCC
Sup pl y vol tag e
Applied between P-NU,NV,NW
450
V
VCC(surge)
Sup pl y vol tag e (s urg e)
Applied between P-NU,NV,NW
500
V
V
CES
Collector-emi t t er volt ag e
600
V
±I
C
Each IGBT collector current
T
C
= 25°C
(Note 1)
30
A
±I
CP
Each IGBT collector current (peak)
T
C
= 25°C, less than 1ms
60
A
P
C
Colle c tor di s s ipation
T
C
= 25°C, per 1 chip
90.9
W
Tj
Junc t i on t emp erature
-20~+150
°C
Note1: Pulse width and period are limited due to junction temperature.
CONTROL (PROTECTION) PART
Symbol
Parameter
Condition
Ratings
Unit
VD Control supply voltage Applied b etw een
V
P1-VNC, VN1-VNC 20 V
VDB
Control supply voltage
App li ed b etw een
VUFB-VUFS, V VFB-VVFS ,VWFB-VWFS
20
V
VIN
Inp ut v olt age
App li ed b etw een
UP, VP, WP-VPC, UN, VN, WN-VNC
-0.5~VD+0.5
V
V
FO
Fault output supply voltage
App li ed b etw een
F
O
-V
NC
-0.5~V
D
+0.5
V
I
FO
Fault output current
Sink current at F
O
terminal
1
mA
V
SC
Current sensing input voltage
Applied between CIN-V
NC
-0.5~V
D
+0.5
V
TOTAL SYSTEM
Symbol
Parameter
Condition
Ratings
Unit
VCC(PROT)
Self protection supply voltage limit
(Short circuit pro tection capability)
V
D
= 13.5~16.5V, In verter Par t
Tj = 125°C, n on-repetitive, less than 2μs
400 V
T
C
Modul e c ase operat i on t em per at ure
Measurement point of Tc is provided in Fig.1
-20~+100
°C
Tstg
St orag e temp erature
-40~+125
°C
Viso Isol ati on v oltage
60Hz, Sinusoidal, AC 1min, between connected all pins
and heat sink plate
2500 Vrms
Fig. 1: TC MEASUREMENT POINT
THERM AL RESI STANCE
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Rth(j-c)Q
Junction to case thermal
resistance (Note 2)
In vert er IG BT part ( p er 1/ 6 m odu l e)
-
-
1.1
K/W
Rth(j-c)F
Inverter FWDi part (per 1/6 module)
-
-
2.8
K/W
Note 2: G rease wi th good thermal conducti vit y and lon g-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of
DIPIPM and h eat s i nk. T he contac ti ng therm al resistanc e between DIPIP M ca se and heat s i nk Rth(c-f) is deter m ined by the thi cknes s and the t her m al
conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k).
Control terminals
Tc point
IGBT chip position
FWDi chip position
Power terminals
Heat sink s ide
Groove
17.7mm
18mm
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
3
ELECTRICAL CHARACTERIS TICS
(Tj = 25°C, unless otherwise noted)
INVE RTER PART
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
VCE(sat) Collector-emitter saturation
voltage VD=VDB = 15V, VIN= 5V
I
C
= 30A , T
j
= 25°C
-
1.40
1.90
V
IC= 30A , Tj= 125°C
-
1.50
2.00
VEC
FWDi forward voltage
VIN= 0V, -IC= 30A
-
1.50
2.00
V
t
on
Switching times VCC= 300V, VD= VDB= 15V
IC= 30A, Tj= 125°C, VIN= 0↔5V
Ind uc ti ve L oad (upper-low er arm)
0.95
1.55
2.15
μs
t
C(on)
-
0.50
0.80
μs
t
off
-
1.75
2.35
μs
tC(off) - 0.40 0.60 μs
trr
-
0.30
-
μs
ICES Collector-emitter cut-off
current VCE=VCES
Tj= 25°C
-
-
1
mA
T
j
= 125°C
-
-
10
CONTROL (PROTECTION) PART
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
ID Circuit current Total of VP1-VNC, VN1-VNC
VD=15V, VIN=0V
-
-
6.00
mA
V
D
=15V, V
IN
=5V
-
-
6.00
IDB Each part of VUFB- VUFS,
VVFB- VVFS, VWFB- VWFS
V
D
=V
DB
=15V, V
IN
=0V
-
-
0.55
V
D
=V
DB
=15V, V
IN
=5V
-
-
0.55
VSC(ref) Short circ uit trip level VD = 15V (Note 3) 0.45 0.48 0.51 V
UVDBt
P-side Control supply
under-voltage protection(UV) Tj ≤125°C
Trip level
10.0
-
12.0
V
UVDBr
Reset le v el
10.5
-
12.5
V
UV
Dt
N-side Control supply
under-voltage protection(UV)
Trip level
10.3
-
12.5
V
UV
Dr
Reset le v el
10.8
-
13.0
V
V
OT
Temperature Output
Pull down R=5kΩ
(Note 4)
L VIC T emperature=85
°
C
2.51
2.64
2.76
V
VFOH Fault output voltage VSC = 0V, FO t er mi nal pulled up to 5V by 10kΩ 4.9 - - V
VFOL
VSC = 1V, IFO = 1mA
-
-
0.95
V
tFO
F ault ou tput pu lse width
CFO=22nF
(Note 5)
1.6
2.4
-
ms
I
IN
Input current
V
IN
= 5V
0.70
1.00
1.50
mA
V
th(on)
ON threshold voltage
Applied between UP, VP, WP, UN, VN, WN-VNC
-
2.10
2.60
V
Vth(off)
OFF threshold voltage
0.80
1.30
-
Vth(hys)
ON/OFF threshold
hysteresis vol tage
0.35 0.80 -
V
F
B ootstrap D i for war d volt age
I
F
=10mA including volt ag e drop by limit ing resistor
(Note 6)
0.5
0.9
1.3
V
R
Built-in limiting resistance
Inc lu d ed in b oot s tr ap D i
16
20
24
Ω
Note 3 : SC protection works only for N-side IGBT. Please select the external shunt resistance such that the SC trip-level is less than 2.0 times of the current rating.
4 : DIPIPM don't shutdown IGBTs and output fault signal automatically when temperature rises excessively. When temperature exceeds the protective level that
user defined, controller (MCU) should stop the DIPIPM. Temperature of LVIC vs. VOT output characteristics is described in Fig. 3.
5 : Faul t s ignal Fo outputs when SC or UV protecti on wor ks. Fo pul s e wi dth is different for each pr otec tion m odes . At SC fail ur e, Fo pul se wi dth is a fixed width
whic h i s s pec ified b y the capac i tor c onnected to CFO ter m inal . ( CFO=9.1 x 10-6 x t FO [F]), but at UV fai l ure, F o o utputs c onti nuo usl y until r eco vering from U V
state. (But minimum Fo pulse width is the specified time by CFO.)
6 : The characteristics of bootstrap Di is described in Fig.2.
Fig. 2 Characterist ics of bootstrap Di VF-IF curve (@Ta=25°C) inc l uding volt age drop by limiting resistor (Right ch ar t is enl ar g ed ch ar t.)
0
100
200
300
400
500
600
700
800
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I
F
[mA]
V
F
[V]
0
5
10
15
20
25
30
35
40
45
50
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
I
F
[mA]
V
F
[V]
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
4
Fig. 3 Temperature o f LVIC vs. VOT output characteristics
2.51
2.64
2.76
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
55 65 75 85 95 105 115
VOT output (V)_
LVIC temperature (°C)
Typ.
Max.
Min.
Fig. 4 VOT output circuit
(1) It is recommended to insert 5kΩ (5.1kΩ is recommended) pull down resistor for getting linear output characteristics at low temp eratu r e
below room temperature. When the pull down resistor is inserted between VOT and VNC(control GND), the extra circuit current, which is
calculated approximately by VOT output volt ag e divided by pull down resistance, flows a s LVIC circuit current continuously. In the case of
using VOT for detecting high temperature over room temperature only, it is unnecessary to insert the pull down resistor.
(2) In the case of using VOT with low voltage controller like 3.3V MCU, VOT output might exceed control supply voltage 3.3V when
t emper atur e ris es exc essi vely. If syst em us es l ow volt age c ontr oll er, it is rec omm ended to ins ert a cl amp Di bet ween c ont r ol s up ply of
the controller and VOT outp ut f or pr ev enting ov er vol t age destruction.
(3) In the case of not using VOT, leave VOT output NC (No Connection).
Refer the application note for this product about th e usage of VOT.
Ref
V
OT
Temperature
Signal
V
NC
Inside LVIC
of DIPIPM
MCU
5kΩ
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
5
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Condition
Limits
Unit
Min.
Typ.
Max.
Mounting tor qu e
Mounting screw : M3
(Note 7)
Recommended 0.78N·m
0.59
-
0.98
N·m
Terminal pulling strength Load 9.8N JEITA-ED-4701 10 - - s
Terminal bending strength
Load 4.9N, 90deg. bend
JEITA-ED-4701
2
-
-
times
Weight - 21 - g
Heat-sink flatness (Note 8) -50 - 100 μm
Note 7: Plain washers (ISO 7089~7094) are recommended.
Note 8: Measurement point of heat sink flatness
RECOMMENDED OPERATION CONDITIONS
Symbol Parameter Condition
Limits
Unit
Min.
Typ.
Max.
V
CC
Sup pl y vol tag e
Applied between P-NU, NV, N W
0
300
400
V
VD Control supply voltage Applied between VP1-VNC, VN1-VNC 13.5 15.0 16.5 V
VDB Control supply voltage A pp li ed betw een VUFB-VUFS, VVFB-VVFS, VWFB-VWFS 13.0 15.0 18.5 V
ΔVD, ΔVDB
Control supply variation
-1
-
+1
V/μs
t
dead
Arm shoot-through blocking time
For each input signal
1.5
-
-
μs
f
PWM
PWM input frequency
T
C
≤ 100°C, T
j
≤ 125°C
-
-
20
kHz
IO Allowable r.m.s. current
V
CC
= 300V, V
D
= 15V, P.F = 0.8,
Sinusoidal PWM
TC ≤ 100°C, Tj ≤ 125°C (Note9)
fPWM= 5kHz - - 21.0 Arms
fPWM= 15kHz - - 16.0
PWIN(on)
Minimum input pulse width
(Note 10)
0.7
-
-
μs
PWIN(off)
200V≤V
CC
≤350V,
13.5V≤VD≤16.5V,
13.0V≤VDB≤18.5V,
-20°C≤Tc≤100°C,
N-line wi ring induc tance
less than 10nH (Note 11)
Below rated current
1.5
-
-
Between rated current
and 1.7 times of rated
current
3.0 - -
Between 1.7 t imes and
2.0 times of rated current
3.6 - -
V
NC
V
NC
variation
Between V
NC
-NU, NV , NW (including surge)
-5.0
-
+5.0
V
T
j
Juncti on t emp eratu r e
-20
-
+125
°C
Note 9: A llowable r.m.s. current depends on the actual application conditions.
10: DIPIPM might not make response if the input signal pulse width is less than PWIN(on)
11: IPM might make delayed response or no response for the input signal with off pulse width less than PWIN(off). Please refer below about delayed response.
Delayed Response against Shorte r Input Off Signal than PWIN(off) (P-side only)
4.65mm
+
+
-
Meas urement positi on
Heat sink s ide
Heat sink s ide
12.78mm
13.5mm
23mm
-
P Side Control Input
Internal IGBT Gate
Output Current Ic
t1
t2
Real line: off pulse width > PWIN(off); turn on time t1
Br ok en line: off pulse widt h
< PWIN(off); turn on time t2
(t1:Normal switching time)
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
6
Fig. 5 Timin g C harts of The DIPIPM Prot ective Functions
[A] Short-C i rc uit Protec t io n (N-side only with the ext ernal shunt resistor and RC filter)
a1. Normal operation: IGBT ON and outputs current.
a2. Short circuit current detection (SC trigger)
(It is recommended to set RC time constant 1.5~2.0μs so that IGBT shut down within 2.0μs wh en SC .)
a3. All N-side IGBT's gates are hard interrupted.
a4. All N-side IGBTs turn OFF.
a5. FO outputs. T he pulse widt h of the Fo si g n al is s et by th e ext er nal c apac i t or CFO.
a6. Input = “L”: IGBT OFF
a7. Fo finishes out put, but IGBTs don't tur n on until inputting nex t ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
a8. Normal operation: IGBT ON and outputs current.
[B] Under -Vol t age Protec t io n (N-side, UVD)
b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but IGBT turns ON by next ON signal (LH).
(IGBT of each phase can return to normal state by inputting ON signal to each phase.)
b2. Normal operation: IGBT ON and outputs current.
b3. VD level drops to und er vol t ag e trip level. (UVDt).
b4. All N-side IGBTs turn OFF in spite of control input condition.
b5. F o out puts for the period set by the capacitance CFO, bu t output is ext end ed during VD keeps below UVDr.
b6. VD l ev el r eac hes UVDr.
b7. N ormal op erati on: IGB T ON an d output s current.
Lower-side control
input
Protection circuit state
Internal IGBT gate
Output current Ic
S ens e volt ag e of
the
shunt resistor
Error output Fo
SC
trip current level
a2
SET
RESET
SC
reference voltage
a1
a3
a6
a7
a4
a8
a5
D
elay by RC filtering
UVDr
RESET
SET
RESET
UV
Dt
b1
b2
b3
b4
b6
b7
b5
Control input
Protection circuit state
Control supply voltage V
D
Output current Ic
Error output Fo
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
7
[C] Un der -Vol t age Protection (P-side, UVDB)
c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, IGBT turns on by next ON signal (LH).
c2. Normal operation: IGBT ON and outputs current.
c3. VDB l ev el drops to und er vol tag e trip level (U VDBt).
c4. IGBT of the corres pon d phas e only turns OFF in spite of control input signal level, but there is no FO sig n al output .
c5. VDB l ev el r eac hes UVDBr.
c6. Normal operation: IGBT ON and outputs current.
Control input
Protection circuit state
Control supply voltage V
DB
Output current Ic
Error output Fo
UV
DBr
RESET
SET
RESET
UV
DBt
Keep High-level (no fault output)
c1
c2
c3
c4
c5
c6
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
8
Fig. 6 Example of Application Circuit
(1) If control GND is connected with power GND b y common broad p attern, it may cause mal func ti on by power G ND fluctuation.
It is rec ommen ded to c onnect control GND and power GND at on ly a point N1 ( near the ter minal of shunt resistor).
(2) It is recommen ded to insert a Zener diode D1(24V/1W) between each p air of cont rol supply termi nals to prev ent surge dest ruct ion.
(3) To prevent surge dest ruction, the wirin g between the smoothing capacitor an d the P, N1 ter minal s should be as short as p ossib le.
G ener al ly a 0.1-0.22μF s n ubb er c ap ac it or C3 b etw een the P-N1 termi nals is recom men ded.
(4) R1, C 4 of RC f ilter for preventin g protecti on cir cuit malfuncti on is recommended to select tig ht tolerance, temp-com pensated type.
The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is recommended generally.) SC
interrupting tim e might vary with th e wiring pattern, so th e enough ev aluation on the r eal sys tem is necessary.
(5) T o prev ent m alf unc t ion, th e wir ing of A, B, C shou l d be as s h ort a s poss ib le.
(6) The point D at which the wiring to CIN filter is divided s hould b e near t he terminal of shunt resistor. NU, NV, NW terminals should be
connected at near NU, NV, NW terminals when it is us ed by one shunt operation. Low in duc tanc e S MD t ype wit h tig ht t oler anc e,
temp-compensated type is recom mended for shun t resi stor.
(7) A l l ca paci tors s ho u ld b e mo un te d as cl ose to the termi n a l s as po ss i b le. (C1 : g ood t em p erature, frequ enc y characteristic electrolytic
type and C2: 0.22μ-2μF, good temperature, f requency and DC bias characterist ic ceramic t ype are recommended.)
(8) Input logic is Hi gh-active. T here is a 3.3kΩ(min.) pull-d ow n res is t or in th e inp ut cir c uit of I C. T o pr ev ent m alf u nc ti on, th e input wiring
should be as short as possible. When using RC coupling, make the input signal level meet the turn-on and turn-off threshold voltage.
(9) Fo ou tp ut is op en drain type. It should be pulled up to p ow er su pp ly of M CU (e.g. 5V,3.3V ) by a re si s tor th a t ma kes I Fo up t o 1m A.
(IFO is estim a t e d roug hly b y the formula of cont rol power s upply voltage divided by pull-u p r es istance. In th e c as e of pu ll ed up t o 5V,
10kΩ (5kΩ or more) is recom mended. ) When usi ng opto c oupl er, F o also can be pulled up to 15V (control supply of DIPIPM ) by the
resistor.
(10) Fo p ulse wi dth can be set by th e capacitor connected to CFO terminal. CFO(F) = 9.1 x 10-6 x tFO (R eq u ir ed Fo pu ls e wi dth) .
(11) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous
operat ion. To avoid such prob lem, li ne ripple voltage s houl d meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p.
(12) For DIPIP M, it isn' t recomm ended to dr iv e s am e lo ad b y p ar all el con n ect i on w ith ot her ph ase IG BT or oth er D IP IPM.
Long GN D wir ing h er e mi ght
generate noise to input signal and
cause IGBT malfunction.
Long wiring here might cause SC
level fluctuati on and m alfunc t i on .
Power GND wiring
Control GND wiring
M
MCU
C2
15V
VD
C4
R1
Shunt
resistor
N1
B
C
5V
A
+
U
N
(21)
V
N
(22)
W
N
(23)
Fo(24)
V
N1
(28)
V
NC
(27)
P
U
W
NU
LVIC
V
CIN(26)
NV
NW
IGBT1
IGBT2
IGBT3
IGBT4
IGBT5
IGBT6
Di1
Di2
Di3
Di4
Di5
Di6
C1
D
CFO(25)
D1
C3
+
R2
V
OT
(20)
5kΩ
W
P
(18)
V
WFB
(15)
WFS
C1 D1 C2
+
V
P1
(16)
C2
HVIC
V
P
(12)
V
VFB
(9)
V
VFS
(7)
C1 D1 C2
+
V
P1
(10)
C2
HVIC
U
P
(6)
V
UFB
(3)
V
UFS
(1)
C1 D1 C2
+
V
P1
(4)
C2
HVIC
Long wiring here might
cause short circuit failure
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
9
Fig. 7 MCU I/O Interface Circuit
Fig. 8 P attern Wir in g Ar ound the S hunt Res ist or
Fig. 9 Pattern Wiring Around the Shunt Resistor (for the c ase of open emitter)
When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use
the external protection circuit as below.
(1) It is necessary to set the time constant RfCf of external comparator input so that IGBT stops within 2μs when short circuit occurs.
SC interrupting time might vary with the wiring pattern, comparator speed and so on.
(2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V).
(3) Select the external shunt resistance so that SC trip-level is less than specified value (=2.0 times of rating current).
(4) To avoid malfunction, the wiring A, B, C should be as short as possible.
(5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor.
(6) OR output high level when protection works should be over 0.51V (=maximum Vsc(ref) rating).
(7) GND of Comparator, GND of Vref circuit and Cf should be not connected to power GND but to control GND wiring.
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
Fo
V
NC
(Logic)
DIPIPM
MCU
10kΩ
5V line
3.3kΩ(min)
Note)
Desi gn for i nput RC fil ter dep ends o n PWM contr ol s chem e used
in the application and wiring impedance of the printed circuit board.
DIPIPM input signal interface integrates a minimum 3.3kΩ
pull-down resistor. Therefore, when inserting RC filter,
it is
necessary to satisfy turn-on threshold voltage requirement.
Fo output is open drain type. It should be pulled up to control
power supply (e.g. 5V, 15V) with a resistor that makes Fo sink
current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ
（5kΩ or more） is recommended.
Wiring Induc tance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, width=3mm is about 10nH.
NU, NV, NW should be connected
each other at near terminals.
N1
V
NC
NU
NV
NW
DIPIPM
V
NC
GND wi ring from V
NC
should
be
connected close to the
terminal of shunt resistor.
DIPIPM
NU
NV
NW
N1
Low inductanc e shunt resistor like surface mounted (SMD ) type is recommended.
GND wi ring fr om V
NC
should
be
connected close to the
terminal of shunt resistor.
Each wiring Inductance should be less than 10nH.
Inductance of a copper pattern with
length=17mm, wi dth=3mm is about 10nH.
P
V
U
W
N-side IGBT
P-side IGBT
Drive circuit
DIPIPM
V
NC
NW
Drive circuit
CIN
NV
NU
-
Vref
+
Vref
Vref
Comparators
(Open collector output type)
External protecti on circui t
Protection circuit
Shunt
resistors
Rf
Cf
5V
B
A
C
OR output
D
N1
-
+
-
+
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
10
Fig. 10 Package Outlines
Dimensions in mm
Terminal of ( ) is the dummy terminal for internal use. This terminal should be kept NC (no connection).
2D
CODE
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
11
Revis io n Reco rd
Rev. Date Page Revised contents
1
15/10/2013
-
New
2 25/12/2013 5
R evis e m isd escr ipti on (C ondit i on of Terminal pulling strength and Terminal bending
strength)
3 12/ 2/2014 1
[INTERNAL CIRCUIT] R evise mis desc ription of termi n al nam e( V
UFS
,V
UFB
, V
VFS
,
VVFB,VWFS,VWFB)
10
Fig .1 0 A nn otat i on is add ed.
4 15/ 3/2014
2
Add Note1
3
R evise misdesc r ip ti on of th e c ond it i on of VOT
5 7/8/2018
5
JEITA-ED-4701 was EIAJ-ED-4701
10
Change phrase to 2D CODE
< DIPIPM >
PSS30S71F6
TRA N SFE R MOLDING TYPE
INSULATED TYPE
Publication Date :August 2018
12
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