74ABT573ADB,118"" - NXP SEMICONDUCTORS

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 853–1455 15703

FEATURES

•74ABT573A is flow-through pinout version of 74ABT373

•Inputs and outputs on opposite side of package allow easy

interface to microprocessors

•3-State output buffers

•Common output enable

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

•Power-up 3-State

•Power-up reset

DESCRIPTION

The 74ABT573A high-performance BiCMOS device combines low

static and dynamic power dissipation with high speed and high

output drive.

The 74ABT573A device is an octal transparent latch coupled to

eight 3-State output buffers. The two sections of the device are

controlled independently by Enable (E) and Output Enable (OE)

control gates. The 74ABT573A is functionally identical to the

74ABT373 but has a flow-through pinout configuration to facilitate

PC board layout and allow easy interface with microprocessors.

The data on the D inputs are transferred to the latch outputs when

the Latch Enable (E) input is High. The latch remains transparent to

the data inputs while E is High, and stores the data that is present

one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors. The

active-Low Output Enable (OE) controls all eight 3-State buffers

independent of the latch operation.

When OE is Low, the latched or transparent data appears at the

outputs. When OE is High, the outputs are in the High-impedance

”OFF” state, which means they will neither drive nor load the bus.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS

Tamb = 25°C; GND = 0V TYPICAL UNIT

tPLH

tPHL Propagation delay

Dn to Qn CL = 50pF; VCC = 5V 2.8

3.3 ns

CIN Input capacitance VI = 0V or VCC 3pF

COUT Output capacitance Outputs disabled; VO = 0V or VCC 6pF

ICCZ Total supply current Outputs disabled; VCC =5.5V 100 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic DIP –40°C to +85°C74ABT573A N 74ABT573A N SOT146-1

20-Pin plastic SO –40°C to +85°C74ABT573A D 74ABT573A D SOT163-1

20-Pin Plastic SSOP Type II –40°C to +85°C74ABT573A DB 74ABT573A DB SOT339-1

20-Pin Plastic TSSOP Type I –40°C to +85°C74ABT573A PW 74ABT573APW DH SOT360-1

PIN CONFIGURATION

10 11

1VCC

GND

SA00185

PIN DESCRIPTION

NUMBER SYMBOL FUNCTION

1 OE Output enable input (active-Low)

2, 3, 4, 5,

6, 7, 8, 9 D0-D7 Data inputs

19, 18, 17,

16, 15, 14,

13, 12 Q0-Q7 Data outputs

11 E Enable input (active-High)

10 GND Ground (0V)

20 VCC Positive supply voltage

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 2

LOGIC SYMBOL (IEEE/IEC)

2D 1 19

SA00187

LOGIC SYMBOL

23456789

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

19 18 17 16 15 14 13 12

SA00186

FUNCTION TABLE

INPUTS INTERNAL OUTPUTS OPERATING MODE

OE E Dn REGISTER Q0 – Q7

HEnable and read register

L↓

↓l

HLatch and read register

L L X NC NC Hold

Dn NC

Dn Z

ZDisable outputs

H = High voltage level

h = High voltage level one set-up time prior to the High-to-Low E transition

L = Low voltage level

l = Low voltage level one set-up time prior to the High-to-Low E transition

NC= No change

X = Don’t care

Z = High impedance “of f” state

↓= High-to-Low E transition

LOGIC DIAGRAM

SA00188

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 3

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL PARAMETER CONDITIONS RATING UNIT

VCC DC supply voltage –0.5 to +7.0 V

IIK DC input diode current VI < 0 –18 mA

VIDC input voltage3–1.2 to +7.0 V

IOK DC output diode current VO < 0 –50 mA

VOUT DC output voltage3output in Off or High state –0.5 to +5.5 V

IOUT DC output current output in Low state 128 mA

Tstg Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute-maximum-rated conditions for extended periods may affect device reliability.

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

VCC DC supply voltage 4.5 5.5 V

VIInput voltage 0 VCC V

VIH High-level input voltage 2.0 V

VIL Low-level input voltage 0.8 V

IOH High-level output current –32 mA

IOL Low-level output current 64 mA

∆t/∆vInput transition rise or fall rate 0 5 ns/V

Tamb Operating free-air temperature range –40 +85 °C

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 4

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°CTamb = –40°C

to +85°CUNIT

Min Typ Max Min Max

VIK Input clamp voltage VCC = 4.5V ; IIK = –18mA –0.9 –1.2 –1.2 V

VCC = 4.5V ; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V

VOH High-level output voltage VCC = 5.0V ; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V

VCC = 4.5V ; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V

VOL Low-level output voltage VCC = 4.5V ; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V

VRST Power-up output low

voltage3VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V

IIInput leakage current VCC = 5.5V ; V I = GND or 5.5V ±0.01 ±1.0 ±1.0 µA

IOFF Power-of f leakage current VCC = 0.0V; VO or VI ≤4.5V ±5.0 ±100 ±100 µA

IPU/IPD Power-up/down 3-State

output current4VCC = 2.0V; VO = 0.5V ; V OE = Don’t Care;

VI = GND or VCC ±5.0 ±50 ±50 µA

IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA

IOZL 3-State output Low current VCC = 5.5V ; V O = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA

ICEX Output High leakage current VCC = 5.5V ; V O = 5.5V; VI = GND or V CC 5.0 50 50 µA

IOOutput current1VCC = 5.5V; VO = 2.5V –40 –180 –40 –180 mA

ICCH VCC = 5.5V; Outputs High, VI = GND or VCC 100 250 250 µA

ICCL Quiescent supply current VCC = 5.5V ; Outputs Low, VI = GND or VCC 24 30 30 mA

ICCZ VCC = 5.5V; Outputs 3-State;

VI = GND or VCC 100 250 250 µA

∆ICC Additional supply current per

input pin2VCC = 5.5V ; one input at 3.4V,

other inputs at VCC or GND 0.5 1.5 1.5 mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V  10%, a

transition time of up to 100µsec is permitted.

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM Tamb = +25oC

VCC = +5.0V

Tamb = -40 to

+85oC

VCC = +5.0V ±0.5V UNIT

Min Typ Max Min Max

tPLH

tPHL Propagation delay

Dn to Qn 21.5

2.2 2.8

3.3 4.0

4.8 1.5

2.2 4.5

5.3 ns

tPLH

tPHL Propagation delay

E to Qn 11.2

1.8 2.5

3.0 4.0

4.4 1.2

1.8 4.5

4.7 ns

tPZH

tPZL Output enable time

to High and Low level 4

51.2

2.7 3.0

3.8 4.5

5.3 1.2

2.7 5.2

5.7 ns

tPHZ

tPLZ Output disable time

from High and Low level 4

51.5

1.2 2.8

2.2 4.1

3.4 1.5

1.2 4.5

3.8 ns

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 5

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω

LIMITS

SYMBOL PARAMETER WAVEFORM Tamb = +25oC

VCC = +5.0V Tamb = -40 to +85oC

VCC = +5.0V ±0.5V UNIT

Min Typ Min

ts(H)

ts(L) Setup time, High or Low

Dn to E 31.0

1.0 0.3

0.2 1.0

1.0 ns

th(H)

th(L) Hold time, High or Low

Dn to E 31.0

1.0 –0.1

–0.2 1.0

1.0 ns

tw(H) E pulse width

High 1 2.0 0.7 2.0 ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

tw(H)

tPHL tPLH

SA00063

VMVMVM

VMVM

W aveform 1. Propagation Delay, Enable to Output, and Enable

Pulse Width

tPLH tPHL

SA00064

W aveform 2. Propagation Delay for Data to Outputs

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

ÉÉÉ

ÉÉÉÉÉÉÉÉ

ÉÉÉ

VMVM

ts(H) th(H) ts(L) th(L)

SA00065

W aveform 3. Data Setup and Hold Times

OE VM

tPZH tPHZ

Qn VM

SA00066

VOH–0.3V

W aveform 4. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

tPZL tPLZ

VOL

SA00332

VOL+0.3V

W aveform 5. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

Philips Semiconductors Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06 6

TEST CIRCUIT AND WAVEFORM

PULSE

GENERATOR

VIN VOUT

CLRL

VCC

7.0V

Test Circuit for 3-State Outputs

VMVM

tWAMP (V)

NEGATIVE

PULSE 10% 10%

90% 90%

VMVM

AMP (V)

POSITIVE

PULSE

90% 90%

10% 10% 0V

tTHL (tF)

tTLH (tR)t

THL (tF)

tTLH (tR)

VM = 1.5V

Input Pulse Definition

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of

pulse generators.

INPUT PULSE REQUIREMENTS

FAMILY Amplitude Rep. Rate tWtRtF

74ABT 3.0V 1MHz 500ns 2.5ns 2.5ns

SWITCH POSITION

TEST SWITCH

tPLZ closed

tPZL closed

All other open

SA00012

D.U.T.