SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
1
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DWide Bandwidth . . . 10 MHz
DHigh Output Drive
− IOH . . . 57 mA at VDD − 1.5 V
− IOL . . . 55 mA at 0.5 V
DHigh Slew Rate
− SR+ . . . 16 V/µs
− SR− . . . 19 V/µs
DWide Supply Range . . . 4.5 V to 16 V
DSupply Current . . . 1.9 mA/Channel
DUltralow Power Shutdown Mode
IDD . . . 125 µA/Channel
DLow Input Noise Voltage . . . 8.5 nV√Hz
DInput Offset Voltage ...60 µV
DUltra-Small Packages
− 8 or 10 Pin MSOP (TLC080/1/2/3)
description
The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC08x. The BiMOS
family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to
single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16
V across commercial (0°C to 70°C) and an extended industrial temperature range (−40°C to 125°C), BiMOS
suits a wide range of audio, automotive, industrial, and instrumentation applications. Familiar features like of fset
nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels
of performance in a variety of applications.
Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum
performance features of both. AC performance improvements over the TL08x BiFET predecessors include a
bandwidth of 10 MHz (an increase of 300%) and voltage noise of 8.5 nV/√Hz (an improvement of 60%). DC
improvements include an ensured VICR that includes ground, a factor of 4 reduction in input of fset voltage down
to 1.5 mV (maximum) in the standard grade, and a power supply rejection improvement of greater than 40 dB
to 130 dB. Added to this list of impressive features is the ability to drive ±50-mA loads comfortably from an
ultrasmall-footprint MSOP PowerPAD package, which positions the TLC08x as the ideal high-performance
general-purpose operational amplifier family.
FAMILY PACKAGE TABLE
DEVICE
NO. OF
PACKAGE TYPES
SHUTDOWN
UNIVERSAL
DEVICE
NO. OF
CHANNELS MSOP PDIP SOIC TSSOP
SHUTDOWN
UNIVERSAL
EVM BOARD
TLC080 1 8 8 8 — Yes
TLC081 1 8 8 8 —
Refer to the EVM
TLC082 2 8 8 8 — — Refer to the EVM
Selection Guide
TLC083 2 10 14 14 — Yes
Selection Guide
(Lit# SLOU060)
TLC084 4 — 14 14 20 —
(Lit# SLOU060)
TLC085 4 — 16 16 20 Yes
Copyright 2000−2004 Texas Instruments Incorporated
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1
%$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (2, (,%&) $# ,') ")(%+&,"()
)('"0'%0 3'%%'"(41 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0,
(,)(!"5 $# '// -'%'&,(,%)1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Operational Amplifier
−
+
PowerPAD is a trademark of Texas Instruments.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
2WWW.TI.COM
TLC080 and TLC081 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
†
SMALL OUTLINE
†
SYMBOL
PLASTIC DIP
TA
SMALL OUTLINE
(D)†
SMALL OUTLINE
(DGN)†
SYMBOL
PLASTIC DIP
(P)
0°C to 70°CTLC080CD
TLC081CD TLC080CDGN
TLC081CDGN xxTIACW
xxTIACY TLC080CP
TLC081CP
−40°C to 125°C
TLC080ID
TLC081ID TLC080IDGN
TLC081IDGN xxTIACX
xxTIACZ TLC080IP
TLC081IP
−40
°
C to 125
°
C
TLC080AID
TLC081AID —
——
—TLC080AIP
TLC081AIP
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC080CDR).
TLC082 and TLC083 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL
OUTLINE
MSOP PLASTIC
DIP
PLASTIC
DIP
TA
OUTLINE
(D)†(DGN)†SYMBOL‡(DGQ)†SYMBOL‡
DIP
(N)
DIP
(P)
0°C to 70°CTLC082CD
TLC083CD TLC082CDGN
—xxTIADZ
——
TLC083CDGQ —
xxTIAEB —
TLC083CN TLC082CP
—
−40°C to 125°C
TLC082ID
TLC083ID TLC082IDGN
—xxTIAEA
——
TLC083IDGQ —
xxTIAEC —
TLC083IN TLC082IP
—
−40
°
C to 125
°
C
TLC082AID
TLC083AID —
——
——
——
——
TLC083AIN TLC082AIP
—
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC082CDR).
‡xx represents the device date code.
TLC084 and TLC085 AVAILABLE OPTIONS
PACKAGED DEVICES
TASMALL OUTLINE
(D)†PLASTIC DIP
(N) TSSOP
(PWP)†
0°C to 70°CTLC084CD
TLC085CD TLC084CN
TLC085CN TLC084CPWP
TLC085CPWP
−40°C to 125°C
TLC084ID
TLC085ID TLC084IN
TLC085IN TLC084IPWP
TLC085IPWP
−40
°
C to 125
°
C
TLC084AID
TLC085AID TLC084AIN
TLC085AIN TLC084AIPWP
TLC085AIPWP
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g.,
TLC084CDR).
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
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TLC08x PACKAGE PINOUTS
NC − No internal connection
1
2
3
4
8
7
6
5
NULL
IN−
IN+
GND
SHDN
VDD
OUT
NULL
TLC080
D, DGN, OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NULL
IN−
IN+
GND
NC
VDD
OUT
NULL
TLC081
D, DGN, OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLC082
D, DGN, OR P PACKAGE
(TOP VIEW)
TLC083
D OR N PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
(TOP VIEW)
TLC085
D OR N PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLC084
D OR N PACKAGE
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1
SHDN
VDD
2OUT
2IN−
2IN+
2SHDN
TLC083
DGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
(TOP VIEW)
TLC084
PWP PACKAGE
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
NC
NC
NC
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
NC
NC
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
NC
NC
(TOP VIEW)
TLC085
PWP PACKAGE
TYPICAL PIN 1 INDICATORS
Printed or
Molded Dot Bevel Edges
Pin 1
Molded ”U” Shape
Pin 1
Stripe Pin 1 Pin 1
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage range, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING
D (8) 38.3 176 710 mW
D (14) 26.9 122.3 1022 mW
D (16) 25.7 114.7 1090 mW
DGN (8) 4.7 52.7 2.37 W
DGQ (10) 4.7 52.3 2.39 W
N (14, 16) 32 78 1600 mW
P (8) 41 104 1200 mW
PWP (20) 1.40 26.1 4.79 W
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 4.5 16
V
Supply voltage, VDD Split supply ±2.25 ±8V
Common-mode input voltage, VICR GND VDD−2 V
Shutdown on/off voltage level‡
VIH 2
V
Shutdown on/off voltage level‡
VIL 0.8
V
Operating free-air temperature, TA
C-suffix 0 70
°C
Operating free-air temperature, T
AI-suffix −40 125 °
C
‡Relative to the voltage on the GND terminal of the device.
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
TLC080/1/2/3,
25°C 390 1900
VIO
Input offset voltage
VDD = 5 V,
TLC080/1/2/3,
TLC084/5 Full range 3000
V
VIO Input offset voltage
VDD = 5 V,
V
IC
= 2.5 V,
TLC080/1/2/3A,
25°C 390 1400 µV
VIC = 2.5 V,
VO = 2.5 V,
RS = 50 Ω
TLC080/1/2/3A,
TLC084/5A Full range 2000
VIO
Temperature coefficient of input
O
RS = 50 Ω
1.2
V/°C
αVIO
Temperature coefficient of input
offset voltage 1.2 µV/°C
25°C 1.9 50
I
IO
Input offset current
VDD = 5 V,
TLC08XC
Full range
100 pA
IIO
Input offset current
V
DD
= 5 V,
VIC = 2.5 V,
TLC08XI Full range 700
pA
VIC = 2.5 V,
VO = 2.5 V,
R = 50 Ω
25°C 3 50
I
IB
Input bias current
VO = 2.5 V,
RS = 50 ΩTLC08XC
Full range
100 pA
IIB
Input bias current
TLC08XI Full range 700
pA
VICR
Common-mode input voltage
RS = 50 Ω
25°C0
to
3.0
0
to
3.5
V
VICR Common-mode input voltage RS = 50 Ω
Full range 0
to
3.0
0
to
3.5
V
IOH = −1 mA
25°C 4.1 4.3
IOH = −1 mA Full range 3.9
IOH = −20 mA
25°C 3.7 4
IOH = −20 mA Full range 3.5
VOH High-level output voltage VIC = 2.5 V
IOH = −35 mA
25°C 3.4 3.8 V
VOH
High-level output voltage
VIC = 2.5 V
IOH = −35 mA Full range 3.2
V
25°C 3.2 3.6
IOH = −50 mA −40°C to
85°C3
IOL = 1 mA
25°C 0.18 0.25
IOL = 1 mA Full range 0.35
IOL = 20 mA
25°C 0.35 0.39
IOL = 20 mA Full range 0.45
VOL Low-level output voltage VIC = 2.5 V
IOL = 35 mA
25°C 0.43 0.55 V
VOL
Low-level output voltage
VIC = 2.5 V
IOL = 35 mA Full range 0.7
V
25°C 0.45 0.63
IOL = 50 mA −40°C to
85°C0.7
IOS
Short-circuit output current
Sourcing 25°C 100
mA
IOS Short-circuit output current Sinking 25°C 100 mA
IO
Output current
VOH = 1.5 V from positive rail 25°C 57
mA
IOOutput current VOL = 0.5 V from negative rail 25°C 55 mA
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
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electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
(continued)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
AVD
Large-signal differential voltage
VO(PP) = 3 V,
RL = 10 kΩ
25°C 100 120
dB
AVD
Large-signal differential voltage
amplification VO(PP) = 3 V, RL = 10 kΩFull range 100 dB
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input
capacitance f = 10 kHz 25°C 22.9 pF
zoClosed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω
CMRR
Common-mode rejection ratio
VIC = 0 to 3 V,
RS = 50 Ω
25°C 80 110
dB
CMRR Common-mode rejection ratio VIC = 0 to 3 V, RS = 50 ΩFull range 80 dB
kSVR
Supply voltage rejection ratio
VDD = 4.5 V to 16 V,
VIC = VDD/2,
25°C 80 100
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 4.5 V to 16 V,
No load
VIC = VDD/2,
Full range 80 dB
IDD
Supply current (per channel)
VO = 2.5 V,
No load
25°C 1.8 2.5
mA
I
DD
Supply current (per channel)
V
O
= 2.5 V,
No load
Full range 3.5
mA
IDD(SHDN)
Supply current in shutdown
mode (per channel)
SHDN ≤ 0.8 V
25°C 125 200
A
IDD(SHDN
)
mode (per channel)
(TLC080, TLC083, TLC085) SHDN ≤ 0.8 V Full range 250 µA
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
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operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
SR+
Positive slew rate at unity gain
VO(PP) = 0.8 V,
CL = 50 pF,
25°C10 16
V/ s
SR+ Positive slew rate at unity gain
VO(PP) = 0.8 V,
RL = 10 kΩ
CL = 50 pF,
Full range 9.5 V/µs
SR−
Negative slew rate at unity gain
VO(PP) = 0.8 V,
CL = 50 pF,
25°C12.5 19
V/ s
SR− Negative slew rate at unity gain
VO(PP) = 0.8 V,
RL = 10 kΩ
CL = 50 pF,
Full range 10 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 12
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C 8.5
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
VO(PP) = 3 V,
AV = 1 0.002%
THD + N Total harmonic distortion plus noise
VO(PP) = 3 V,
R
L
= 10 kΩ and 250 Ω
,
f = 1 kHz
AV = 10 25°C0.012%
THD + N
Total harmonic distortion plus noise
RL = 10 kΩ and 250 Ω,
f = 1 kHz AV = 100
25 C
0.085%
t(on) Amplifier turnon time‡
RL = 10 kΩ
25°C 0.15 µs
t(off) Amplifier turnoff time‡RL = 10 kΩ25°C 1.3 µs
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ25°C 10 MHz
V(STEP)PP = 1 V,
AV = −1,
0.1% 0.18
ts
Settling time
AV = −1,
CL = 10 pF,
R
L
= 10 kΩ0.01%
25°C
0.39
s
tsSettling time V(STEP)PP = 1 V,
AV = −1,
0.1% 25°C0.18 µs
AV = −1,
CL = 47 pF,
R
L
= 10 kΩ0.01% 0.39
φm
Phase margin
RL = 10 kΩ, CL = 50 pF
25°C
32°
φmPhase margin RL = 10 kΩ,CL = 0 pF 25°C40°
Gain margin
RL = 10 kΩ, CL = 50 pF
25°C
2.2
dB
Gain margin
RL = 10 kΩ, CL = 0 pF
25
°
C
3.3
dB
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
‡Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
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electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
TLC0841/2/3,
25°C 390 1900
VIO
Input offset voltage
VDD = 12 V
TLC0841/2/3,
TLC084/5 Full range 3000
V
VIO Input offset voltage
VDD = 12 V
V
IC
= 6 V,
TLC0841/2/3A,
25°C 390 1400 µV
VIC = 6 V,
VO = 6 V,
RS = 50 Ω
TLC0841/2/3A,
TLC084/5A Full range 2000
VIO
Temperature coefficient of input
O
RS = 50 Ω
1.2
V/°C
αVIO
Temperature coefficient of input
offset voltage 1.2 µV/°C
25°C 1.5 50
I
IO
Input offset current
VDD = 12 V
TLC08xC
Full range
100 pA
IIO
Input offset current
V
DD
= 12 V
VIC = 6 V,
TLC08xI Full range 700
pA
VIC = 6 V,
VO = 6 V,
R = 50 Ω
25°C 2 50
I
IB
Input bias current
VO = 6 V,
RS = 50 ΩTLC08xC
Full range
100 pA
IIB
Input bias current
TLC08xI Full range 700
pA
VICR
Common-mode input voltage
RS = 50 Ω
25°C0
to
10.0
0
to
10.5
V
VICR Common-mode input voltage RS = 50 Ω
Full range 0
to
10.0
0
to
10.5
V
IOH = −1 mA
25°C 11.1 11.2
IOH = −1 mA Full range 11
IOH = −20 mA
25°C 10.8 11
IOH = −20 mA Full range 10.7
VOH High-level output voltage VIC = 6 V
IOH = −35 mA
25°C 10.6 10.7 V
VOH
High-level output voltage
VIC = 6 V
IOH = −35 mA Full range 10.3
V
25°C 10.3 10.5
IOH = −50 mA −40°C to
85°C10.2
IOL = 1 mA
25°C 0.17 0.25
IOL = 1 mA Full range 0.35
IOL = 20 mA
25°C 0.35 0.45
IOL = 20 mA Full range 0.5
VOL Low-level output voltage VIC = 6 V
IOL = 35 mA
25°C 0.4 0.52 V
VOL
Low-level output voltage
VIC = 6 V
IOL = 35 mA Full range 0.6
V
25°C 0.45 0.6
IOL = 50 mA −40°C to
85°C0.65
IOS
Short-circuit output current
Sourcing 25°C 150
mA
IOS Short-circuit output current Sinking 25°C 150 mA
IO
Output current
VOH = 1.5 V from positive rail 25°C 57
mA
IOOutput current VOL = 0.5 V from negative rail 25°C 55 mA
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
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electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted)
(continued)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
AVD
Large-signal differential voltage
VO(PP) = 8 V,
RL = 10 kΩ
25°C 120 140
dB
AVD
Large-signal differential voltage
amplification VO(PP) = 8 V, RL = 10 kΩFull range 120 dB
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input
capacitance f = 10 kHz 25°C 21.6 pF
zoClosed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω
CMRR
Common-mode rejection ratio
VIC = 0 to 10 V,
RS = 50 Ω
25°C 80 110
dB
CMRR Common-mode rejection ratio VIC = 0 to 10 V, RS = 50 ΩFull range 80 dB
kSVR
Supply voltage rejection ratio
VDD = 4.5 V to 16 V,
VIC = VDD/2,
25°C 80 100
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 4.5 V to 16 V,
No load
VIC = VDD/2,
Full range 80 dB
IDD
Supply current (per channel)
VO = 7.5 V,
No load
25°C 1.9 2.9
mA
I
DD
Supply current (per channel)
V
O
= 7.5 V,
No load
Full range 3.5
mA
IDD(SHDN)
Supply current in shutdown
mode (TLC080, TLC083,
SHDN ≤ 0.8 V
25°C 125 200
A
IDD(SHDN
)
mode (TLC080, TLC083,
TLC085) (per channel) SHDN ≤ 0.8 V Full range 250 µA
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
10 WWW.TI.COM
operating characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
SR+
Positive slew rate at unity gain
VO(PP) = 2 V,
CL = 50 pF,
25°C10 16
V/ s
SR+ Positive slew rate at unity gain
VO(PP) = 2 V,
RL = 10 kΩ
CL = 50 pF,
Full range 9.5 V/µs
SR−
Negative slew rate at unity gain
VO(PP) = 2 V,
CL = 50 pF,
25°C12.5 19
V/ s
SR− Negative slew rate at unity gain
VO(PP) = 2 V,
RL = 10 kΩ
CL = 50 pF,
Full range 10 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 14
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C 8.5
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
VO(PP) = 8 V,
AV = 1 0.002%
THD + N Total harmonic distortion plus noise
VO(PP) = 8 V,
R
L
= 10 kΩ and 250 Ω
,
f = 1 kHz
AV = 10 25°C0.005%
THD + N
Total harmonic distortion plus noise
RL = 10 kΩ and 250 Ω,
f = 1 kHz AV = 100
25 C
0.022%
t(on) Amplifier turnon time‡
RL = 10 kΩ
25°C 0.47 µs
t(off) Amplifier turnoff time‡RL = 10 kΩ25°C 2.5 µs
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ25°C 10 MHz
V(STEP)PP = 1 V,
AV = −1,
0.1% 0.17
ts
Settling time
AV = −1,
CL = 10 pF,
R
L
= 10 kΩ0.01%
25°C
0.22
s
tsSettling time V(STEP)PP = 1 V,
AV = −1,
0.1% 25°C0.17 µs
AV = −1,
CL = 47 pF,
R
L
= 10 kΩ0.01% 0.29
φm
Phase margin
RL = 10 kΩ, CL = 50 pF
25°C
37°
φmPhase margin RL = 10 kΩ,CL = 0 pF 25°C42°
Gain margin
RL = 10 kΩ, CL = 50 pF
25°C
3.1
dB
Gain margin
RL = 10 kΩ, CL = 0 pF
25
°
C
4
dB
†Full range is 0°C to 70°C for C suffix and −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
‡Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
IIO Input offset current vs Free-air temperature 3, 4
IIB Input bias current vs Free-air temperature 3, 4
VOH High-level output voltage vs High-level output current 5, 7
VOL Low-level output voltage vs Low-level output current 6, 8
ZoOutput impedance vs Frequency 9
IDD Supply current vs Supply voltage 10
PSRR Power supply rejection ratio vs Frequency 11
CMRR Common-mode rejection ratio vs Frequency 12
VnEquivalent input noise voltage vs Frequency 13
VO(PP) Peak-to-peak output voltage vs Frequency 14, 15
Crosstalk vs Frequency 16
Differential voltage gain vs Frequency 17, 18
Phase vs Frequency 17, 18
φmPhase margin vs Load capacitance 19, 20
Gain margin vs Load capacitance 21, 22
Gain-bandwidth product vs Supply voltage 23
SR Slew rate vs Supply voltage
vs Free-air temperature 24
25, 26
THD + N
Total harmonic distortion plus noise
vs Frequency 27, 28
THD + N Total harmonic distortion plus noise vs Peak-to-peak output voltage 29, 30
Large-signal follower pulse response 31, 32
Small-signal follower pulse response 33
Large-signal inverting pulse response 34, 35
Small-signal inverting pulse response 36
Shutdown forward isolation vs Frequency 37, 38
Shutdown reverse isolation vs Frequency 39, 40
Shutdown supply current
vs Supply voltage 41
Shutdown supply current vs Free-air temperature 42
Shutdown pulse 43, 44
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
12 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 1
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0
−200
−400
−600
0.0 0.5 1.0 1.5 2.0 2.5 3.0
200
400
600
800
1000
3.5 4.0 4.5 5.0
VICR − Common-Mode Input Voltage − V
VDD = 5 V
TA = 25° C
VIO − Input Offset Voltage − Vµ
Figure 2
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
300
100
−100
−300
−5000123456
500
700
900
1100
1500
1300
789101112
VICR − Common-Mode Input Voltage − V
V
IO
− Input Offset Voltage − V
µ
VDD = 12 V
TA = 25° C
Figure 3
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
−100
−55 −40
50
200
−10 5
TA − Free−Air Temperature − °C
150
100
−50
−25 20 35 50
IIB
/I
IO
Input Bias and Input Offset Current − pAI
IB
−
VDD = 5 V
65 80 95 110 125
250
300
IIO
0
Figure 4
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
−120
−55 −40
−80
−20
−10 5
TA − Free-Air Temperature − °C
IIO
−40
−60
−100
−25
−140
−160 20 35 50
IIB
/IIO Input Bias and Input Offset Current − pAIIB −
VDD = 12 V
65 80 95 110 125
0
20
Figure 5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25 30 35 40 45 50
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH - High-Level Output Current - mA
VDD = 5 V
VOH − High-Level Output Voltage − V
TA = 125°C
TA = 70°CTA = 25°C
TA = −40°C
Figure 6
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25 30 35 40 45 50
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL - Low-Level Output Current - mA
TA = 125°C
TA = 70°C
TA = 25°C
TA = −40°C
VDD = 5 V
OL
V − Low-Level Output Voltage − V
Figure 7
9.0
9.5
10.0
10.5
11.0
11.5
12.0
0 5 10 15 20 25 30 35 40 45 50
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH - High-Level Output Current - mA
TA = 125°C
TA = 70°C
TA = 25°CTA = −40°C
VOH − High-Level Output Voltage − V
VDD = 12 V
Figure 8
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25 30 35 40 45 50
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL - Low-Level Output Current - mA
TA = 125°C
TA = 25°C
TA = −40°C
OL
V − Low-Level Output Voltage − V
VDD = 12 V
TA = 70°C
Figure 9
OUTPUT IMPEDANCE
vs
FREQUENCY
f - Frequency - Hz
100k
1000
1M 10M
− Output Impedance −Z
oΩ
10k100 1k
100
10
1
0.10
0.01
AV = 100
AV = 10
AV = 1
VDD = 5 V and 12
V
TA = 25°C
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
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TYPICAL CHARACTERISTICS
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
456789101112131415
TA = −40°C
Figure 10
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage - V
AV = 1
SHDN = VDD
Per Channel
TA = 125°C
TA = 70°C
TA = 25°C
IDD − Supply Current − mA
Figure 11
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
40
010
80
140
1k 10k
f − Frequency − Hz
VDD = 12 V
120
100
60
100
20
0
− Power Supply Rejection Ratio − dBPSRR
100k 1M 10M
VDD = 5 V
0
20
40
60
80
100
120
140
Figure 12
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k100 1k
CMRR − Common-Mode Rejection Ratio − dB
VDD = 5 V and 12 V
TA = 25°C
Figure 13
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
0
10 100
10
25
10k 100k
f − Frequency − Hz
VDD = 5 V
40
VDD = 12 V
35
30
20
15
5
1k
nV/ Hz− Equivalent Input Noise Voltage −Vn
Figure 14
0
2
4
6
8
10
12
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k
THD+N < = 5%
RL = 600 Ω
TA = 25°C
VDD = 12 V
VDD = 5 V
VO(PP) − Peak-to-Peak Output Voltage − V
Figure 15
0
2
4
6
8
10
12
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k
VO(PP) − Peak-to-Peak Output Voltage − V
THD+N < = 5%
RL= 10 kΩ
TA = 25°C
VDD = 12 V
VDD = 5 V
Figure 16
−120
10 100
−80
−20
10k
f − Frequency − Hz
0
−40
−60
−100
1k
−140
−160
Crosstalk − dB
100k
CROSSTALK
vs
FREQUENCY
VDD = 5 V and 12 V
AV = 1
RL = 10 kΩ
VI(PP) = 2 V
For All Channels
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TYPICAL CHARACTERISTICS
Figure 17
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
0
1k 10k
20
50
1M 10M
f − Frequency − Hz
Gain
80
70
60
40
30
10
100k
−10
−20
− Different Voltage Gain − dBAVD
100M
−180
−135
0
−45
−90
−225
Phase
VDD = ±2.5 V
RL = 10 kΩ
CL = 0 pF
TA = 25°C
Phase − °
Figure 18
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
0
1k 10k
20
50
1M 10M
f − Frequency − Hz
Gain
80
70
60
40
30
10
100k
−10
−20
− Different Voltage Gain − dBAVD
100M
−180
−135
0
−45
−90
−225
Phase
VDD = ±6 V
RL = 10 kΩ
CL = 0 pF TA
= 25°C
Phase − °
Figure 19
PHASE MARGIN
vs
LOAD CAPACITANCE
10°
10
20°
35°
CL − Load Capacitance − pF
30°
25°
15°
100
5°
0°
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 5 V
RL = 10 kΩ
TA = 25°C
40°
m
φ− Phase Margin
Figure 20
PHASE MARGIN
vs
LOAD CAPACITANCE
10°
10
20°
35°
CL − Load Capacitance − pF
30°
25°
15°
100
5°
0°
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 12 V
RL = 10 kΩ
TA = 25°C
40°
45°
m
φ
− Phase Margin
Figure 21
GAIN MARGIN
vs
LOAD CAPACITANCE
1
10
2
4
CL − Load Capacitance − pF
3.5
2.5
1.5
100
0.5
0
− Gain Margin − dBG
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 5 V
RL = 10 kΩ
TA = 25°C
3
Figure 22
GAIN MARGIN
vs
LOAD CAPACITANCE
1
10
2
3.5
CL − Load Capacitance − pF
3
2.5
1.5
100
0.5
0
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 12 V
RL = 10 kΩ
TA = 25°C
4
4.5
5
m
φ− Phase Margin − dB
Figure 23
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.0
45678910111213141516
CL = 11 pF
TA = 25°C
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
VDD - Supply Voltage - V
GBWP - Gain Bandwidth Product - MHz
RL = 10 kΩ
RL = 600 Ω
Figure 24
12
13
14
15
16
17
18
19
20
21
22
45678910111213141516
SLEW RATE
vs
SUPPLY VOLTAGE
VDD - Supply Voltage - V
RL = 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
SR − Slew Rate − V/ µs
Slew Rate +
Slew Rate −
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TYPICAL CHARACTERISTICS
Figure 25
0
5
10
15
20
25
−55 −35 −15 5 25 45 65 85 105 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
VDD = 5 V
RL= 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
SR − Slew Rate − V/ µs
Slew Rate +
Slew Rate −
Figure 26
0
5
10
15
20
25
−55 −35 −15 5 25 45 65 85 105 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
VDD = 12 V
RL= 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
SR − Slew Rate − V/ µs
Slew Rate +
Slew Rate −
Figure 27
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
0.001
100 1k
0.01
0.1
10k 100k
f − Frequency − Hz
AV = 100
AV = 10
AV = 1
1
Total Harmonic Distortion + Noise − %
VDD = 5 V
VO(PP) = 2 V
RL = 10 kΩ
Figure 28
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
Total Harmonic Distortion + Noise − %
0.001
100 1k
0.01
0.1
10k 100k
f − Frequency − Hz
AV = 100
VDD = 12 V
VO(PP) = 8 V
RL = 10 kΩ
AV = 10
AV = 1
Figure 29
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
Total Harmonic Distortion + Noise − %
0.0001
0.25 0.75
0.01
0.1
1.25 1.75
VO(PP) − Peak-to-Peak Output Voltage − V
2.25 2.75 3.25 3.75
0.001
1
10 VDD = 5 V
AV = 1
f = 1 kHz RL = 250 Ω
RL = 600 Ω
RL = 10 kΩ
Figure 30
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
Total Harmonic Distortion + Noise − %
0.0001
0.5 2.5
0.01
0.1
4.5 6.5
VO(PP) − Peak-to-Peak Output Voltage − V
8.5 10.5
0.001
1
10 VDD = 12 V
AV = 1
f = 1 kHz
RL = 250 Ω
RL = 600 Ω
RL = 10 kΩ
Figure 31
t − Time − µs
0 0.2 0.4 0.6 0.8 1 1.2
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
1.4 1.6 1.8 2
− Output Voltage − VVO
VI (1 V/Div)
VO (500 mV/Div)
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
Figure 32
t − Time − µs
0 0.2 0.4 0.6 0.8 1 1.2
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
1.4 1.6 1.8 2
− Output Voltage − VV
O
VI (5 V/Div)
VO (2 V/Div)
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
Figure 33
SMALL SIGNAL FOLLOWER PULSE
RESPONSE
0 0.1 0.3 0.4
t − Time − µs
0.2 0.5 0.6 0.7 0.8 0.9 0.10
VO(50mV/Div)
VI(100mV/Div)
VDD = 5 V and 12 V
RL = 600 Ω and 10 kΩ
CL = 8 pF
TA = 25°C
− Output Voltage − V
V
O
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
16 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 34
t − Time − µs
0 0.2 0.4 0.6 0.8 1 1.2
LARGE SIGNAL INVERTING
PULSE RESPONSE
1.4 1.6 1.8 2
− Output Voltage − VVO
VI (2 V/div)
VO (500 mV/Div)
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
Figure 35
t − Time − µs
0 0.2 0.4 0.6 0.8 1 1.2
LARGE SIGNAL INVERTING
PULSE RESPONSE
1.4 1.6 1.8 2
− Output Voltage − VV
O
VI (5 V/div)
VO (2 V/Div)
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
Figure 36
t − Time − µs
0 0.1 0.2 0.3 0.4 0.5 0.6
SMALL SIGNAL INVERTING
PULSE RESPONSE
0.7 0.8 0.9 1
− Output Voltage − VV
O
VI (100 mV/div)
VO (50 mV/Div)
VDD = 5 V and 12 V
RL = 600 Ω and 10 kΩ
CL = 8 pF
TA = 25°C
Figure 37
20
40
60
80
100
120
140
SHUTDOWN FORWARD
ISOLATION
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k100 1k
Sutdown Forward Isolation - dB
100M
VDD = 5 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 2.5, and 5 V
RL = 600 Ω
RL = 10 kΩ
Figure 38
20
40
60
80
100
120
140
SHUTDOWN FORWARD
ISOLATION
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k100 1k
Sutdown Forward Isolation - dB
100M
VDD = 12 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 8, 12 V
RL = 600 Ω
RL = 10 kΩ
Figure 39
20
40
60
80
100
120
140
SHUTDOWN REVERSE
ISOLATION
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k100 1k
Sutdown Reverse Isolation - dB
100M
RL = 600 Ω
RL = 10 kΩ
VDD = 5 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 2.5, and 5 V
Figure 40
20
40
60
80
100
120
140
SHUTDOWN REVERSE
ISOLATION
vs
FREQUENCY
f - Frequency - Hz
100k 1M 10M10k100 1k
Sutdown Reverse Isolation - dB
100M
VDD = 12 V
CL= 0 pF
TA = 25°C
VI(PP) = 0.1, 8, 12 V
RL = 600 Ω
RL = 10 kΩ
Figure 41
118
120
122
124
126
128
130
132
134
136
45678910111213141516
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD - Supply Voltage - V
IDD(SHDN) − Shutdown Supply Current - Aµ
Shutdown On
RL = open
VIN = VDD/2
Figure 42
60
80
100
120
140
160
180
−55 −25 5 35 65 95 125
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
VDD = 12 V
AV = 1
VIN = VDD/2
IDD(SHDN) − Shutdown Supply Current - Aµ
VDD = 5 V
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TYPICAL CHARACTERISTICS
Figure 43
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 1020304050607080
−2
−4
2
6
t - Time - µs
0
−6
4
Shutdown Pulse SD Off
VDD = 5 V
CL= 8 pF
TA = 25°C
IDD RL = 600 Ω
IDD RL = 10 kΩ
IDD − Supply Current − mA
Shutdown Pulse - V
SHUTDOWN PULSE
Figure 44
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 1020304050607080
−2
−4
2
6
t - Time - µs
0
−6
4
Shutdown Pulse SD Off
VDD = 12 V
CL= 8 pF
TA = 25°C
IDD RL = 600 Ω
IDD RL = 10 kΩ
IDD − Supply Current − mA
Shutdown Pulse - V
SHUTDOWN PULSE
PARAMETER MEASUREMENT INFORMATION
_
+
Rnull
RLCL
Figure 45
APPLICATION INFORMATION
input offset voltage null circuit
The TLC080 and TLC081 has an input offset nulling function. Refer to Figure 46 for the diagram.
N1
100 kΩ
+
−
N2
R1
VDD−
OUT
IN−
IN+
NOTE A: R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV.
R1 = 20 kΩ for offset voltage adjustment of ±3 mV.
Figure 46. Input Offset Voltage Null Circuit
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18 WWW.TI.COM
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 47. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
_
+
Figure 47. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 48. Output Offset Voltage Model
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APPLICATION INFORMATION
high speed CMOS input amplifiers
The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input
capacitance of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function
equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance.
For example, a gain of −10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional
pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their
greater input capacitance.
This is o f little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs
at frequencies where there is on the order of 5dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180_ phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buf fer and with a 10-kΩ feedback resistor. B y adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x.
_
+
600 Ω22 pF
50 Ω
10 kΩ
10 pF
IN
With
CF = 10 pF
VDD = ±5 V
AV = +1
RF = 10 kΩ
RL = 600 Ω
CL = 22 pF
VI− Input Voltage − V
0
0.5
1
1.5
1
0
−1
2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
− Output Voltage − V
VO
t - Time - µs
VIN
VOUT
−0.5
Figure 49. 1-V Step Response
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
20 WWW.TI.COM
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 50).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
21
WWW.TI.COM
APPLICATION INFORMATION
shutdown function
Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery
life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125
µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply vo l t a ges (e.g. ±2.5 V), the shutdown terminal needs to be pulled to VDD− (not system ground) to disable
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a
single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figures 37, 38, 39, and 40 show the amplifier ’s forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency
using 0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals
at ±6 V supplies.
circuit layout considerations
To achieve the levels of high performance of the TLC08x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
DSurface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
22 WWW.TI.COM
APPLICATION INFORMATION
general PowerPAD design considerations
The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE B: The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
68 mils x 70 mils with 5 vias
(Via diameter = 13 mils) 78 mils x 94 mils with 9 via
s
(Via diameter = 13 mils)
Thermal Pad Area
Single or Dual
Quad
Figure 53. PowerPAD PCB Etch and Via Pattern
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
23
WWW.TI.COM
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 53. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils
in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLC08x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 54 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLC08x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
24 WWW.TI.COM
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
TJ = 150°C
4
3
2
0
−55 −40 −10 20 35
Maximum Power Dissipation − W
5
6
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
65 95 125
1
TA − Free-Air Temperature − °C
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
−25 5 50 80 110
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 54. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in
these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
25
WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model generation software used
with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using
the TLC08x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
PSpice and Parts are trademarks of MicroSim Corporation.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
26 WWW.TI.COM
APPLICATION INFORMATION
OUT
+
−
+
−
+
−
+
−
+
−
+
−
+
−+
−
+−
.subckt TLC08X_5V 1 2 3 4 5
*
c1 11 12 4.6015E−12
c2 6 7 8.0000E−12
css 10 99 986.29E−15
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 13.984E6 −1E3 1E3
14E6 −14E6
ga 6 0 11 12 402.12E−6
gcm 0 6 10 99 1.5735E−6
ioff 0 6 dc 1.212E−6
iss 3 10 dc 130.40E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
j2 12 1 10 jx2
r2 6 9 100.00E3
rd1 4 11 2.4868E3
rd2 4 12 2.4868E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 2.8249E3
rss 10 99 1.5337E6
vb 9 0 dc 0
vc 3 53 dc 1.5537
ve 54 4 dc .84373
vlim 7 8 dc 0
vlp 91 0 dc 117.60
vln 0 92 dc 117.60
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
.model jx2 PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1)
.ends
VDD
RP
IN − 2
IN+ 1
GND VAD
RD1
11
J1 J2
10
RSS ISS
3
12
RD2
60
VE
54 DE
DP
VC
DC
4
C1
53
R2 6
9
EGND
VB
FB
C2
GCM GA VLIM
8
5RO1
RO2
HLIM
90 DLP
91
DLN
92
VLNVLP
99
7
*DEVICE=TLC08X_5V, OPAMP, PJF, INT
* TLC08X_5V − 5V operational amplifier ”macromodel” sub-
circuit
* created using Parts release 8.0 on 12/16/99 at 14:03
* Parts is a MicroSim product.
*
* connections: non-inverting input
* inverting input
* positive power supply
* negative power supply
* output
*
Figure 55. Boyle Macromodel and Subcircuit
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
27
WWW.TI.COM
THERMAL PAD MECHANICAL DATA
DGQ (S−PDSO−G10) PowerPADt PLASTIC SMALL-OUTLINE
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
28 WWW.TI.COM
THERMAL PAD MECHANICAL DATA
DGN (S−PDSO−G8) PowerPADt PLASTIC SMALL-OUTLINE
NOTES:
Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application
Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.
PowerPAD is a trademark of Texas Instruments
B. This drawing is subject to change without notice.
C. For additional information on the PowerPADpackage and how to take advantage of its heat dissipating abilities, refer to
PPTD041
Not to Scale
Top View
85
14
Exposed Pad
1,73 MAX
1,78 MAX
A. All linear dimensions are in millimeters.
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
29
WWW.TI.COM
THERMAL PAD MECHANICAL DATA
PPTD023
PWP (R− PDSO− G14) PowerPADt PLASTIC SMALL−OUTLINE
SLOS254D − JUNE 1999 − REVISED FEBRUAR Y 2004
30 WWW.TI.COM
THERMAL PAD MECHANICAL DATA
PPTD024
PWP (R− PDSO− G16) PowerPADt PLASTIC SMALL−OUTLINE
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°– 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC080AID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080AIDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC080AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC080CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC080CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC080ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLC080IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC081AID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC081AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC081CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGNG4 ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC081CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC081ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 2
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLC081IPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082AID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082AIPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082CD ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082CPE4 ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082ID ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGN ACTIVE MSOP-
Power
PAD
DGN 8 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGNR ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGNRG4 ACTIVE MSOP-
Power
PAD
DGN 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC082IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 3
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS)
TLC083AID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083AIN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC083AINE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC083CD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDGQ ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDGQG4 ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC083CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC083ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDGQ ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC083INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 4
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC084AID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084AINE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084AIPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CD ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084CNE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084ID ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IDR ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IN ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084INE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS) CU NIPD Level-NC-NC-NC
TLC084IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084IPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084IPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085AID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 5
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC085AIN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085AINE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085AIPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085AIPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085CD ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085CDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085CN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085CNE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085ID ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085IDG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085IDR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085IN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085INE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC085IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085IPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085IPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085IPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 6
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Sep-2005
Addendum-Page 7
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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