SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 D Wide Bandwidth . . . 10 MHz D High Output Drive D D D D D D D Operational Amplifier - IOH . . . 57 mA at VDD - 1.5 V - IOL . . . 55 mA at 0.5 V High Slew Rate - SR+ . . . 16 V/s - SR- . . . 19 V/s Wide Supply Range . . . 4.5 V to 16 V Supply Current . . . 1.9 mA/Channel Ultralow Power Shutdown Mode IDD . . . 125 A/Channel Low Input Noise Voltage . . . 8.5 nVHz Input Offset Voltage . . . 60 V Ultra-Small Packages - 8 or 10 Pin MSOP (TLC080/1/2/3) - + description The first members of TI's new BiMOS general-purpose operational amplifier family are the TLC08x. The BiMOS family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16 V across commercial (0C to 70C) and an extended industrial temperature range (-40C to 125C), BiMOS suits a wide range of audio, automotive, industrial, and instrumentation applications. Familiar features like offset nulling pins, and new features like MSOP PowerPAD packages and shutdown modes, enable higher levels of performance in a variety of applications. Developed in TI's patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum performance features of both. AC performance improvements over the TL08x BiFET predecessors include a bandwidth of 10 MHz (an increase of 300%) and voltage noise of 8.5 nV/Hz (an improvement of 60%). DC improvements include an ensured VICR that includes ground, a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum) in the standard grade, and a power supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of impressive features is the ability to drive 50-mA loads comfortably from an ultrasmall-footprint MSOP PowerPAD package, which positions the TLC08x as the ideal high-performance general-purpose operational amplifier family. FAMILY PACKAGE TABLE PACKAGE TYPES NO. OF CHANNELS MSOP PDIP SOIC TSSOP TLC080 1 8 8 8 -- TLC081 1 8 8 8 -- TLC082 2 8 8 8 -- -- TLC083 2 10 14 14 -- Yes TLC084 4 -- 14 14 20 -- TLC085 4 -- 16 16 20 Yes DEVICE SHUTDOWN UNIVERSAL EVM BOARD Yes Refer to the EVM Selection Guide (Lit# SLOU060) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2000-2004 Texas Instruments Incorporated !"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1 %$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (2, (,%&) $# , ') ")(%+&,"() )('"0'%0 3'%%'"(41 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0, (,)(!"5 $# '// -'%'&,(,%)1 WWW.TI.COM 1 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TLC080 and TLC081 AVAILABLE OPTIONS PACKAGED DEVICES TA 0C to 70C -40C to 125C SMALL OUTLINE (D) SMALL OUTLINE (DGN) SYMBOL PLASTIC DIP (P) TLC080CD TLC081CD TLC080CDGN TLC081CDGN xxTIACW xxTIACY TLC080CP TLC081CP TLC080ID TLC081ID TLC080IDGN TLC081IDGN xxTIACX xxTIACZ TLC080IP TLC081IP -- -- -- -- TLC080AID TLC081AID TLC080AIP TLC081AIP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC080CDR). TLC082 and TLC083 AVAILABLE OPTIONS PACKAGED DEVICES TA 0C to 70C -40C to 125C SMALL OUTLINE (D) SYMBOL PLASTIC DIP (N) PLASTIC DIP (P) (DGN) SYMBOL (DGQ) TLC082CD TLC083CD TLC082CDGN -- xxTIADZ -- -- TLC083CDGQ -- xxTIAEB -- TLC083CN TLC082CP -- TLC082ID TLC083ID TLC082IDGN -- xxTIAEA -- -- TLC083IDGQ -- xxTIAEC -- TLC083IN TLC082IP -- TLC082AID TLC083AID -- -- -- -- -- -- -- -- -- TLC083AIN TLC082AIP -- MSOP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC082CDR). xx represents the device date code. TLC084 and TLC085 AVAILABLE OPTIONS PACKAGED DEVICES TA 0C to 70C -40C to 125C SMALL OUTLINE (D) PLASTIC DIP (N) TSSOP (PWP) TLC084CD TLC085CD TLC084CN TLC085CN TLC084CPWP TLC085CPWP TLC084ID TLC085ID TLC084IN TLC085IN TLC084IPWP TLC085IPWP TLC084AID TLC085AID TLC084AIN TLC085AIN TLC084AIPWP TLC085AIPWP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC084CDR). 2 WWW.TI.COM SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TLC08x PACKAGE PINOUTS TLC080 D, DGN, OR P PACKAGE (TOP VIEW) NULL IN - IN + GND 1 8 2 7 3 6 4 5 SHDN VDD OUT NULL TLC081 D, DGN, OR P PACKAGE (TOP VIEW) NULL IN - IN + GND TLC083 DGQ PACKAGE (TOP VIEW) 1OUT 1IN - 1IN+ GND 1SHDN 1 2 3 4 5 10 9 8 7 6 VDD 2OUT 2IN - 2IN+ 2SHDN 1 20 2 19 3 18 4 17 5 16 6 7 15 14 8 13 9 12 10 11 7 3 6 4 5 NC VDD OUT NULL 1OUT 1IN - 1IN + GND 8 2 7 3 6 4 5 (TOP VIEW) (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD 2OUT 2IN - 2IN+ NC 2SHDN NC 1OUT 1IN - 1IN+ VDD 2IN+ 2IN - 2OUT 1 16 2 15 3 14 4 5 6 7 8 13 12 11 10 9 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN - 4IN+ GND 3IN+ 3IN - 3OUT (TOP VIEW) (TOP VIEW) 1OUT 1IN - 1IN+ VDD 2IN+ 2IN - 2OUT 1/2SHDN 1 VDD 2OUT 2IN - 2IN+ TLC085 PWP PACKAGE TLC085 D OR N PACKAGE 4OUT 4IN- 4IN+ GND 3IN+ 3IN- 3OUT NC NC NC 1 TLC084 D OR N PACKAGE (TOP VIEW) 1OUT 1IN- 1IN+ VDD 2IN+ 2IN- 2OUT NC NC NC 8 2 TLC083 D OR N PACKAGE 1OUT 1IN - 1IN+ GND NC 1SHDN NC TLC084 PWP PACKAGE 1 TLC082 D, DGN, OR P PACKAGE (TOP VIEW) 4OUT 4IN - 4IN+ GND 3IN + 3IN- 3OUT 3/4SHDN 1OUT 1IN- 1IN+ VDD 2IN+ 2IN- 2OUT 1/2SHDN NC NC 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 4OUT 4IN- 4IN+ GND 3IN+ 3IN- 3OUT 3/4SHDN NC NC NC - No internal connection TYPICAL PIN 1 INDICATORS Pin 1 Printed or Molded Dot Pin 1 Stripe Pin 1 Bevel Edges Pin 1 Molded "U" Shape WWW.TI.COM 3 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V Differential input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND . DISSIPATION RATING TABLE PACKAGE JC (C/W) JA (C/W) TA 25C POWER RATING D (8) 38.3 176 710 mW D (14) 26.9 122.3 1022 mW D (16) 25.7 114.7 1090 mW DGN (8) 4.7 52.7 2.37 W DGQ (10) 4.7 52.3 2.39 W N (14, 16) 32 78 1600 mW P (8) 41 104 1200 mW PWP (20) 1.40 26.1 4.79 W recommended operating conditions Single supply Supply voltage, VDD Split supply Common-mode input voltage, VICR Shutdown on/off voltage level Operating free-air temperature, TA VIH VIL C-suffix I-suffix Relative to the voltage on the GND terminal of the device. 4 WWW.TI.COM MIN MAX 4.5 16 2.25 8 V GND VDD-2 V 2 0.8 0 70 -40 125 UNIT V C SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage VIO Temperature coefficient of input offset voltage TEST CONDITIONS VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 TLC080/1/2/3, TLC084/5 TLC080/1/2/3A, TLC084/5A TA 25C MIN IIB Input offset current Input bias current Common-mode input voltage VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 TLC08XI 3000 25C 390 Full range IOH = - 35 mA 3 Full range 0 to 3.0 0 to 3.5 Full range 0 to 3.0 0 to 3.5 25C 4.1 4.3 Full range 3.9 25C 3.7 Full range 3.5 25C 3.4 Full range 3.2 25C 3.2 Full range IOL = 20 mA Full range 25C IOL = 35 mA IOS Short-circuit output current IO Output current V 4 V 3.8 3.6 0.18 0.25 0.35 0.35 0.39 0.45 0.43 0.55 0.45 0.63 Full range 25C IOL = 50 mA pA 3 25C VIC = 2.5 V 50 700 25C IOL = 1 mA pA 700 25C Low-level output voltage 50 100 -40C to 85C V V V/C V/C 100 Full range RS = 50 VIC = 2.5 V 1.9 25C IOH = - 50 mA VOL 1400 UNIT 2000 TLC08XC IOH = - 20 mA High-level output voltage 1900 TLC08XC IOH = - 1 mA VOH 390 1.2 TLC08XI VICR MAX Full range 25C IIO TYP V 0.7 -40C to 85C 0.7 Sourcing 25C 100 Sinking 25C 100 VOH = 1.5 V from positive rail VOL = 0.5 V from negative rail 25C 57 25C 55 mA mA Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. WWW.TI.COM 5 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS AVD Large-signal differential voltage amplification ri(d) Differential input resistance CIC Common-mode input capacitance f = 10 kHz zo Closed-loop output impedance f = 10 kHz, VO(PP) = 3 V, RL = 10 k AV = 10 CMRR Common-mode rejection ratio VIC = 0 to 3 V, RS = 50 kSVR Supply voltage rejection ratio (VDD /VIO) VDD = 4.5 V to 16 V, No load VIC = VDD /2, IDD Supply current (per channel) VO = 2.5 V, No load IDD(SHDN) Supply current in shutdown mode (per channel) (TLC080, TLC083, TLC085) SHDN 0.8 V TA MIN TYP 25C 100 120 Full range 100 dB 1000 G 25C 22.9 pF 0.25 25C 25C 80 Full range 80 25C 80 Full range 80 25C 110 dB 100 dB 1.8 Full range 25C WWW.TI.COM UNIT 25C Full range Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. 6 MAX 2.5 3.5 125 mA 200 250 A A SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS SR+ Positive slew rate at unity gain VO(PP) = 0.8 V, RL = 10 k CL = 50 pF, SR- Negative slew rate at unity gain VO(PP) = 0.8 V, RL = 10 k CL = 50 pF, Vn Equivalent input noise voltage In TA 25C MIN TYP 10 16 Full range 9.5 25C 12.5 Full range 19 V/ s V/s 10 25C 12 f = 1 kHz 25C 8.5 Equivalent input noise current f = 1 kHz 25C 0.6 THD + N Total harmonic distortion plus noise VO(PP) = 3 V, RL = 10 k and 250 , f = 1 kHz t(on) t(off) Amplifier turnon time Amplifier turnoff time RL = 10 k Gain-bandwidth product f = 10 kHz, RL = 10 k V(STEP)PP = 1 V, AV = -1, CL = 10 pF, RL = 10 k 0.1% V(STEP)PP = 1 V, AV = -1, CL = 47 pF, RL = 10 k 0.1% 0.18 0.01% 0.39 RL = 10 k, CL = 50 pF RL = 10 k, CL = 0 pF RL = 10 k, CL = 50 pF RL = 10 k, CL = 0 pF ts m Settling time Phase margin Gain margin UNIT V/ s V/s f = 100 Hz AV = 1 AV = 10 MAX nV/Hz fA /Hz 0.002% 25C 25 C AV = 100 0.012% 0.085% 25C 0.15 s 25C 1.3 s 25C 10 MHz 0.18 0.01% 0.39 ss 25C 32 25C 40 2.2 25C 3.3 dB Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. WWW.TI.COM 7 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) PARAMETER VIO Input offset voltage VIO Temperature coefficient of input offset voltage TEST CONDITIONS VDD = 12 V VIC = 6 V, VO = 6 V, RS = 50 TLC0841/2/3, TLC084/5 TLC0841/2/3A, TLC084/5A TA 25C MIN IIB Input offset current Input bias current Common-mode input voltage VDD = 12 V VIC = 6 V, VO = 6 V, RS = 50 TLC08xI 3000 25C 390 Full range IOH = - 35 mA 2 Full range 0 to 10.0 0 to 10.5 Full range 0 to 10.0 0 to 10.5 25C 11.1 11.2 10.8 Full range 10.7 25C 10.6 Full range 10.3 25C 10.3 -40C to 85C 10.2 Full range IOL = 20 mA Full range 25C IOL = 35 mA IOS Short-circuit output current IO Output current 10.5 0.17 0.25 0.35 0.35 0.45 0.4 0.52 0.5 V 0.6 0.45 0.6 0.65 Sourcing 25C 150 Sinking 25C 150 VOH = 1.5 V from positive rail VOL = 0.5 V from negative rail 25C 57 25C 55 WWW.TI.COM V 10.7 -40C to 85C Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. 8 V 11 Full range 25C IOL = 50 mA pA 11 25C 25C VIC = 6 V 50 700 25C IOL = 1 mA pA 700 25C Low-level output voltage 50 100 Full range V V V/C V/C 100 Full range RS = 50 VIC = 6 V 1.5 25C IOH = - 50 mA VOL 1400 UNIT 2000 TLC08xC IOH = - 20 mA High-level output voltage 1900 TLC08xC IOH = - 1 mA VOH 390 1.2 TLC08xI VICR MAX Full range 25C IIO TYP mA mA SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 electrical characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS AVD Large-signal differential voltage amplification ri(d) Differential input resistance CIC Common-mode input capacitance f = 10 kHz zo Closed-loop output impedance f = 10 kHz, VO(PP) = 8 V, RL = 10 k AV = 10 CMRR Common-mode rejection ratio VIC = 0 to 10 V, RS = 50 kSVR Supply voltage rejection ratio (VDD /VIO) VDD = 4.5 V to 16 V, No load VIC = VDD /2, IDD Supply current (per channel) VO = 7.5 V, No load IDD(SHDN) Supply current in shutdown mode (TLC080, TLC083, TLC085) (per channel) SHDN 0.8 V TA MIN TYP 25C 120 140 Full range 120 MAX UNIT dB 25C 1000 G 25C 21.6 pF 0.25 25C 25C 80 Full range 80 25C 80 Full range 80 25C 110 dB 100 dB 1.9 Full range 25C Full range 2.9 3.5 125 mA 200 250 A A Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. WWW.TI.COM 9 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 operating characteristics at specified free-air temperature, VDD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS SR+ Positive slew rate at unity gain VO(PP) = 2 V, RL = 10 k CL = 50 pF, SR- Negative slew rate at unity gain VO(PP) = 2 V, RL = 10 k CL = 50 pF, Vn Equivalent input noise voltage In TA 25C MIN TYP 10 16 Full range 9.5 25C 12.5 Full range 19 V/ s V/s 10 25C 14 f = 1 kHz 25C 8.5 Equivalent input noise current f = 1 kHz 25C 0.6 THD + N Total harmonic distortion plus noise VO(PP) = 8 V, RL = 10 k and 250 , f = 1 kHz t(on) t(off) Amplifier turnon time Amplifier turnoff time RL = 10 k Gain-bandwidth product f = 10 kHz, RL = 10 k V(STEP)PP = 1 V, AV = -1, CL = 10 pF, RL = 10 k 0.1% V(STEP)PP = 1 V, AV = -1, CL = 47 pF, RL = 10 k 0.1% 0.17 0.01% 0.29 RL = 10 k, CL = 50 pF RL = 10 k, CL = 0 pF RL = 10 k, CL = 50 pF RL = 10 k, CL = 0 pF ts m Settling time Phase margin Gain margin UNIT V/ s V/s f = 100 Hz AV = 1 AV = 10 MAX nV/Hz fA /Hz 0.002% 25C 25 C AV = 100 0.005% 0.022% 25C 0.47 s 25C 2.5 s 25C 10 MHz 0.17 0.01% 0.22 ss 25C 37 25C 42 3.1 25C 4 dB Full range is 0C to 70C for C suffix and - 40C to 125C for I suffix. If not specified, full range is - 40C to 125C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. 10 WWW.TI.COM SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO IIO Input offset voltage vs Common-mode input voltage 1, 2 Input offset current vs Free-air temperature 3, 4 IIB VOH Input bias current vs Free-air temperature 3, 4 High-level output voltage vs High-level output current 5, 7 VOL Zo Low-level output voltage vs Low-level output current 6, 8 Output impedance vs Frequency 9 IDD PSRR Supply current vs Supply voltage 10 Power supply rejection ratio vs Frequency 11 CMRR Common-mode rejection ratio vs Frequency 12 Vn VO(PP) Equivalent input noise voltage vs Frequency 13 Peak-to-peak output voltage vs Frequency 14, 15 Crosstalk vs Frequency 16 Differential voltage gain vs Frequency 17, 18 Phase vs Frequency 17, 18 Phase margin vs Load capacitance 19, 20 Gain margin vs Load capacitance 21, 22 Gain-bandwidth product vs Supply voltage SR Slew rate vs Supply voltage vs Free-air temperature 24 25, 26 vs Frequency 27, 28 THD + N Total harmonic distortion plus noise vs Peak-to-peak output voltage 29, 30 m 23 Large-signal follower pulse response 31, 32 Small-signal follower pulse response 33 Large-signal inverting pulse response 34, 35 Small-signal inverting pulse response 36 Shutdown forward isolation vs Frequency 37, 38 Shutdown reverse isolation vs Frequency 39, 40 vs Supply voltage Shutdown supply current vs Free-air temperature Shutdown pulse 41 42 43, 44 WWW.TI.COM 11 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 1500 VDD = 5 V TA = 25 C VDD = 12 V TA = 25 C 1300 600 400 200 0 -200 -400 1100 900 700 500 300 100 -100 -300 -600 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -500 0 VICR - Common-Mode Input Voltage - V 1 2 3 4 8 9 10 11 12 IIO -20 -40 -60 -80 -100 IIB -120 VDD = 12 V -140 IIO -100 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 4.5 TA = 70C TA = 25C 4.0 TA = -40C 3.5 TA = 125C 3.0 2.5 11.0 TA = -40C TA = 25C 10.0 9.5 VDD = 12 V 9.0 0.8 0.7 TA = 125C 0.6 TA = 70C TA = 25C 0.5 0.4 0.3 TA = -40C 0.2 0.1 5 10 15 20 25 30 35 40 45 50 IOH - High-Level Output Current - mA 0 5 10 15 20 25 30 35 40 45 50 IOL - Low-Level Output Current - mA Figure 5 Figure 6 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT OUTPUT IMPEDANCE vs FREQUENCY 1000 0.9 0.8 TA = 125C 0.7 TA = 70C 0.6 TA = 25C 0.5 0.4 0.3 TA = -40C 0.2 0.1 100 VDD = 5 V and 12 V TA = 25C 10 AV = 100 1 AV = 1 0.10 AV = 10 VDD = 12 V 0.0 10 15 20 25 30 35 40 45 50 IOH - High-Level Output Current - mA VDD = 5 V 0.9 0.0 0 VOL - Low-Level Output Voltage - V TA = 125C TA = 70C LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.0 1.0 Figure 7 0 -50 TA - Free-Air Temperature - C 2.0 12.0 5 IIB 50 Figure 3 VDD = 5 V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 0 100 5.0 -160 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 10.5 150 VOL - Low-Level Output Voltage - V 0 11.5 200 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT V OH - High-Level Output Voltage - V I IB / I IO - Input Bias and Input Offset Current - pA INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE Figure 4 V OH - High-Level Output Voltage - V 7 VDD = 5 V 250 Figure 2 TA - Free-Air Temperature - C 12 6 300 VICR - Common-Mode Input Voltage - V Figure 1 20 5 Z o - Output Impedance - 800 V IO - Input Offset Voltage - V V IO - Input Offset Voltage - V 1000 INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE I IB / I IO - Input Bias and Input Offset Current - pA INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 5 10 15 20 25 30 35 40 45 50 IOL - Low-Level Output Current - mA Figure 8 WWW.TI.COM 0.01 100 1k 100k 10k f - Frequency - Hz Figure 9 1M 10M SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE TA = 25C 1.8 TA = 125C 1.6 TA = 70C 1.4 AV = 1 SHDN = VDD Per Channel 1.2 1.0 4 5 6 140 120 VDD = 12 V 100 80 60 40 VDD = 5 V 20 0 7 8 9 10 11 12 13 14 15 VDD - Supply Voltage - V 0 10 V O(PP) - Peak-to-Peak Output Voltage - V 25 20 VDD = 12 V 10 VDD = 5 V 5 0 10 100 1k 1M 10M 100 80 60 40 20 0 100 10k VDD = 12 V 8 6 VDD = 5 V 4 THD+N < = 5% RL = 600 TA = 25C 2 0 100k 10k 100k 1M f - Frequency - Hz f - Frequency - Hz Figure 13 10k 100k f - Frequency - Hz 1M 10M PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 12 10 1k Figure 12 PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 10M Figure 14 12 10 VDD = 12 V 8 6 VDD = 5 V 4 2 0 10k THD+N < = 5% RL= 10 k TA = 25C 100k 1M f - Frequency - Hz 10M Figure 15 CROSSTALK vs FREQUENCY 0 -20 -40 Crosstalk - dB Hz V n - Equivalent Input Noise Voltage - nV/ 30 15 100k VDD = 5 V and 12 V TA = 25C 120 Figure 11 EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 35 10k 140 f - Frequency - Hz Figure 10 40 1k 100 V O(PP) - Peak-to-Peak Output Voltage - V I DD - Supply Current - mA TA = -40C 2.0 CMRR - Common-Mode Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB 2.4 2.2 COMMON-MODE REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY VDD = 5 V and 12 V AV = 1 RL = 10 k VI(PP) = 2 V For All Channels -60 -80 -100 -120 -140 -160 10 100 1k 10k 100k f - Frequency - Hz Figure 16 WWW.TI.COM 13 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY 80 80 60 Gain A VD - Different Voltage Gain - dB 70 -45 50 Phase 40 -90 30 20 -135 10 0 -10 -20 1k VDD = 2.5 V RL = 10 k CL = 0 pF TA = 25C 10k 100k -180 1M 70 Gain 60 Phase 40 20 -135 10 0 -10 VDD = 6 V RL = 10 k CL = 0 pF TA = 25C 10k PHASE MARGIN vs LOAD CAPACITANCE 40 25 Rnull = 50 Rnull = 20 VDD = 5 V RL = 10 k TA = 25C 30 Rnull = 100 25 Rnull = 20 15 VDD = 12 V RL = 10 k TA = 25C 10 5 0 10 Rnull = 50 1.5 1 VDD = 5 V RL = 10 k TA = 25C Rnull = 20 0 10 100 100 CL - Load Capacitance - pF Figure 19 Figure 20 Figure 21 GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 3.5 3 Rnull = 50 Rnull = 20 1.5 VDD = 12 V RL = 10 k TA = 25C 0 10 100 CL - Load Capacitance - pF Figure 22 22 CL = 11 pF 9.9 9.8 9.7 RL = 10 k 9.6 9.5 9.4 RL = 600 9.3 20 RL = 600 and 10 k CL = 50 pF AV = 1 19 Slew Rate - 21 TA = 25C SR - Slew Rate - V/ s GBWP - Gain Bandwidth Product - MHz Rnull = 100 2 SLEW RATE vs SUPPLY VOLTAGE 10.0 Rnull = 0 4 m - Phase Margin - dB 2 CL - Load Capacitance - pF 5 0.5 2.5 CL - Load Capacitance - pF 4.5 1 Rnull = 100 3 0.5 0 10 100 GAIN MARGIN vs LOAD CAPACITANCE 2.5 Rnull = 50 20 Rnull = 0 3.5 G - Gain Margin - dB m - Phase Margin m - Phase Margin 4 Rnull = 0 35 5 14 GAIN MARGIN vs LOAD CAPACITANCE 45 30 10 -225 100M 10M Figure 18 Rnull = 0 Rnull = 100 15 1M f - Frequency - Hz PHASE MARGIN vs LOAD CAPACITANCE 20 -180 100k Figure 17 35 -90 30 f - Frequency - Hz 40 -45 50 -20 1k -225 100M 10M 0 Phase - 0 Phase - A VD - Different Voltage Gain - dB TYPICAL CHARACTERISTICS 18 17 16 9.2 14 9.1 13 9.0 Slew Rate + 15 12 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD - Supply Voltage - V Figure 23 WWW.TI.COM 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD - Supply Voltage - V Figure 24 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS SLEW RATE vs FREE-AIR TEMPERATURE Slew Rate - 20 SR - Slew Rate - V/ s 15 Slew Rate + 10 15 Slew Rate + 10 VDD = 12 V RL= 600 and 10 k CL = 50 pF AV = 1 5 5 0 -55 -35 -15 5 25 45 65 85 105 125 TA - Free-Air Temperature - C 0 -55 -35 -15 5 25 45 65 85 105 125 TA - Free-Air Temperature - C Figure 25 0.1 Total Harmonic Distortion + Noise - % VDD = 12 V VO(PP) = 8 V RL = 10 k AV = 100 0.01 AV = 10 AV = 1 10k 1k AV = 1 0.001 100 100k 10k 1k 100k f - Frequency - Hz Figure 27 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE 10 10 VDD = 5 V AV = 1 f = 1 kHz 1 RL = 250 0.1 RL = 600 0.01 RL = 10 k 0.001 0.0001 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 VDD = 12 V AV = 1 f = 1 kHz 1 RL = 250 0.1 RL = 600 0.01 0.001 RL = 10 k 0.0001 0.5 2.5 4.5 6.5 8.5 10.5 VO(PP) - Peak-to-Peak Output Voltage - V VO(PP) - Peak-to-Peak Output Voltage - V Figure 28 Figure 29 Figure 30 LARGE SIGNAL FOLLOWER PULSE RESPONSE LARGE SIGNAL FOLLOWER PULSE RESPONSE SMALL SIGNAL FOLLOWER PULSE RESPONSE VI (1 V/Div) VI (5 V/Div) VO (500 mV/Div) VDD = 5 V RL = 600 and 10 k CL = 8 pF TA = 25C 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VO (2 V/Div) VDD = 12 V RL = 600 and 10 k CL = 8 pF TA = 25C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t - Time - s t - Time - s Figure 31 Figure 32 WWW.TI.COM VI(100mV/Div) V O - Output Voltage - V V O - Output Voltage - V V O - Output Voltage - V AV = 10 0.01 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE f - Frequency - Hz 0 AV = 100 0.1 Figure 26 TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 0.001 100 VDD = 5 V VO(PP) = 2 V RL = 10 k Total Harmonic Distortion + Noise - % Slew Rate - 20 SR - Slew Rate - V/ s 1 25 VDD = 5 V RL= 600 and 10 k CL = 50 pF AV = 1 Total Harmonic Distortion + Noise - % 25 Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY SLEW RATE vs FREE-AIR TEMPERATURE 2 VO(50mV/Div) VDD = 5 V and 12 V RL = 600 and 10 k CL = 8 pF TA = 25C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10 t - Time - s Figure 33 15 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS LARGE SIGNAL INVERTING PULSE RESPONSE LARGE SIGNAL INVERTING PULSE RESPONSE VI (5 V/div) VDD = 5 V RL = 600 and 10 k CL = 8 pF TA = 25C VI (100 mV/div) V O - Output Voltage - V V O - Output Voltage - V VI (2 V/div) V O - Output Voltage - V SMALL SIGNAL INVERTING PULSE RESPONSE VDD = 12 V RL = 600 and 10 k CL = 8 pF TA = 25C VDD = 5 V and 12 V RL = 600 and 10 k CL = 8 pF TA = 25C VO (50 mV/Div) VO (2 V/Div) VO (500 mV/Div) 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 2 0.2 0.4 0.6 0.8 Figure 35 Figure 36 SHUTDOWN FORWARD ISOLATION vs FREQUENCY 100 RL = 600 80 60 RL = 10 k 40 140 VDD = 12 V CL= 0 pF TA = 25C VI(PP) = 0.1, 8, 12 V 120 100 80 RL = 600 60 RL = 10 k 40 20 10k 100k 1M f - Frequency - Hz 10M I DD(SHDN) - Shutdown Supply Current - A VDD = 12 V CL= 0 pF TA = 25C VI(PP) = 0.1, 8, 12 V 100 RL = 600 60 RL = 10 k 40 20 1k 10k 100k 1M f - Frequency - Hz Figure 40 80 RL = 600 60 RL = 10 k 40 1k 10k 100k 1M f - Frequency - Hz 10M 100 100M 10M 100M 136 Shutdown On RL = open VIN = VDD/2 134 132 130 128 126 124 122 120 118 4 5 6 7 8 9 10 11 12 13 14 15 16 VDD - Supply Voltage - V Figure 41 WWW.TI.COM 1k 10k 100k 1M f - Frequency - Hz 10M 100M Figure 39 SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE 140 80 100 Figure 38 SHUTDOWN REVERSE ISOLATION vs FREQUENCY 120 VDD = 5 V CL= 0 pF TA = 25C VI(PP) = 0.1, 2.5, and 5 V 120 20 100 100M Figure 37 Sutdown Reverse Isolation - dB Sutdown Reverse Isolation - dB Sutdown Forward Isolation - dB Sutdown Forward Isolation - dB 120 1 SHUTDOWN REVERSE ISOLATION vs FREQUENCY 140 VDD = 5 V CL= 0 pF TA = 25C VI(PP) = 0.1, 2.5, and 5 V 1k 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Figure 34 20 16 0 2 t - Time - s 140 100 1.2 1.4 1.6 1.8 t - Time - s SHUTDOWN FORWARD ISOLATION vs FREQUENCY 100 1 t - Time - s SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE I DD(SHDN) - Shutdown Supply Current - A 0 180 AV = 1 VIN = VDD/2 160 140 VDD = 12 V 120 VDD = 5 V 100 80 60 -55 -25 5 35 65 95 TA - Free-Air Temperature - C Figure 42 125 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 TYPICAL CHARACTERISTICS SHUTDOWN PULSE SHUTDOWN PULSE 5.5 4 Shutdown Pulse I DD - Supply Current - mA 5.0 4.5 4.0 2 VDD = 5 V CL= 8 pF TA = 25C 3.5 3.0 2.5 0 IDD RL = 10 k 2.0 1.5 -2 IDD RL = 600 1.0 6 5.5 SD Off Shutdown Pulse - V I DD - Supply Current - mA 6.0 6 -4 SD Off 5.0 4 Shutdown Pulse 4.5 4.0 2 VDD = 12 V CL= 8 pF TA = 25C 3.5 3.0 2.5 0 IDD RL = 10 k 2.0 1.5 -2 IDD RL = 600 1.0 Shutdown Pulse - V 6.0 -4 0.5 0.5 0.0 0.0 -6 0 10 20 30 40 50 t - Time - s 60 70 -6 0 80 10 20 30 40 50 t - Time - s 60 70 80 Figure 44 Figure 43 PARAMETER MEASUREMENT INFORMATION Rnull _ + RL CL Figure 45 APPLICATION INFORMATION input offset voltage null circuit The TLC080 and TLC081 has an input offset nulling function. Refer to Figure 46 for the diagram. - IN - OUT + IN + N2 N1 100 k R1 VDD - NOTE A: R1 = 5.6 k for offset voltage adjustment of 10 mV. R1 = 20 k for offset voltage adjustment of 3 mV. Figure 46. Input Offset Voltage Null Circuit WWW.TI.COM 17 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 47. A minimum value of 20 should work well for most applications. RF RG RNULL _ Input Output + CLOAD Figure 47. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB- RG + - VI IIB+ V OO +V IO 1) R R F G VO + RS "I IB) R S 1) R R F G "I IB- Figure 48. Output Offset Voltage Model 18 WWW.TI.COM R F SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION high speed CMOS input amplifiers The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of -10, a source resistance of 1 k, and a feedback resistance of 10 k add an additional pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance. This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at frequencies where there is on the order of 5dB gain left and the phase shift adds considerably. The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the feedback resistance is increased, the gain peaking increases at a lower frequency and the 180_ phase shift crossover point also moves down in frequency, decreasing the phase margin. For the TLC08x, the maximum feedback resistor recommended is 5 k; larger resistances can be used but a capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance pole. The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when configured as a unity gain buffer and with a 10-k feedback resistor. By adding a 10-pF capacitor in parallel with the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only. 2 VIN V O - Output Voltage - V 1 0 With CF = 10 pF 1.5 -1 V I - Input Voltage - V Load capacitance had little effect on these measurements due to the excellent output drive capability of the TLC08x. 10 pF 10 k _ 1 + IN 0.5 VOUT 0 VDD = 5 V AV = +1 RF = 10 k RL = 600 CL = 22 pF 50 600 22 pF -0.5 0 0.2 0.4 0.6 0.8 t - Time - s 1 1.2 1.4 1.6 Figure 49. 1-V Step Response WWW.TI.COM 19 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 50). RG RF - VO + VI R1 C1 f V O + V I 1) R R F G -3dB + 1 2pR1C1 1 1 ) sR1C1 Figure 50. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF RG = Figure 51. 2-Pole Low-Pass Sallen-Key Filter 20 WWW.TI.COM -3dB + ( 1 2pRC RF 1 2- Q ) SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION shutdown function Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 125 A/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to be pulled to VDD- (not system ground) to disable the operational amplifier. The amplifier's output with a shutdown pulse is shown in Figures 43 and 44. The amplifier is powered with a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figures 37, 38, 39, and 40 show the amplifier's forward and reverse isolation in shutdown. The operational amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using 0.1 VPP, 2.5 VPP, and 5 VPP input signals at 2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals at 6 V supplies. circuit layout considerations To achieve the levels of high performance of the TLC08x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling - Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets - Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements - Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components - Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. WWW.TI.COM 21 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION general PowerPAD design considerations The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE B: The thermal pad is electrically isolated from all terminals in the package. Figure 52. Views of Thermally Enhanced DGN Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. Thermal Pad Area Quad Single or Dual 68 mils x 70 mils with 5 vias (Via diameter = 13 mils) Figure 53. PowerPAD PCB Etch and Via Pattern 22 WWW.TI.COM 78 mils x 94 mils with 9 vias (Via diameter = 13 mils) SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION general PowerPAD design considerations (continued) 1. Prepare the PCB with a top side etch pattern as shown in Figure 53. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given JA, the maximum power dissipation is shown in Figure 54 and is calculated by the following formula: P Where: D + T -T MAX A q JA PD = Maximum power dissipation of TLC08x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) WWW.TI.COM 23 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION general PowerPAD design considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE Maximum Power Dissipation - W 7 6 5 4 3 2 PWP Package Low-K Test PCB JA = 29.7C/W TJ = 150C SOT-23 Package Low-K Test PCB JA = 324C/W DGN Package Low-K Test PCB JA = 52.3C/W SOIC Package Low-K Test PCB JA = 176C/W PDIP Package Low-K Test PCB JA = 104C/W 1 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 54. Maximum Power Dissipation vs Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, JA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. 24 WWW.TI.COM SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts, the model generation software used with Microsim PSpice. The Boyle macromodel (see Note 1) and subcircuit in Figure 55 are generated using the TLC08x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D D D D D D Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification D D D D D D Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). PSpice and Parts are trademarks of MicroSim Corporation. WWW.TI.COM 25 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 APPLICATION INFORMATION 99 3 VDD 9 RSS 92 FB + 10 J1 DP VC J2 IN + 11 VAD DC 12 C1 RD1 R2 - 53 HLIM - C2 6 - + + GA GCM VLIM 8 - - RO1 DE 5 + VE OUT *DEVICE=TLC08X_5V, OPAMP, PJF, INT * TLC08X_5V - 5V operational amplifier "macromodel" subcircuit * created using Parts release 8.0 on 12/16/99 at 14:03 * Parts is a MicroSim product. * * connections: non-inverting input * inverting input * positive power supply * negative power supply * output * .subckt TLC08X_5V 1 2 3 4 5 * c1 11 12 4.6015E-12 c2 6 7 8.0000E-12 css 10 99 986.29E-15 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 13.984E6 -1E3 1E3 14E6 -14E6 ga gcm ioff iss hlim j1 j2 r2 rd1 rd2 ro1 ro2 rp rss vb vc ve vlim vlp vln .model .model .model .model .ends 6 0 0 3 90 11 12 6 4 4 8 7 3 10 9 3 54 7 91 0 dx dy jx1 jx2 0 11 12 402.12E-6 6 10 99 1.5735E-6 6 dc 1.212E-6 10 dc 130.40E-6 0 vlim 1K 2 10 jx1 1 10 jx2 9 100.00E3 11 2.4868E3 12 2.4868E3 5 10 99 10 4 2.8249E3 99 1.5337E6 0 dc 0 53 dc 1.5537 4 dc .84373 8 dc 0 0 dc 117.60 92 dc 117.60 D(Is=800.00E-18) D(Is=800.00E-18 Rs=1m Cjo=10p) PJF(Is=80.000E-15 Beta=1.2401E-3 Vto=-1) PJF(Is=80.000E-15 Beta=1.2401E-3 Vto=-1) Figure 55. Boyle Macromodel and Subcircuit 26 - RD2 54 4 - 7 60 + - + DLP 91 + VLP 90 RO2 VB IN - GND - + ISS RP 2 1 DLN EGND + WWW.TI.COM VLN SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC SMALL-OUTLINE DGQ (S-PDSO-G10) WWW.TI.COM 27 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC SMALL-OUTLINE DGN (S-PDSO-G8) Top View 8 5 Exposed Pad 1,73 MAX 1 4 1,78 MAX Not to Scale PPTD041 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002 and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com. PowerPAD is a trademark of Texas Instruments 28 WWW.TI.COM SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC SMALL-OUTLINE PWP (R-PDSO-G14) PPTD023 WWW.TI.COM 29 SLOS254D - JUNE 1999 - REVISED FEBRUARY 2004 THERMAL PAD MECHANICAL DATA PowerPADt PLASTIC SMALL-OUTLINE PWP (R-PDSO-G16) PPTD024 30 WWW.TI.COM MECHANICAL DATA MPDI001A - JANUARY 1995 - REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC080AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080AIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC080AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC080CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC080CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC080ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC080IP ACTIVE PDIP P 8 CU NIPDAU Level-NC-NC-NC 50 Addendum-Page 1 Pb-Free Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC080IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC081AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC081AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC081CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDGNG4 ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC081CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC081ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC081IP ACTIVE PDIP P 8 CU NIPDAU Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) (RoHS) 50 Addendum-Page 2 Pb-Free PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC081IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IDGN ACTIVE MSOPPower PAD DGN 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IDGNR ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IDGNRG4 ACTIVE MSOPPower PAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC082IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC082IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU Level-NC-NC-NC Lead/Ball Finish MSL Peak Temp (3) (RoHS) Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC083AID ACTIVE SOIC D 14 TLC083AIDR ACTIVE SOIC D TLC083AIDRG4 ACTIVE SOIC TLC083AIN ACTIVE TLC083AINE4 Lead/Ball Finish MSL Peak Temp (3) (RoHS) 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC083CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDGQ ACTIVE MSOPPower PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDGQG4 ACTIVE MSOPPower PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDGQR ACTIVE MSOPPower PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDGQRG4 ACTIVE MSOPPower PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC083CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC083ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IDGQ ACTIVE MSOPPower PAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IDGQR ACTIVE MSOPPower PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IDGQRG4 ACTIVE MSOPPower PAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC083IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC083INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC084AID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084AIDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084AIDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084AIPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084CD ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084CPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084ID ACTIVE SOIC D 14 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC084IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPD Level-NC-NC-NC TLC084IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084IPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC084IPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085AID ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085AIDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 50 50 40 Addendum-Page 5 Lead/Ball Finish MSL Peak Temp (3) PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC085AIN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085AINE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085AIPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085AIPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085CD ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC085IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC085IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085IPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085IPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLC085IPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 40 (1) Lead/Ball Finish MSL Peak Temp (3) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 6 PACKAGE OPTION ADDENDUM www.ti.com 13-Sep-2005 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 7 MECHANICAL DATA MPDI001A - JANUARY 1995 - REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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