FUNCTIONAL BLOCK DIAGRAM
CS
CLK
SDI
SHDN
AD8802/AD8804
D7
D0
ADDR
DEC
EN
D11
D10
D9
D8
D7
SER
REG
DD0
DAC
REG
#1
R
V
DD
D7
D0
DAC
12
DAC
REG
#12
R
DAC
1
8
O1
O2
O4
O5
O6
O7
O8
O9
O10
O11
O12
V
REFH
GND RS
(AD8802 ONLY) V
REFL
(AD8804 ONLY)
O3
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
12 Channel, 8-Bit TrimDACs
with Power Shutdown
AD8802/AD8804
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
GENERAL DESCRIPTION
The 12-channel AD8802/AD8804 provides independent digitally-
controllable voltage outputs in a compact 20-lead package. This
potentiometer divider TrimDAC® allows replacement of the
mechanical trimmer function in new designs. The AD8802/
AD8804 is ideal for dc voltage adjustment applications.
Easily programmed by serial interfaced microcontroller ports,
the AD8802 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Appli-
cations such as gain control of video amplifiers, voltage con-
trolled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT com-
puter graphic displays are a few of the many applications ideally
suited for these parts. The AD8804 provides independent con-
trol of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
V
REFL
pin. This is helpful for maximizing the resolution of
devices with a limited allowable voltage control range.
Internally the AD8802/AD8804 contains 12 voltage-output
digital-to-analog converters, sharing a common reference-
voltage input.
TrimDAC is a registered trademark of Analog Devices, Inc.
FEATURES
Low Cost
Replaces 12 Potentiometers
Individually Programmable Outputs
3-Wire SPI Compatible Serial Input
Power Shutdown <55 mWatts Including IDD & IREF
Midscale Preset, AD8802
Separate VREFL Range Setting, AD8804
+3 V to +5 V Single Supply Operation
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
Each DAC has its own DAC latch that holds its output state.
These DAC latches are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire
serial input digital interface. The serial-data-input word is
decoded where the first 4 bits determine the address of the DAC
latches to be loaded with the last 8 bits of data. The AD8802/
AD8804 consumes only 10 µA from 5 V power supplies. In ad-
dition, in shutdown mode reference input current consumption
is also reduced to 10 µA while saving the DAC latch settings for
use after return to normal operation.
The AD8802/AD8804 is available in the 20-pin plastic DIP, the
SOIC-20 surface mount package, and the 1 mm thin TSSOP-20
package.
Parameter Symbol Conditions Min Typ
1
Max Units
STATIC ACCURACY
Specifications apply to all DACs
Resolution N 8 Bits
Differential Nonlinearity Error DNL Guaranteed Monotonic –1 ±1/4 +1 LSB
Integral Nonlinearity Error INL –1.5 ±1/2 +1.5 LSB
Full-Scale Error G
FSE
–1 1/2 +1 LSB
Zero Code Error V
ZSE
–1 1/4 +1 LSB
DAC Output Resistance R
OUT
35 8 kΩ
Output Resistance Match ∆R/R
O
1.5 %
REFERENCE INPUT
Voltage Range
2
V
REFH
0V
DD
V
V
REFL
Pin Available on AD8804 Only 0 V
DD
V
REFH Input Resistance R
REFH
Digital Inputs = 55
H
, V
REFH
= V
DD
1.2 kΩ
REFL Input Resistance
3
R
REFL
Digital Inputs = 55
H
, V
REFL
= V
DD
1.2 kΩ
Reference Input Capacitance
3
C
REF0
Digital Inputs all Zeros 32 pF
C
REF1
Digital Inputs all Ones 32 pF
DIGITAL INPUTS
Logic High V
IH
V
DD
= +5 V 2.4 V
Logic Low V
IL
V
DD
= +5 V 0.8 V
Logic High V
IH
V
DD
= +3 V 2.1 V
Logic Low V
IL
V
DD
= +3 V 0.6 V
Input Current I
IL
V
IN
= 0 V or + 5 V ±1µA
Input Capacitance
3
C
IL
5pF
POWER SUPPLIES
4
Power Supply Range V
DD
Range 2.7 5.5 V
Supply Current (CMOS) I
DD
V
IH
= V
DD
or V
IL
= 0 V 0.01 10 µA
Supply Current (TTL) I
DD
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V 1 4 mA
Shutdown Current I
REFH
SHDN = 0 0.2 10 µA
Power Dissipation P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V 55 µW
Power Supply Sensitivity PSRR V
DD
= +5 V ± 10% 0.001 0.002 %/%
DYNAMIC PERFORMANCE
3
V
OUT
Settling Time t
S
±1/2 LSB Error Band 0.6 µs
Crosstalk CT Between Adjacent Outputs
5
50 dB
SWITCHING CHARACTERISTICS
3, 6
Input Clock Pulse Width t
CH
, t
CL
Clock Level High or Low 15 ns
Data Setup Time t
DS
5ns
Data Hold Time t
DH
5ns
CS Setup Time t
CSS
10 ns
CS High Pulse Width t
CSW
10 ns
Reset Pulse Width t
RS
90 ns
CLK Rise to CS Rise Hold Time t
CSH
20 ns
CS Rise to Clock Rise Setup t
CS1
10 ns
NOTES
1
Typicals represent average readings at +25°C.
2
V
REFH
can be any value between GND and V
DD
, for the AD8804 V
REFL
can be any value between GND and V
DD
.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages V
IN
= 0 V or V
DD
for CMOS condition. DAC outputs unloaded. P
DISS
is calculated from (I
DD
× V
DD
).
5
Measured at a V
OUT
pin where an adjacent V
OUT
pin is making a full-scale voltage change (f = 100 kHz).
6
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage level of
1.6 V.
Specifications subject to change without notice.
AD8802/AD8804–SPECIFICATIONS
REV. 0
–2–
(VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C
≤TA ≤ +858C unless otherwise noted)
AD8802/AD8804
REV. 0 –3–
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, + 8 V
V
REFX
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (T
J
MAX – T
A
)/θ
JA
Thermal Resistance θ
JA,
SOIC (SOL-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
TSSOP-20 (RU-20) . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
AD8802 PIN DESCRIPTIONS
Pin Name Description
1V
REF
Common DAC Reference Input
2 O1 DAC Output #1, addr = 0000
2
3 O2 DAC Output #2, addr = 0001
2
4 O3 DAC Output #3, addr = 0010
2
5 O4 DAC Output #4, addr = 0011
2
6 O5 DAC Output #5, addr = 0100
2
7 O6 DAC Output #6, addr = 0101
2
8SHDN Reference input current goes to zero. DAC
latch settings maintained
9CS Chip Select Input, Active Low. When CS
returns high, data in the serial input register is
decoded based on the address bits and loaded
into the target DAC register
10 GND Ground
11 CLK Serial Clock Input, Positive Edge Triggered
12 SDI Serial Data Input
13 O7 DAC Output #7, addr = 0110
2
14 O8 DAC Output #8, addr = 0111
2
15 O9 DAC Output #9, addr = 1000
2
16 O10 DAC Output #10, addr = 1001
2
17 O11 DAC Output #11, addr = 1010
2
18 O12 DAC Output #12, addr = 1011
2
19 RS Asynchronous Preset to Midscale Output
Setting. Loads all DAC Registers with 80
H
20 V
DD
Positive Power Supply, Specified for Operation
at Both +3 V and +5 V
PIN CONFIGURATIONS
14
13
12
11
17
16
15
20
19
18
9
8
1
2
3
4
7
6
5
10
O10
O11
O12
VDD
O7
O8
O9
VREFL
CLK
SDI
VREFH
O1
O2
O3
O4
O5
O6
SHDN
CS
GND
TOP VIEW
(Not to Scale)
AD8804
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
VREFH
O11
O12
RS
VDD
O1
O2
O3
AD8802
O8
O9
O10
O4
O5
O6
SHDN
CS
GND CLK
SDI
O7
AD8804 PIN DESCRIPTIONS
Pin Name Description
1V
REFH
Common High-Side DAC Reference Input
2 O1 DAC Output #1, addr = 0000
2
3 O2 DAC Output #2, addr = 0001
2
4 O3 DAC Output #3, addr = 0010
2
5 O4 DAC Output #4, addr = 0011
2
6 O5 DAC Output #5, addr = 0100
2
7 O6 DAC Output #6, addr = 0101
2
8SHDN Reference input current goes to zero DAC latch
settings maintained
9CS Chip Select Input, Active Low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded input the
target DAC register
10 GND Ground
11 V
REFL
Common Low-Side DAC Reference Input
12 CLK Serial Clock Input, Positive Edge Triggered
13 SDI Serial Data Input
14 O7 DAC Output #7, addr = 0110
2
15 O8 DAC Output #8, addr = 0111
2
16 O9 DAC Output #9, addr = 1000
2
17 O10 DAC Output #10, addr = 1001
2
18 O11 DAC Output #11, addr = 1010
2
19 O12 DAC Output #12, addr = 1011
2
20 V
DD
Positive power supply, specified for operation at
both +3 V and +5 V
ORDERING GUIDE
Temperature Package Package
Model FTN Range Description Option
AD8802AN RS –40°C/+85°C PDIP-20 N-20
AD8802AR RS –40°C/+85°C SOL-20 R-20
AD8802ARU RS –40°C/+85°C TSSOP-20 RU-20
AD8804AN REFL –40°C/+85°C PDIP-20 N-20
AD8804AR REFL – 40°C/+85°C SOL-20 R-20
AD8804ARU REFL –40°C/+85°C TSSOP-20 RU-20
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD8802/AD8804–Typical Performance Characteristics
REV. 0
–4–
CODE – Decimal
INL – LSB
1
–1
0.75
0
–0.25
–0.5
–0.75
0.5
0.25
0 25632 64 96 128 160 192 224
V
DD
= +5V
V
REFH
= +5V
V
REFL
= 0V
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
Figure 1. INL vs. Code
CODE – Decimal
INL – LSB
1
–1
0.75
0
–0.25
–0.5
–0.75
0.5
0.25
0 25632 64 96 128 160 192 224
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
DD
= +5V
V
REFH
= +5V
V
REFL
= 0V
Figure 2. Differential Nonlinearity Error vs. Code
FREQUENCY
ABSOLUTE VALUE TOTAL UNADJUSTED ERROR – LSB
1600
320
960
640
1280
00 0.2 0.4 0.6 0.8 1.0
V
DD
= +4.5V
V
REF
= +4.5V
V
REFL
= 0V
T
A
= +25°C
SS = 3600 PCS
Figure 3. Total Unadjusted Error Histogram
CODE – Decimal
160
0
80
40
120
140
100
60
20
0 25632 64 96 128 160 192 224
I
REF
CURRENT – µA
V
DD
= +5V
V
REFH
= +2V
V
REFL
= 0V
ONE DAC CHANGING WITH CODE,
OTHER DACs SET TO 00H
T
A
= +25°C
Figure 4. Input Reference Current vs. Code
10k
1k
0
100
10
–35 255–15–55 65 1251058545
TEMPERATURE – °C
SHUTDOWN CURRENT – nA
V
DD
= +5.5V
V
REF
= +5.5V
V
DD
= +2.7V
V
REF
= +2.7V
Figure 5. Shutdown Current vs. Temperature
TEMPERATURE – °C
SUPPLY CURRENT – µA
100k
0.001
10k
10
1
0.1
0.01
1k
100
–55 125–35 –15 5 25 45 65 85 105
V
DD
= +5.5V
V
IN
= +5.5V
V
DD
= +5.5V
V
IN
= +2.4V
Figure 6. Supply Current vs. Temperature
AD8802/AD8804
REV. 0 –5–
100
0.0001 2.5
0.01
0.001
0.50
0.1
1.0
10
21.51 INPUT VOLTAGE – Volts 53 4.543.5
T
A
= +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
SUPPLY CURRENT – mA
V
DD
= +5V
V
DD
= +3V
Figure 7. Supply Current vs. Logic Input Voltage
80
60
40
20
0100 100k10k1k10 FREQUENCY – Hz
PSRR – dB
V
DD
= +5V
ALL OUTPUTS SET
TO MIDSCALE (80H)
Figure 8. Power Supply Rejection vs. Frequency
10
0%
100
90
0%
V
DD
= +5V
V
REF
= +5V
TIME – 5µs/DIV
4V
0V
5V
0V
OUT
CS
2V 5µs
6V
2V
5V
Figure 9. Large-Signal Settling Time
10
0%
100
90
OUTPUT1: OO
H
→ FF
H
TIME – 0.2µs/DIV
OUTPUT2 – 10mV/DIV
10mV 200ns
V
DD
= +5V
V
REF
= +5V
f = 1MHz
Figure 10. Adjacent Channel Clock Feedthrough
10
0%
100
90
OUTPUT1: 7F
H
→ 80
H
V
DD
= +5V
V
REF
= +5V
TIME – 1µs/DIV
OUT1
5mV/DIV
CS
5V/DIV
5mV 1µs
5V
Figure 11. Midscale Transition
HOURS OF OPERATION AT 150°C
0.01
–0.01
0
–0.005
0.005
0600100 300 500
CHANGE IN ZERO-SCALE ERROR – LSB
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
VREFL = 0V
200 400
Figure 12. Zero-Scale Error Accelerated by Burn-In
AD8802/AD8804
REV. 0
–6–
HOURS OF OPERATION AT 150°C
0.04
–0.04
0
–0.02
0.02
0600200 300 500
V
DD
= +4.5V
V
REF
= +4.5V
SS = 176 PCS
x + 2σ
CHANGE IN FULL-SCALE ERROR – LSB
x
x – 2σ
100 400
Figure 13. Full-Scale Error Accelerated by Burn-In
HOURS OF OPERATION AT 150°C
1.0
–1.0
0
–0.5
0.5
INPUT RESISTANCE DRIFT – kΩ
0600200 300 400
V
DD
= +4.5V
V
REF
= +4.5V
CODE = 55
H
SS = 176 PCS
x + 2σx
x – 2σ
100 500
Figure 14. REF Input Resistance Accelerated by Burn-In
OPERATION
The AD8802/AD8804 provides twelve channels of program-
mable voltage output adjustment capability. Changing the pro-
grammed output voltage of each DAC is accomplished by
clocking in a 12-bit serial data word into the SDI (Serial Data
Input) pin. The format of this data word is four address bits,
MSB first, followed by 8 data bits, MSB first. Table I provides
the serial register data word format. The AD8802/AD8804 has
the following address assignments for the ADDR decode which
determines the location of the DAC register receiving the serial
register data in Bits B7 through B0:
DAC# = A3
×
8 + A2
×
4 + A1
×
2 + A0 + 1
DAC outputs can be changed one at a time in random se-
quence. The fast serial-data loading of 33 MHz makes it pos-
sible to load all 12 DACs in as little time as 4.6 µs (13
×
12
×
30 ns). The exact timing requirements are shown in Figure 15.
Table I. Serial-Data Word Format
ADDR DATA
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB LSB
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
The AD8802 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power-up. The
AD8804 has both a V
REFH
and a V
REFL
pin to establish indepen-
dent positive full-scale and zero-scale settings to optimize reso-
lution. Both parts offer a power shutdown SHDN which places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply
and V
REF
inputs. In shutdown mode the DACX register settings
are maintained. When returning to operational mode from
power shutdown the DAC outputs return to their previous volt-
age settings.
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DAC REGISTER LOAD
1
0
1
0
1
0
+5V
0V
SDI
CLK
CS
V
OUT
Figure 15a. Timing Diagram
AX OR DXAX OR DX
1
0
1
0
1
0
+5V
0V
SDI
(DATA IN)
CLK
CS
VOUT ±1/2 LSB
±1/2 LSB ERROR BAND
t
CSH
t
CL
t
CSS
t
DS
t
DH
t
CS1
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
t
CSW
t
CH
t
S
Figure 15b. Detail Timing Diagram
t
S
t
RS
±1 LSB
±1 LSB ERROR BAND
1
0
+5V
2.5V
RS
V
OUT
RESET TIMING
Figure 15c. Reset Timing Diagram
AD8802/AD8804
REV. 0 –7–
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external refer-
ence connected to V
REFH
and V
REFL
pins. See Figure 16 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8802 its V
REFL
is internally connected to GND and
therefore cannot be offset. V
REFH
can be tied to V
DD
and V
REFL
can be tied to GND establishing a basic rail-to-rail voltage out-
put programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation which determines the programmed output
voltage is:
VO (Dx) = (Dx)/256 × (V
REFH
– V
REFL
) + V
REFL
Eq. 1
where Dx is the data contained in the 8-bit DACx register.
MSB O
X
2R
R
P CH
N CH
TO OTHER DACS
R
2R
2R
2R
GND
V
REFL
LSB
DAC
REGISTER
D6
D0
D7
V
REFH
.
.
..
.
..
.
.
Figure 16. AD8802/AD8804 Equivalent TrimDAC Circuit
For example, when V
REFH
= +5 V and V
REFL
= 0 V, the follow-
ing output voltages will be generated for the following codes:
Output State
D VOx (V
REFH
= +5 V, V
REFL
= 0 V)
255 4.98 V Full Scale
128 2.50 V Half Scale (Midscale Reset Value)
1 0.02 V 1 LSB
0 0.00 V Zero Scale
REFERENCE INPUTS (V
REFH
, V
REFL
)
The reference input pins set the output voltage range of all
twelve DACs. In the case of the AD8802 only the V
REFH
pin is
available to establish a user designed full-scale output voltage.
The external reference voltage can be any value between 0 and
V
DD
but must not exceed the V
DD
supply voltage. The AD8804
has access to the V
REFL
which establishes the zero-scale output
voltage, any voltage can be applied between 0 V and V
DD
. V
REFL
can be smaller or larger in voltage than V
REFH
since the DAC
design uses fully bidirectional switches as shown in Figure 16.
The input resistance to the DAC has a code dependent variation
which has a nominal worst case measured at 55
H
, which is ap-
proximately 1.2 kΩ. When V
REFH
is greater than V
REFL
, the
REFL reference must be able to sink current out of the DAC
ladder, while the REFH reference is sourcing current into the
DAC ladder. The DAC design minimizes reference glitch cur-
rent maintaining minimum interference between DAC channels
during code changes.
DAC OUTPUTS (O1–O12)
The twelve DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribu-
tion of R
OUT
from DAC-to-DAC typically matches within ±1%.
However device-to-device matching is process lot dependent
having a ±20% variation. The change in R
OUT
with temperature
has a 500 ppm/°C temperature coefficient. During power shut-
down all twelve outputs are open-circuited.
CS
CLK
SDI
SHDN
AD8802/AD8804
D7
D0
ADDR
DEC
EN
D11
D10
D9
D8
D7
SER
REG
DD0
DAC
REG
#1
R
V
DD
D7
D0
DAC
12
DAC
REG
#12
R
DAC
1
8
O1
O2
O4
O5
O6
O7
O8
O9
O10
O11
O12
V
REFH
GND RS
(AD8802 ONLY) V
REFL
(AD8804 ONLY)
O3
Figure 17. Block Diagram
DIGITAL INTERFACING
The AD8802/AD8804 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 17 block diagram shows more detail of the internal digital
circuitry. When CS is taken active low, the clock can load data
into the serial register on each positive clock edge, see Table II.
Table II. Input Logic Control Truth Table
CS CLK Register Activity
1 X No effect.
0 P Shifts Serial Register One bit loading the next bit
in from the SDI pin.
P 1 Clock should be high when the CS returns to the
inactive state.
P = Positive Edge, X = Don’t Care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the twelve positive-edge triggered
DAC registers, see Figure 18 detail.
AD8802/AD8804
REV. 0
–8–
.
.
.
DAC 12
ADDR
DECODE
SERIAL
REGISTER
CS
CLK
SDI
DAC 2
DAC 1
Figure 18. Equivalent Control Logic
The target DAC register is loaded with the last eight bits of the
serial data-word completing one DAC update. Twelve separate
12-bit data words must be clocked in to change all twelve out-
put settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 19. Applies to
digital input pins CS, SDI, RS, SHDN, CLK
LOGIC
1kΩ
Figure 19. Equivalent ESD Protection Circuit
Digital inputs can be driven by voltages exceeding the AD8802/
AD8804 V
DD
supply value. This allows 5 V logic to interface
directly to the part when it is operated at 3 V.
APPLICATIONS
Supply Bypassing
Precision analog products, such as the AD8802/AD8804, re-
quire a well filtered power source. Since the AD8802/AD8804
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
If possible, the AD8802/AD8804 should be powered directly
from the system power supply. This arrangement, shown in Fig-
ure 20, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line in-
duced errors. Local supply bypassing consisting of a 10 µF tan-
talum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 21).
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
10µF
TANT 0.1µF
+AD8802/
AD8804
Figure 20. Use Separate Traces to Reduce Power Supply
Noise
AD8802/
AD8804
V
DD
DGND
10µF 0.1µF
+
+5V
Figure 21. Recommended Supply Bypassing for the
AD8802/AD8804
Buffering the AD8802/AD8804 Output
In many cases, the nominal 5 kΩ output impedance of the
AD8802/AD8804 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 22. One ampli-
fier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers opera-
tion to less than 3 V, low offset voltage, and low supply current.
The next two DACs, B and C, are configured in a summing
arrangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The inser-
tion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
VH
VL
VREFH VDD
+5V
GND
VREFL
DIGITAL INTERFACING
OMITTED FOR CLARITY
R1
100kΩ
OP291
AD8802/
AD8804
SIMPLE BUFFER
0V TO 5V
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
VH
VL
VH
VL
Figure 22. Buffering the AD8802/AD8804 Output
Increasing Output Voltage Swing
An external amplifier can also be used to extend the output volt-
age swing beyond the power supply rails of the AD8802/AD8804.
This technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Fig-
ure 23 is configured to swing from –5 V to +5 V. The actual
output voltage is given by:
V
OUT
=1+R
F
R
S
×D
256 ×5V
()
–5V
where D is the DAC input value (i.e., 0 to 255). This circuit can
be combined with the “fine/coarse” circuit of Figure 22 if, for
example, a very accurate adjustment around 0 V is desired.
AD8802/AD8804
REV. 0 –9–
A
VDD VREFH
GND VREFL
AD8802/
AD8804
B
+5V
+12V
–5V
OP191
OP193
RF
100kΩ
RS
100kΩ
–5V TO +4.98V
0V TO +10V
100kΩ
100kΩ
+5V
AD8804
ONLY
Figure 23. Increasing Output Voltage Swing
DAC B of Figure 24 is in a noninverting gain of two configura-
tions, which increases the available output swing to +10 V. The
feedback resistors can be adjusted to provide any scaling of the
output voltage, within the limits of the external op amp power
supplies.
Microcomputer Interfaces
The AD8802/AD8804 serial data input provides an easy inter-
face to a variety of single-chip microcomputers (µCs). Many µCs
have a built-in serial data capability that can be used for com-
municating with the DAC. In cases where no serial port is pro-
vided, or it is being used for some other purpose (such as an
RS-232 communications interface), the AD8802/AD8804 can
easily be addressed in software.
Twelve data bits are required to load a value into the AD8802/
AD8804 (4 bits for the DAC address and 8 bits for the DAC
value). If more than 12 bits are transmitted before the Chip Se-
lect input goes high, the extra (i.e., the most-significant) bits are
ignored. This feature is valuable because most µCs only transmit
data in 8-bit increments. Thus, the µC will send 16 bits to the
DAC instead of 12 bits. The AD8802/AD8804 will only re-
spond to the last 12 bits clocked into the SDI port, however, so
the serial data interface is not affected.
An 8051 µC Interface
A typical interface between the AD8802/AD8804 and an 8051
µC is shown in Figure 24. This interface uses the 8051’s internal
serial port. The serial port is programmed for Mode 0 opera-
tion, which functions as a simple 8-bit shift register. The 8051’s
Port 3.0 pin functions as the serial data output, while Port 3.1
serves as the serial clock.
When data is written to the Serial Buffer Register (SBUF, at
Special Function Register location 99
H
), the data is automati-
cally converted to serial format and clocked out via Port 3.0 and
Port 3.1. After 8 bits have been transmitted, the Transmit Inter-
rupt flag (SCON.1) is set and the next 8 bits can be transmitted.
The AD8802 and AD8804 require the Chip Select to go low at
the beginning of the serial data transfer. In addition, the SCLK
input must be high when the Chip Select input goes high at the
end of the transfer. The 8051’s serial clock meets this require-
ment, since Port 3.1 both begins and ends the serial data in the
high state.
+5V
P3.0
P3.1
P1.3
P1.2
P1.1
SERIAL DATA
SHIFT REGISTER RxD
TxD
SHIFT CLOCK
1.11.21.3
PORT 1
SBUF
8051 µC
0.1µF 10µF
O1
O12
GND
AD8802
SDI
SCLK
RESET
SHDN
CS
V
REFH
V
DD
Figure 24. Interfacing the 8051
µ
C to an AD8802/AD8804,
Using the Serial Port
Software for the 8051 Interface
A software for the AD8802/AD8804 to 8051 interface is
shown in Listing 1. The routine transters the 8-bit data stored at
data memory location DAC_VALUE to the AD8802/AD8804
DAC addressed by the contents of location DAC_ADDR.
The subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0 opera-
tion. Next the DAC’s Chip Select input is set low to enable the
AD8802/AD8804. The DAC address is obtained from memory
location DAC_ADDR, adjusted to compensate for the 8051’s
serial data format, and moved to the serial buffer register. At
this point, serial data transmission begins automatically. When
all 8 bits have been sent, the Transmit Interrupt bit is set, and
the subroutine then proceeds to send the DAC value stored at
location DAC_VALUE. Finally the Chip Select input is re-
turned high, causing the appropriate AD8802/AD8804 output
voltage to change, and the subroutine ends.
The 8051 sends data out of its shift register LSB first, while the
AD8802/AD8804 require data MSB first. The subroutine there-
fore includes a BYTESWAP subroutine to reformat the data.
This routine transfers the MSB-first byte at location SHIFT1 to
an LSB-first byte at location SHIFT2. The routine rotates the
MSB of the first byte into the carry with a Rotate Left Carry in-
struction, then rotates the carry into the MSB of the second byte
with a Rotate Right Carry instruction. After 8 loops, SHIFT2
contains the data in the proper format.
The BYTESWAP routine in Listing 1 is convenient because the
DAC data can be calculated in normal LSB form. For example,
producing a ramp voltage on a DAC is simply a matter of re-
peatedly incrementing the DAC_VALUE location and calling
the LD_8802 subroutine.
If the µC’s hardware serial port is being used for other purposes,
the AD8802/AD8804 DAC can be loaded by using the parallel
port. A typical parallel interface is shown in Figure 25. The se-
rial data is transmitted to the DAC via the 8051’s Port 1.6 out-
put, while Port 1.6 acts as the serial clock.
Software for the interface of Figure 25 is contained in Listing 2. The
subroutine will send the value stored at location DAC_VALUE to
the AD8802/AD8804 DAC addressed by location DAC_ADDR.
The program begins by setting the AD8802/AD8804’s Serial
Clock and Chip Select inputs high, then setting Chip Select low
AD8802/AD8804
REV. 0
–10–
;
; This subroutine loads an AD8802/AD8804 DAC from an 8051 microcomputer,
; using the 8051’s serial port in MODE 0 (Shift Register Mode).
; The DAC value is stored at location DAC_VAL
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
;
PORT1 DATA 90H ;SFR register for port 1
DAC_VALUE DATA 40H ;DAC Value
DAC_ADDR DATA 41H ;DAC Address
SHIFT1 DATA 042H ;high byte of 16-bit answer
SHIFT2 DATA 043H ;low byte of answer
SHIFT_COUNT DATA 44H ;
;ORG 100H ;arbitrary start
DO_8802: CLR SCON.7 ;set serial
CLR SCON.6 ;data mode 0
CLR SCON.5
CLR SCON.1 ;clr transmit flag
ORL PORT1.1,#00001110B ;/RS, /SHDN, /CS high
CLR PORT1.1 ;set the /CS low
MOV SHIFT1,DAC_ADDR ;put DAC value in shift register
ACALL BYTESWAP ;
MOV SBUF,SHIFT2 ;send the address byte
ADDR_WAIT: JNB SCON.1,ADDR_WAIT ;wait until 8 bits are sent
CLR SCON.1 ;clear the serial transmit flag
MOV SHIFT1,DAC_VALUE ;send the DAC value
ACALL BYTESWAP ;
MOV SBUF,SHIFT2 ;
VALU_WAIT: JNB SCON.1,VALU_WAIT ;wait again
CLR SCON.1 ;clear serial flag
SETB PORT1.1 ;/CS high, latch data
RET ; into AD8801
;
BYTESWAP: MOV SHIFT_COUNT,#8 ;Shift 8 bits
SWAP_LOOP: MOV A,SHIFT1 ;Get source byte
RLC A ;Rotate MSB to carry
MOV SHIFT1,A ;Save new source byte
MOV A,SHIFT2 ;Get destination byte
RRC A ;Move carry to MSB
MOV SHIFT2,A ;Save
DJNZ SHIFT_COUNT,SWAP_LOOP ;Done?
RET
END
Listing 1. Software for the 8051 to AD8802/AD8804 Serial Port Interface
+5V
P1.7
P1.6
P1.5
P1.4
1.51.61.7
PORT 1
8051 µC
1.4
CLK
V
REFL
SDI O1
O12
CS
SHDN
GND
AD8804
V
DD
V
REFH
Figure 25. An AD8802/AD8804-8051
µ
C Interface Using
Parallel Port 1
to start the serial interface process. The DAC address is loaded
into the accumulator and four Rotate Right shifts are per-
formed. This places the DAC address in the 4 MSBs of the ac-
cumulator. The address is then sent to the AD8802/AD8804 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8802/AD8804. Finally,
the Chip Select input is set high to complete the data transfer
Unlike the serial port interface of Figure 24, the parallel port in-
terface only transmits 12 bits to the AD8802/AD8804. Also, the
BYTESWAP subroutine is not required for the parallel inter-
face, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be deter-
mined by whether or not the serial data port is available for
communication with the AD8802/AD8804.
AD8802/AD8804
REV. 0 –11–
; This 8051 µC subroutine loads an AD8802 or AD8804 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1 DATA 90H ;SFR register for port 1
DAC_VALUE DATA 40H ;DAC Value
DAC_ADDR DATA 41H ;DAC Address (0 through 7)
LOOPCOUNT DATA 43H ;COUNT LOOPS
;
ORG 100H ;arbitrary start
LD_8804: ORL PORT1,#11110000B ;set CLK, /CS and /SHDN high
CLR PORT1.5 ;Set Chip Select low
MOV LOOPCOUNT,#4 ;Address is 4 bits
MOV A,DAC_ADDR ;Get DAC address
RR A ;Rotate the DAC
RR A ;address to the Most
RR A ;Significant Bits (MSBs)
RR A ;
ACALL SEND_SERIAL ;Send the address
MOV LOOPCOUNT,#8 ;Do 8 bits of data
MOV A,DAC_VALUE
ACALL SEND_SERIAL ;Send the data
SETB PORT1.5 ;Set /CS high
RET ;DONE
SEND_SERIAL: RLC A ;Move next bit to carry
MOV PORT1.7,C ;Move data to SDI
CLR PORT1.6 ;Pulse the
SETB PORT1.6 ;CLK input
DJNZ LOOPCOUNT,SEND_SERIAL ;Loop if not done
RET;
END
Listing 2. Software for the 8051 to AD8802/AD8804 Parallel Port Interface
An MC68HC11-to-AD8802/AD8804 Interface
Like the 8051 µC, the MC68HC11 includes a dedicated serial
data port (labeled SPI). The SPI port provides an easy interface
to the AD8802/AD8804 (Figure 27). The interface uses three
lines of Port D for the serial data, and one or two lines from
Port C to control the SHDN and RS (AD8802 only) inputs.
SDI
CLK
CS
SHDN
RS (AD8802 ONLY)
AD8802/
AD8804*
MC68HC11*
MOSI
SCK
SS
PC0
PC1
(PD3)
(PD4)
(PD5)
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 26. An AD8802/AD8804-to-MC68HC11 Interface
A software routine for loading the AD8802/AD8804 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8802/AD8804. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8802/AD8804’s CS is driven low. Next, the DAC’s ad-
dress byte is transferred to the SPDR register, which automati-
cally initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8802/AD8804.
AD8802/AD8804
REV. 0
–12–
*
* AD8802/AD8804 to M68HC11 Interface Assembly Program
*
* M68HC11 Register definitions
*
PORTC EQU $1003 Port C control register
* “0,0,0,0;0,0,RS/, SHDN/”
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
* “0,0,/CS,CLK;SDI,0,0,0”
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
* “SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR EQU $1029 SPI status register
* “SPIF,WCOL,0,MODF;0,0,0,0”
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables: SDI1 is encoded from 0H to 7H
* SDI2 is encoded from 00H to FFH
* AD8802/AD8804 requires two 8-bit loads; upper 4 bits
* of SDI1 are ignored. AD8802/AD8804 address bits in last
* four LSBs of SDI1.
*
SDI1 EQU $00 SDI packed byte 1 “0,0,0,0;A3,A2,A1,A0”
SDI2 EQU $01 SDI packed byte 2 “DB7–DB4;DB3–DB0”
*
* Main Program
*ORG $C000 Start of user’s RAM in EVB
INIT LDS #$CFFF Top of C page RAM
*
* Initialize Port C Outputs
*LDAA #$03 0,0,0,0;0,0,1,1
* /RS-Hi, /SHDN-Hi
STAA PORTC Initialize Port C Outputs
LDAA #$03 0,0,0,0;0,0,1,1
STAA DDRC /RS and /SHDN are now enabled as outputs
*
* Initialize Port D Outputs
*LDAA #$20 0,0,1,0;0,0,0,0
* /CS-Hi,/CLK-Lo,SDI-Lo
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
STAA DDRD /CS,CLK, and SDI are now enabled as outputs
*
* Initialize SPI Interface
*LDAA #$53
STAA SPCR SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32
*
* Call update subroutine
*BSR UPDATE Xfer 2 8-bit words to AD8402
JMP $E000 Restart BUFFALO
*
* Subroutine UPDATE
*
UPDATE PSHX Save registers X, Y, and A
PSHY
PSHA
*
* Enter Contents of SDI1 Data Register
AD8802/AD8804
REV. 0 –13–
*LDAA $0000 Hi-byte data loaded from memory
STAA SDI1 SDI1 = data in location 0000H
*
* Enter Contents of SDI2 Data Register
*LDAA $0001 Low-byte data loaded from memory
STAA SDI2 SDI2 = Data in location 0001H
*LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
*
* Reset AD8802 to one-half scale (AD8804 does not have a Reset input)
*BCLR PORTC,Y $02 Assert /RS
BSET PORTC,Y $02 De-Assert /RS
*
* Get AD8802/04 ready for data input
*BCLR PORTD,Y $02 Assert /CS
*
TFRLP LDAA 0,X Get a byte to transfer for SPI
STAA SPDR Write SDI data reg to start xfer
*
WAIT LDAA SPSR Loop to wait for SPIF
BPL WAIT SPIF is the MSB of SPSR
*INX Increment counter to next byte for xfer
CPX #SDI2+1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
*
* Update AD8802 output
*BSET PORTD,Y $20 Latch register & update AD8802
*PULA When done, restore registers X, Y & A
PULY
PULX
RTS ** Return to Main Program **
Listing 3. AD8802/AD8804 to MC68HC11 Interface Program Source Code
An Intelligent Temperature Control System—Interfacing the
8051 mC with the AD8802/AD8804 and TMP14
Connecting the 80CL51 µC, or any modern microcontroller,
with the TMP14 and AD8802/AD8804 yields a powerful tem-
perature control tool, as shown in Figure 27. For example, the
80CL51 µC controls the TrimDACs allowing the user to auto-
matically set the temperature setpoints voltages of the TMP14
via computer or touch pad, while the TMP14 senses the tem-
perature and outputs four open-collector trip-points. Feeding
these trip-point outputs back to the 80CL51 µC allow it to sense
whether or not a setpoint has been exceeded. Additional
80CL51 µC port pins or TMP14 trip-point outputs may then
be used to change fan speed (i.e., high, medium, low, off), or
increase/decrease the power level to a heater. (Please refer to the
TMP14 data sheet for more applications information.)
The CS (Chip Select) on the AD8802/AD8804 makes applica-
tions that call for large temperature sensor arrays possible. In
addition, the 12 channels of the AD8802/AD8804 allow inde-
pendent setpoint control for all four trip-point outputs on up to
three TMP14 temperature sensors. For example, assume that
the 80CL51 µC has eight free port pins available after all user
interface lines, interrupts, and the serial port lines have been
assigned. The eight port pins may be used as chip selects, in
which case an array of eight AD8802/AD8804s controlling
twenty-four TMP14 sensors is possible.
The AD8802/AD8804 and TMP14 are also ideal choices for
low power applications. These devices have power shutdown
modes and operate on a single 5 Volt supply. When their shut-
down modes are activated current consumption is reduced to
less than 35 µA. However, at high operating frequencies
(12 MHz) the 80CL51 consumes far more energy (18 mA typ)
than the AD8802/AD8804 and TMP14 combined. Therefore,
to achieve a low power design the 80CL51 should operate at its
lowest possible frequency or be placed in its power-down mode
at the end of each instruction sequence.
To use the power-down mode of the 80CL51 µC set PCON.1
as the last instruction executed prior to going into the power-
down mode. If INT2 and INT9 are enabled, the 80CL51 µC
can be awakened from power-down mode with external inter-
rupts. As shown in Figure 28, the TLC555 outputs a pulse
every few seconds providing the interrupt to restart the 80CL51
µC which then samples the user input pins, the outputs of the
AD8802/AD8804
REV. 0
–14–
USER
INPUTS
3TO 2nd AD8802/4
ARRAY IF NEEDED
TO 2nd TEMP SENSOR
IF NEEDED
4
TO 3rd TEMP SENSOR
IF NEEDED
4
0.1µF 10µF+5V
+5V
0.1µF
TMP14
0.01µF
3
VCC
OUT
RS
DIS
THR
TRIG
GND
AD8802/4
TLC555
2.5 VREF
SET 1
SET 2
SET 3
SET 4
HYS
TRIP 1
TRIP 2
TRIP 3
TRIP 4
V+
GND
SLEEP
O1
O3
O4
O2
05–8
09–12
VDD
GND
SHDN
CS
CLK
SDI
P2.0
P2.1
P2.2
P2.3
P2.4
80CL51 µC
P1.0/INT2
P0.0
P0.7
P3.2
P3.1
P3.0
P3.3
VREFH
+5V
Figure 27. Temperature Sensor Array with Programmable Setpoints
The gain of the SSM2018T is controlled by the voltage at Pin 11.
For maximum attenuation of –100 dB a control signal of 3.0 V
typ is necessary. The control signal has a scale of –30 mV/dB
centered around 0 dB gain for 0 V of control voltage, therefore,
for a maximum gain of 40 dB a control voltage of –1.2 volts is
necessary. Now notice that the normal +5 V to GND voltage
range of the AD8802/AD8804 does not cover the 3.0 V to
–1.2 V operational gain control range of the SSM2018T. To
cover the operating gain range fully and not exceed the maxi-
mum specified power supply rating requires the O1 output of
AD8802/AD8804 to be level shifted down. In Figure 28, the
level shifting is accomplished by a Zener diode and 1/4 of an
OP420 quad op amp. For applications that require only
TMP14, and makes the necessary adjustments to the AD8802/
AD8804 before shutting down again. The 80CL51 consumes
only 50 µA when operating at 32 kHz, in which case there
would be no need for the TLC555, which consumes 1 mW typ.
12 Channel Programmable Voltage Controlled Amplifier
The SSM2018T is a trimless Voltage Controlled Amplifier
(VCA) for volume control in audio systems. The SSM2018T is
the first professional quality audio VCA in the marketplace that
does not require an external trimming potentiometer to mini-
mize distortion. The TrimDAC shown in Figure 28 is not being
used to trim distortion, but rather to control the gain of the am-
plifier. In this configuration up to twelve SSM2018T can be
digitally controlled. (Please refer to the SSM2018T data sheet
for more specifications and applications information.)
–15V
R
O
150kΩ+V
50pF
18kΩ
18kΩ
1µF
18kΩ
1µF
+15V
8
1
2
3
4
7
6
5
14
13
12
11
16
15
10
9
SSM2018T
OP420A
1.2V
+15V
50kΩ
OPTIONAL FOR
0 TO 40dB GAIN
V
OUT
O1 V
REFH
O2–
O12
TO 8 MORE CHANNELS
O2
O3
O4–O12
CS
CLK
SDI
3
TO µC
1µF
V
REFL
(AD8804
ONLY)
OUT IN
GND
REF195
V+
GND
+15V
AD8802/4
47pF NC
Figure 28. 12-Channel Programmable Voltage Controlled Amplifier
AD8802/AD8804
REV. 0 –15–
15
13 –H SYNC
OUTPUT
40, 35, 30
38, 28, 33
BLANK GATE
INPUT
24
+4V
VCC
(+12V)
+12V
VCC
9
43
22
21
20
5
RGB FEEDBACK
CRT
VIDEO
AMP
CRT
CATHODE
0.1µF 10µF OUT IN
GND
REF195
10µF 0.1µF
+12V
VCC
TO µC
O1 O2 O3 04 O5 O6 O7 VREFH
CS
CLK
SDI
AD8802/4
RGB
VIDEO
INPUT
7, 11, 17 LM1204
O1 = 2V
O2 = CONTRAST
O3 = BP CLAMP WIDTH ADJUST
O4 = BLANK LEVEL ADJUST
(FOR BRIGHTNESS CONTROL)
O5 = R AGAIN
O6 = B AGAIN
O7 = G AGAIN
O8 – O12 = NOT USED
R ∆GAIN
B ∆GAIN
G ∆GAIN
Figure 29. A Digitally Controlled LM1204—150 MHz RGB Amplifier System
attenuation the optional circuitry inside the dashed box may be
removed and replaced with a direct connection from O1 of
AD8802/AD8804 to Pin 11 of SSM2018T.
When high gain resolution is desired, V
REFH
and V
REFL
may be
decoupled from the power rails and shifted closer together.
This technique increases the gain resolution with the unfortu-
nate penalty of decreased gain range.
A Digitally Controlled LM1204 150 MHz RGB Amplifier
System
The LM1204 is an industry standard video amplifier system.
Figure 29 illustrates a configuration that removes the usual
seven level setting potentiometers and replaces them with only
one IC. The AD8802/AD8804, in addition to being smaller
and more reliable than mechanical potentiometers, has the
added feature of digital control.
The REF195 is a 5.0 V reference used to supply both the power
and reference voltages to the AD8802/AD8804. This is possible
because of the high reference output current available (30 mA
typical) together with the low power consumption of the
AD8802/AD8804.
A Low Noise 90 MHz Programmable Gain Amplifier
The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin selectable
gains of –11 dB to +31 dB with a bandwidth of 90 MHz or
+9 dB to +51 dB with a bandwidth of 9 MHz. Any intermedi-
ate gain range may be arranged using one external resistor
between Pins 5 and 7. The input referred noise spectral density
is only 1.3 nV√Hz and power consumption is 125 mW at the
recommended ±5 V supplies.
The decibel gain is “linear in dB,” accurately calibrated, and
stable over temperature and supply. The gain is controlled at a
high impedance (50 MΩ), low bias (200 nA) differential input;
the scaling is 25 mV/dB, requiring a gain-control voltage of only
1 V to span the central 40 dB of the gain range. An overrange
and underrange of 1 dB is provided whatever the selected
range. The gain-control response time is less than 1 µs for a 40
dB change. The settling time of the AD8802/AD8804 to within
a ±1/2 LSB band is 0.6 µs making it an excellent choice for con-
trol of the AD603.
The differential gain-control interface allows the use of either
differential or single-ended positive or negative control voltages,
where the common-mode range is –1.2 V to 2.0 V. Once again
the AD8802/AD8804 is ideally suited to provide the differential
input range of 1 V within the common-mode range of 0 V to
2 V. To accomplish this, place V
REFH
at 2.0 V and V
REFL
at
1.0 V, then all 256 voltage levels of the AD8804 will fall within
the gain-control range of the AD603. Please refer to the AD603
data sheet for further information regarding gain control, layout,
and general operation.
The dual OP279 is a rail-to-rail op amp used in Figure 30 to
drive the inputs V
REFH
and V
REFL
because these reference inputs
are low impedance (2 kΩ typical).
AD8802/AD8804
REV. 0
–16–
7
2
5
1
6
3
4
8
AD603
0.1µF+10V
0.1µF
100Ω
0.1µF
IN OUT
GND
REF195
10µF
+10V 1µF
0.1µF
+5.0V
1/2 OP279
V
DD
V
REFH
O1 O2 O3 O4
GND SHDN SDI CLK CS
V
REFL
A
AD8804
1/2 OP279
B1.0V
TO µC
0.1µF+10V
7
2
5
1
6
3
4
8
AD603
30kΩ
2.0V
20kΩ
40kΩ
10kΩ
10µF
Figure 30. A Low Noise 90 MHz PGA
C2052–10–7/95
PRINTED IN U.S.A.
20-Lead Thin Surface Mount TSSOP Package
(RU-20)
20 11
10
1
0.260 (6.60)
0.252 (6.40)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8°
0°
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
20-Pin Plastic DIP Package
(N-20)
20
110
11
0.255 (6.477)
0.245 (6.223)
PIN 1
1.07 (27.18) MAX
SEATING
PLANE
0.021 (0.533)
0.015 (0.381)
0.060 (1.52)
0.015 (0.38)
0.145 (3.683)
MAX
0.125 (3.175)
MIN
0.065 (1.66)
0.045 (1.15)
0.11 (2.79)
0.09 (2.28)
0.32 (8.128)
0.30 (7.62)
0.011 (0.28)
0.009 (0.23)
0.135 (3.429)
0.125 (3.17)
15°
0
20-Lead SOIC Package
(R-20)
SEATING
PLANE
0.011 (0.275)
0.005 (0.125) 0.022 (0.56)
0.014 (0.36)
0.107 (2.72)
0.089 (2.26)
0.050
(1.27)
BSC 0.015 (0.38)
0.007 (0.18) 0.034 (0.86)
0.018 (0.46)
8°
0°
20 11
101
0.512 (13.00)
0.496 (12.60)
0.419 (10.65)
0.404 (10.00)
0.299 (7.60)
0.291 (7.40)
PIN 1
