1
®ISL8120
Dual/n-Phase Buck PWM Controller with
Integrated Drivers
The ISL8120 integrates two voltage-mode synchronous
buck PWM controllers to control a dual independent voltage
regulator or a 2-phase single output regulator. It has PLL
circuits and can output a phase-shift-programmable clock
signal for the system to be expanded to 3-, 4-, 6-, 12- phases
with desired interleaving phase shift. It also integrates
current sharing control for the power module to operate in
parallel, which offers high system flexibility.
It has voltage feed forward compensation to maintain a
constant loop gain for optimal transient response, especially
for applications with a wide input voltage range. Its
integrated high speed MOSFET drivers and multi- feature
functions provide complete control and protection for a
2/n-phase synchronous buck converter, dual indepen dent
regulators, or DDR tracking applications (VDDQ and VTT
outputs).
The output voltage of a ISL8120-based converter can be
precisely regulated to as low as the internal reference
voltage 0.6V, with a system accuracy of ±0.6% over
commercial temperature and line load variations. Channel 2
can track an external ramp signal for DDR /tracking
applications.
The ISL8120 integrates an interna l linear regulator, which
generates VCC from input rail for applications with only one
single supply rail. The internal oscillator is adjustable from
150kHz to 1.5MHz, and is able to track an external clock
signal for frequency synchroni zation and phase paralleling
applications. The integrated Pre-Bi ased Digital Soft-Start,
Differential Remote Sensing Amplifier, and Programmable
Input Voltage POR features enhance the value of ISL8120.
The ISL8120 protects against overcurrent conditions by
inhibiting the PWM operation while monitoring the current
with rDS(ON) of the lower MOSFET, DCR of the output
inductor, or a precision res ist or. It also has a PRE-POR
Overvoltage Protection option, which provides some
protection to the load device if the upper MOSFET(s) is
shorted. See “PRE-POR Overvoltage Protection (PRE-POR-
OVP)” on page 25 for details.
The ISL8120’s Fault Hand Shake feature protects any
channel from overloading/stressing due to system faults or
phase failure. The undervoltage fault protection features are
also designed to prevent a negative transient on the output
voltage during falling down. This eliminates the Schottky
diode that is used in some systems for protecting the load
device from reversed output voltage damage.
Features
• Wide VIN Range Operation: 3V to 22V
- VCC Operation from 3V to 5.60V
• Fast Transient Response
- 80MHz Bandwidth Error Amplifier
- Voltage-Mode PWM Lead ing-edge Modulation Control
- Voltage Feed-forward
• Dual Channel 5V High Speed 4A MOSF ET Gate Drivers
- Internal Bootstrap Diodes
• Internal Linear Regulator Provides a 5.4V Bias from VIN
• External Soft-Start Ramp Reference Input for
DDR/Tracking Applications
• Excellent Output Vo ltage Regulation
- 0.6V ±0.6%/±0.9% Internal Reference Over
Commercial/Industrial Temperature
- True Differential Remote Voltage Sensing
• Oscillator Programmable from 150kHz to 1.5MHz
• Frequency Synchronization
• Scale for 1-, 2-, 3-, 4-, 6-, up to 12- Phase with Single
Output
- Excellent Phase Current Balanc ing
- Programmable Phase Shift Between the 2 Phases
Controlled by the ISL8120 and Programmable Phase
Shift for Clockout Signal
- Interleaving Operation Results in Minimum Input RMS
Current and Minimum Output Ripple Cu rrent
• Fault Hand Shake Capability for High System Reliability
• Overcurrent Protection
- DCR, rDS(ON), or Precision Resistor Current Sensing
- Independent and Average Phase Current OCP
• Output Overvoltage and Undervoltage Protections
• Programmable Phase Shift in Dual Mode Operation
• Digital Soft-Start with Pre-Charged Output Start-up
Capability
• Power-Good Indication
• Dual Independent Channel Enable Inputs with Precision
Voltage Monitor and Voltage Feed-forward Capability
- Programmable In put Voltage POR and its Hysteresis
with a Resistor Divider at EN Input
• Over-Temperature Protection
• Pre-Power-On-Reset Overvoltage Protection Option
• 32 Ld 5x5 QFN Package - Near Chip-Scale Footprint
- Enhanced Thermal Performance for MHz Applications
• Pb-free (RoHS compliant)
FN6641.1Data Sheet April 7, 2009
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2March 20, 2009
FN6641.0
ISL8120
Applications
• Power Supply for Datacom/Telecom and POL
• Paralleling Power Module
• Wide and Narrow Input Voltage Range Buck Regulators
• DDR I and II Applications
• High Current Density Power Supplies
• Multiple Outputs VRM and VRD
Related Literature
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN (MLFP) Packag es”
Pinout ISL8120
(32 LD QFN)
TOP VIEW
Ordering Information
PART
NUMBER
(Note) PART
MARKING
TEMP.
RANGE
(°C) PACKAGE
(Pb-free)
PKG.
DWG.
#
ISL8120CRZ ISL8120 CRZ 0 to +70 32 Ld QFN L32.5x5B
ISL8120CRZ-T* ISL8120 CRZ 0 to +70 32 Ld QFN L32.5x5B
ISL8120IRZ ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
ISL8120IRZ-T* ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B
* Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temper atures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
FB1
VMON1
VSEN1-
VSEN1+
ISEN1B
ISEN1A
VCC
BOOT1
COMP2
FB2
VMON2
VSEN2-
VSEN2+
ISEN2B
ISEN2A
VIN
COMP1
ISET
ISHARE
EN/VFF1
FSYNC
EN/VFF2
CLKOUT/REFIN
PGOOD
UGATE1
PHASE1
LGATE1
PVCC
LGATE2
PHASE2
UGATE2
BOOT2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
910111213141516
33
GND
3April 7, 2009
ISL8120
Block Diagram
FIGURE 1. CHANNEL/PHASE 1 (VDDQ)
BOOT1
UGATE1
PHASE1
FB1
COMP1
LGATE1
E/A1
PVCCVCC
GATE
CONTROL
INTERNAL
REFERENCE
EN/FF1
PGOOD
PGOOD
COMP1
VMON1
VIN
LINEAR REGULATOR
OV/UV
COMP1
VSEN1+
VSEN1-
SOFT-START AND
FAULT LOGIC
OCP
VREF = 0.6V
UNITY GAIN
DIFF AMP1
POWER-ON
RESET (POR)
SAW1
ISEN1A
1.2V
PWM1
ICS1
CURRENT
CORRECTION
∑
+
-
PVCC
IAVG_CS
CHANNEL 1
CHANNEL 1
CURRENT
SAMPLING
700mV
VCC
ISEN1B
(BOTTOM PAD) GND
AVG_OCP
OVER-TEMPERATURE
PROTECTION (OTP)
ISHARE
108µA
7-CYCLE
DELAY
5.4V
CURRENT
CORRECTION ICSH_ERR
CHANNEL1 AVERAGE
OCP
PGOOD
VREF
OTP
ICSH_ERR
M/D Control
4April 7, 2009
ISL8120
FIGURE 2. CHANNEL/PHASE 2 (VTT)
Block Diagram (Continued)
BOOT2
UGATE2
PHASE2
FB2
COMP2
GND
LGATE2
CHANNEL2
E/A2
PVCC
ISEN2A
GATE
CONTROL
108µA
EN/FF2
PGOOD
PGOOD
COMP2
VMON2
OV/UV
COMP2
VSEN2+
VSEN2-
FAULT LOGIC
OCP
VREF
UNITY GAIN
DIFF AMP2
POR
MASTER CLOCK
FSYNC
SAW1
k*VDDQ
∑
+
-
PWM2
CURRENT
CORRECTION
ICS2
ICS2
ICS1 +
+
IAVG
PVCC
CLKOUT/REFIN
SAW2
OSCILLATOR
GENERATOR
CHANNEL 2
SOFT-START AND
VREF2
CHANNEL 2
CURRENT
SAMPLING
700mV
VCC
RELATIVE
PHASE
CONTROL
ISEN2B
AVERAGE
CURRENT
CURRENT
SHARE
BLOCK
ISHARE
ICSH_ERR
+
-
-
IAVG_CS
ISET
AVG_OCP
OTP
7-CYCLE
DELAY
M/D CONTROL
M/D = 1: multiphase
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
ICSH_ERR = (VISARE - VISET)/GCS
0.6V = k*VDDQ
VREF
M/D = 0: DUAL OUTPUT OPERATION
IAVG_CS+15µA
IAVG_CS+15µA
M/D
CONTROL
5March 20, 2009
FN6641.0
ISL8120
Typical Application I (Dual Regulators with DCR Sensing and Remote Sense)
VOUT1
VOUT2
ISL8120
Q1
Q2
COMP1
FB1
VCC
BOOT1
UGATE1
ISEN1A
LGATE1
LIN
LOUT1
CHFIN
CBOOT1
COUT1
RFB1
CF1
PHASE1
PVCC
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
+3.3 TO +22V
VMON1
VSEN1+
CSEN1 VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
ZFB1
Q3
Q4
COMP2
FB2
BOOT2
UGATE2
ISEN2A
LGATE2
LOUT2
CBOOT2
COUT2
RISEN2
RFB2
PHASE2
VSEN2- ROS2
VMON2
VSEN2+
CSEN2 VSENSE2-
VSENSE2+
10Ω
10Ω
ZCOMP2
ZFB2
VIN_F
VIN_F
CLKOUT/REFIN
ISHARE
GND
ISEN1B
CF2
ISEN2B
RISEN1
CBIN
RCC
ISET
VCC
RSET
2kΩ
2kΩ
EN2/FF2
EN1/FF1
VIN
6March 20, 2009
FN6641.0
ISL8120
Typical Application II (Double Data Rate I or II)
0.9V (DDR II)
0.9V
(DDR I)
1.25V
VDDQ
VTT
1.8V (DDR II)
(DDR I)
2.5V
ISL8120
Q1
Q2
COMP1
FB1
VCC
BOOT1
UGATE1
ISEN1A
LGATE1
LIN
LOUT1
CHFIN
CBOOT1
COUT1
RFB1
CF1
PHASE1
PVCC
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
+3.3 TO +22V
VMON1
VSEN1+
CSEN1 VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
ZFB1
Q3
Q4
COMP2
FB2
BOOT2
UGATE2
ISEN2A
LGATE2
LOUT2
CBOOT2
COUT2
RISEN2
RFB2
PHASE2
VSEN2- ROS2
VMON2
VSEN2+
CSEN2 VSENSE2-
VSENSE2+
10Ω
10Ω
ZCOMP1
ZFB1
VIN_F
VDDQ Or VIN_F
CLKOUT/REFIN
GND
ISEN1B
CF2
ISEN2B
RISEN1
CBIN
(V
DDQ/2)
RCC
ISHARE
ISET
RSET
2kΩ
2kΩ
VDDQ
R
VIN
R*(VTT/0.6-1)
(See notes below)
Note 1: Set the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from
the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start.
Note 2: Another way to set REFIN voltage is to connect VMON1 dir ectly to REFIN pin.
1nF
(Or tie REFIN pin to VMON1 pin)
The other way is to add more delay at EN/FF1 pin to have Channel 2 tracking VDDQ (check the DDR section for more details).
7March 20, 2009
FN6641.0
ISL8120
Typical Application III (2-Phase Operation with rDS(ON) Sensing and Voltage Trimming)
LIN
CHFIN CBIN
CF1
PVCC
CF2
RCC
+3V TO +22V
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
RFB1
PHASE1 VOUT1
RFS FSYNC
VIN
VSEN1- ROS1
PGOOD
VMON1/2
VSEN1+
CSEN1
VSENSE1-
VSENSE1+
10Ω
10Ω
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT2
VCC
EN/FF1, 2
CLKOUT/REFIN
GND
GND
ISEN2B
FB2
ISEN1A
RISEN2
TRIM UP
PULLED TO VSENSE1-
TRIM DOWN
PULLED TO VSENSE1+
ISEN1B RISEN1
ISHARE
ISET
RSET
CF3
DNP
0Ω
VIN
ISL8120
8March 20, 2009
FN6641.0
ISL8120
Typical Application IV (3-Phase Regulator with Precision Resistor Sensing)
CF1 PVCC CF2
RCC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1,2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VIN_F
VCC
LOUT3
VCC
EN/FF1, 2
VSEN2+
GND
ISEN2B
FB2
ISEN1A
ZFB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V TO +22V
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT
PHASE1 VOUT
EN/FF1
VIN
VSEN1-
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
BOOT2
UGATE2
ISEN2A
LGATE2
PHASE2
VIN_F
VCC
EN/FF2
FSYNC
ISHARE
GND
VMON2
ISEN1A
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS FSYNC
CLKOUT/REFIN
CF3
VSEN2-
VSEN2+
FB2
RFB1
ROS1 CSEN1
VCC
GND
RISEN3
ISEN1B
VCC
ISEN1B
ISEN2B
RISEN2
RISEN1
RISEN1
GND
ISET
R
R
ISET
R
R
PHASE 1 AND 3
ISL8120
ISL8120
PHASE 2
VCC
9March 20, 2009
FN6641.0
Typical Application V (4 Phase Operation with DCR Sensing)
CF1 PVCC CF2
RCC
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VIN_F
VCC
LOUT3
VCC
VSEN2+
GND
ISEN2B
FB2
ISEN1A
Z
FB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V TO +22V
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT
PHASE1 VOUT1
VIN
ROS1
PGOOD
VMON1/2
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN1,2-
VSEN1, 2+
VIN_F
VCC
LOUT4
VCC
EN/FF1, 2
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN_F
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS
FSYNC
CLKOUT/REFIN
CF3
PHASE 1 AND 3
PHASE 2 AND 4
RFB1
ROS1 CSEN1
2ND DIVIDER TO AVOID
SINGLE POINT FAILURE
RFB1
VCC
VCC
ISEN1B
RISEN2
RISEN4
ISEN1B
RISEN3
RISEN1
VCC
VCC
COS
ISET
R
ISET
R
R
R
ISL8120
ISL8120
ISL8120
10 March 20, 2009
FN6641.0
ISL8120
Typical Application VI (3-Phase Regulator with Resistor Sensing and 1 Phase Regulator)
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT3
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT3
VCC
EN/FF1, 2
VSEN2+
GND
ISEN2B
FB2
ISEN1A
ZFB1
LIN
CIN
CF1 PVCC CF2
RCC
+3V to +22V
ISL8120
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
COUT1
PHASE1 VOUT1
EN/FF1
VIN
VSEN1-
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VIN_F
VCC
LOUT4
EN/FF2
FSYNC
ISHARE
GND
VMON2
ISEN1A
VIN_F
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS FSYNC
CLKOUT/REFIN
CF3
VOUT2
VSENSE2-
VSENSE2+ VSEN2-
VSEN2+
10Ω
10Ω
ZFB2 ZCOMP2
COUT2
FB2
PHASE 1 AND 3
PHASE 2
RFB1
ROS1 CSEN1
VCC
GND
RISEN3
ISEN1B
RISEN4
VCC
VCC
ISEN1B
ISEN2B
RISEN2
RISEN1
RISEN1
ISET
R
ISET
R
R
PHASE 2
R
11 March 20, 2009
FN6641.0
ISL8120
Typical Application VIII (Multiple Power Modules in Parallel with Current Sharing Control)
CF1 PVCC CF2
RCC1
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VIN
VCC
LOUT2
GND
ISEN2B
ISEN1A
Z
FB1
LIN
CIN
CF4 PVCC CF5
RCC2
+3V to +22V
ISL8120
Q5
Q6
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
COUT2
PHASE1 VOUT2
VIN
PGOOD
VMON1/2
VSENSE2+
10Ω
10Ω
CF6
Q7
Q8
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VCC
LOUT4
EN/FF1, 2
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN
VIN_F
VIN
CLKOUT/REFIN
ISHARE
RFS
FSYNC
CLKOUT/REFIN
CF3
2-PHASE
2-PHASE
RFB1
ROS1 CSEN1
ISEN1B
RISEN3
RISEN4
ISEN1B
RISEN2
RISEN1
GND
ISET
R
ISET
R
R
R
COUT1
VOUT1
VSENSE1-
VSENSE1+
10Ω
10Ω
COMP1/2
VSEN1-
VSEN1+
ZCOMP2
Z
FB2
RFB2
ROS2 CSEN2 VSENSE2-
VSEN2-
VSEN2+
VCC
FB2
GND
RCSR1
RCSR2
VCC
VLOAD
MODULE #1
MODULE #2
2kΩ
2kΩ
2kΩ
2kΩ
12 March 20, 2009
FN6641.0
Typical Application VII (6 Phase Operation with DCR Sensing)
LIN CIN
CF1 PVCC CF2
RCC
+3V TO +22V
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT6
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT6
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2 ISEN1A
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
PHASE1 VOUT1
EN/FF1, 2
VIN
VSEN1- ROS1
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
10Ω
10Ω
CF3
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT4
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
ZFB1
CSEN1
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT2
PHASE1
EN/FF1,2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT5
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT5
VCC
FSYNC
ISHARE
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
GND
GND PHASE 2 AND 5
PHASE 1 AND 4
PHASE 3 AND 6
VCC
VCC
VMON2
RFB1
ROS1 RFB1
ISEN1B
ISEN1B
ISEN1B RISEN1
RISEN4
RISEN2
RISEN5
RISEN3
RISEN6
R
ISET
R
ISET
R
ISET
R
GND
VIN
R
R
ISL8120
13 March 20, 2009
FN6641.0
Typical Application VIIII (4 Outputs Operation with DCR Sensing)
COUT3
VOUT3
VSENSE3-
VSENSE3+
2Ω
2Ω
LIN CIN
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1
FB1
BOOT1
UGATE1
LGATE1
LOUT3
CBOOT3
PHASE1
EN/FF1
VIN
VSEN1-
PGOOD VMON1
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT6
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT6
EN/FF2
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT1
CBOOT1
COUT1
PHASE1 VOUT1
EN/FF1, 2
VIN
VSEN1- ROS1
PGOOD
VMON1
VSEN1+
VSENSE1-
VSENSE1+
2Ω
2Ω
CF3
ZCOMP1
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT4
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT4
VCC
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
ZFB1
CSEN1
VIN_F
CLKOUT/REFIN
CF1 PVCC CF2
RCC
ISL8120
Q1
Q2
COMP1/2
FB1
BOOT1
UGATE1
LGATE1
LOUT2
CBOOT1
PHASE1
EN/FF1, 2
VIN
VSEN1-
PGOOD
VMON1/2
VSEN1+
CF3
Q3
Q4
BOOT2
UGATE2
ISEN2A
LGATE2
CBOOT2
PHASE2
VSEN2-
VSEN2+
VIN_F
VCC
LOUT5
VCC
FSYNC
ISHARE/ISET
GND
ISEN2B
FB2
ISEN1A
VIN_F
CLKOUT/REFIN
GND
GND OUTPUT 2
OUTPUT 1
OUTPUT 3 AND 4
VMON2
RFB1
ROS1 RFB1
ISEN1B
ISEN1B
ISEN1B RISEN1
RISEN4
RISEN2
RISEN5
RISEN3
RISEN6
ZCOMP2 ZFB2
VOUT2
VSENSE2-
VSENSE2+
2Ω
COUT2
2Ω
ROS2 CSEN2
RFB2
ROS3 CSEN3
RFB3
ZFB3
COUT4
VOUT4
VSENSE4-
VSENSE4+
2Ω2Ω
ROS4 CSEN4
RFB4
COMP2
ZCOMP4
ZFB3
VMON2
(PHASE 1 and 4)
(PHASE 2 and 5)
(PHASE 3 and 6)
+3V TO +22V VIN
R
R
R
ISL8120
14 March 20, 2009
FN6641.0
Absolute Maximum Ratings Thermal Information
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +27V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
BOOT/UGATE Voltage, VBOOT. . . . . . . . . . . . . . . . . .-0.3V to +36V
Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V
BOOT to PHASE Voltage, VBOOT - VPHASE . . -0.3V to VCC +0.3V
Input, Output or I/O Voltage. . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Recommended Operating Conditions
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V
Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.6V
Boot to Phase Voltage (Overcharged), VBOOT - VPHASE. . . . . .<6V
Commercial Ambient Temperature Range. . . . . . . . . . 0°C to +70°C
Industrial Ambient Temperature R ange . . . . . . . . . . .-40°C to +85°C
Maximum Junction Temperature Range . . . . . . . . . . . . . . . .+125°C
Thermal Resistance (Typical Notes 1, 2) θJA(°C/W) θJC(°C/W)
32 Ld QFN Package . . . . . . . . . . . . . . 32 3.5
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
VCC SUPPLY CURRENT
Nominal Supply VIN Current IQ_VIN VIN = 20V; VCC = PVCC; No Load;
FSW = 500kHz 11 15 20 mA
Nominal Supply VIN Current IQ_VIN VIN = 3.3V;VCC = PVCC; No Load;
FSW = 500kHz 81214mA
Shutdown Supply PVCC Current IPVCC EN = 0V, PVCC = 5V 0.5 1 1.4 mA
Shutdown Supply VCC Current IVCC EN = 0V, VCC = 3V 7 10 12 mA
INTERNAL LINEAR REGULATOR
Maximum Current (Note 3) IPVCC PVCC = 4V TO 5.6V 250 mA
PVCC = 3V TO 4V 150 mA
Saturated Equivalent Impedance (Note 3) RLDO P-Channel MOSFET (VIN = 5V) 1 Ω
PVCC Voltage Level PVCC IPVCC = 0mA to 250mA 5.1 5.4 5.6 V
POWER-ON RESET
Rising VCC Threshold 2.85 2.97 V
Falling VCC Threshold 2.65 2.75 V
Rising PVCC Threshold ISL8120CRZ 2.85 2.97 V
ISL8120IRZ 2.85 3.05
Falling PVCC Threshold 2.65 2.75 V
System Soft-start Delay (Note 3) tSS_DLY After PLL, VCC, and PVCC PORs, and
EN(s) above their thresholds 384 Cycles
ENABLE
Turn-On Threshold Voltage 0.75 0.8 0.86 V
Hysteresis Sink Current IEN_HYS 25 30 35 µA
ISL8120
15 March 20, 2009
FN6641.0
Undervoltage Lockout Hysteresis (Note 3) VEN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V
RUP = 53.6kΩ, RDOWN = 5.23kΩ1.5 V
Sink Current IEN_SINK 15 mA
Sink Impedance REN_SINK IEN_SINK = 5mA 65 Ω
OSCILLATOR
Oscillator Frequency Range 150 1500 kHz
Oscillator Frequency RFS = 100k, Figure 21 344 377 406 kHz
Total Variation VCC = 5V; -40°C < TA <+85°C -9 +9 %
Peak-to-Peak Ramp Amplitude ΔVRAMP VCC = 5V, VEN = 0.8V 1 VP-P
Linear Gain of Ramp Over VEN GRAMP GRAMP = ΔVRAMP/VEN 1.25
Ramp Peak Voltage VRAMP_PEAK VEN = VCC VCC - 1.4 V
Peak-to-Peak Ramp Amplitude ΔVRAMP VEN = VCC = 5.4V, RUP = 2k 3 VP-P
Peak-to-Peak Ramp Amplitude ΔVRAMP VEN = VCC = 3V; RUP = 2k 0.6 VP-P
Ramp Amplitude Upon Disable ΔVRAMP VEN = 0V; VCC = 3.5V to 5.5V 1 VP-P
Ramp Amplitude Upon Disable ΔVRAMP VEN = 0V; VCC < 3.4V VCC - 2.4 VP-P
Ramp DC Offset VRAMP_OS 1V
FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP
Synchronization Frequency VCC = 5.4V (2.97V) 150 1500 kHz
PLL Locking Time VCC = 5.4V (2.97V); FSW = 400kHz;105 µs
Input Signal Duty Cycle Range (Note 3) 10 90 %
PWM
Minimum PWM OFF Time tMIN_OFF 310 345 410 ns
Current Sampling Blanking Time (Note 3) tBLANKING 175 ns
REFERENCE
Channel 1 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets) VREF1 ISL8120CRZ 0.6 V
-0.6 0.6 %
ISL8120IRZ 0.6 V
-0.7 0.7 %
Channel 2 Reference Voltage (Include
Error and Differential Amplifiers’ Offsets) VREF2 ISL8120CRZ 0.6 V
-0.75 0.75 %
ISL8120IRZ 0.6 V
-0.75 0.95 %
ERROR AMPLIFIER
DC Gain (Note 3) RL = 10k, CL = 100pF, at COMP Pin 98 dB
Unity Gain-Bandwidth (Note 3) UGBW_EA RL = 10k, CL = 100pF, at COMP Pin 80 MHz
Input Common Mode Range (Note 3) -0.2 VCC - 1.8 V
Output Voltage Swing VCC = 5V 0.85 VCC - 1.0 V
Slew Rate (Note 3) SR_EA RL = 10k, CL = 100pF, at COMP Pin 20 V/µs
Input Current (Note 3) IFB Positive Direction Into the FB pin 100 nA
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
ISL8120
16 March 20, 2009
FN6641.0
Output Sink Current ICOMP 3mA
Output Source Current ICOMP 6mA
Disable Threshold (Note 3) VVSEN- VCC - 0.4 V
DIFFERENTIAL AMPLIFIER
DC Gain (Note 3) UG_DA Unity Gain Amplifier 0 dB
Unity Gain Bandwidth (Note 3) UGBW_DA 5 MHz
Negative Input Source Current (Note 3) IVSEN- 100 nA
Maximum Source Current for Current
Sharing (Typical Application VIII) (Note 3) IVSEN1-
VSEN1- Source Current for Current
Sharing when parallel multiple modules
each of which has its own voltage loop 350 µA
Input Impedance RVSEN+_to
_VSEN- 1MΩ
Output Voltage Swing (Note 3 ) 0 VCC - 1.8 V
Input Common Mode Range (Note 3) -0.2 VCC - 1.8 V
Disable Threshold (Note 3) VVSEN- VMON1, 2 = Tri-State VCC - 0.4 V
GATE DRIVERS
Upper Drive Source Resistance RUGATE 45mA Source Current 1.0 Ω
Upper Drive Sink Resistance RUGATE 45mA Sink Current 1.0 Ω
Lower Drive Source Resistance RLGATE 45m A Source Current 1.0 Ω
Lower Drive Sink Resistance RLGATE 45mA Sink Current 0.4 Ω
OVERCURRENT PROTECTION
Channel Overcurrent Limit (Note 3) ISOURCE VCC = 2.97V to 5.6V 108 µA
Channel Overcurrent Limit ISOURCE VCC = 5V; ISL8120CRZ 94 108 122 µA
VCC = 5V; ISL8120IRZ 89 108 122 µA
Share Pin OC Threshold VOC_SET VCC = 2.97V to 5.6V
(comparator offset included) 1.16 1.20 1.22 V
Share Pin OC Hysteresis (Note 3) VOC_SET_HYS VCC = 2.97V to 5.6V
(comparator offset included) 50 mV
CURRENT SHARE
Internal Balance Accuracy (Note 3) VCC = 2.97V and 3.6V, 1% Resistor
Sense, 10mV Signal ±5 %
Internal Balance Accuracy (Note 3) VCC = 4.5V and 5.6V, 1% Resistor
Sense, 10mV Signal ±5 %
External Current Share Accuracy (Note 3) VCC = 2.97V and 5.6V, 1% Resistor
Sense, 10mV Signal ±5 %
POWER GOOD MONITOR
Undervoltage Falling Trip Point VUVF Percentage Below Reference Point -15 -13 -11 %
Undervoltage Rising Hysteresis VUVR_HYS Percentage Above UV Trip Point 4 %
Overvoltage Rising Trip Point VOVR Percentage Above Reference Point 11 13 15 %
Overvoltage Falling Hysteresis VOVF_HYS Percentage below OV Trip Point 4 %
PGOOD Low Output Voltage IPGOOD = 2mA 0.35 V
Sinking Impedance IPGOOD = 2mA 70 Ω
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
ISL8120
17 March 20, 2009
FN6641.0
Maximum Sinking Current (Note 3) VPGOOD <0.8V 10 mA
OVERVOLTAGE PROTECTION
OV Latching Up Trip Point EN/FF= UGATE = LATCH Low,
LGATE = High 118 120 122 %
OV Non-Latching Up Trip Point (Note 3) EN/FF = Low, UGATE = Low,
LGATE = High 113 %
LGATE Release Trip Point EN/FF = Low/HIGH, UGATE = Low,
LGATE = Low 87 %
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip (Note 3) 150 °C
Over-Temperature Release Threshold
(Note 3) 125 °C
NOTES:
3. Limits should be considered typical and are not production tested
4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization
and are not production tested.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 4) TYP MAX
(Note 4) UNITS
ISL8120
18 March 20, 2009
FN6641.0
Functional Pin Descriptions
GND (Pin 33)
The bottom pad is the signal and power ground plane. All
voltage levels are referenced to this pad. This pad provides a
return path for the low-side MOSFET drives and internal
power circuitries as well as all analog signals. Connect this
pad to the circuit ground with the shortest possible path
(more than 5 to 6 vias to the internal ground plane, placed on
the soldering pad are recommended).
VIN (Pin 16)
This pin is the input of the internal linear regulator. It should
be tied directly to the input rail. When used with an external
5V supply, this pin should be tied directly to PVCC. The
internal linear device is protected against reverse bias
generated by the remaining charge of the decoupling
capacitor at PVCC when losing the input rail.
VCC (Pin 26)
This pin provides bias power for the analog circuitry. An RC
filter is recommended between the connection of this pin to a
3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω
resistor. And in 3.3V applications, the R could be shorted to
allow the low end input in concerns of the VCC falling
threshold. The VCC decoupling capacitor C is strongly
recommended to be as large as a 10µF ceramic capacitor.
This pin can be powered either by the internal linear
regulator or by an external voltage source.
BOOT1, 2 (Pins 25, 17)
This pin provides the bootstrap bias for the high-side driver.
Internal bootstrap diodes connected to the PVCC pin provide
the necessary bootstrap charge. Its typical operational
voltage range is 2.5V to 5.6V.
UGATE1, UGATE2 (Pin 24, 18)
These pins provide the drive for the high-side devices and
should be connected to the MOSFETs’ gates.
PHASE1, PHASE2 (Pins 23,19)
Connect these pins to the source of the high-side MOSFETs
and the drain of the low-side MOSFETs. These pins
represent the return path for the high-side gate drives.
PVCC (Pin 21)
This pin is the output of the internal series linear regulator. It
provides the bias for both low-side and high-side drives. Its
operational voltage range is 3V to 5.6V. The decoupling
ceramic capacitor in the PVCC pin is 10µF.
LGATE1, LGATE2 (Pins 22, 20)
These pins provide the drive for the low-side devices and
should be connected to the MOSFETs’ gates.
FSYNC (Pin 5)
The oscillator switching frequency is adjusted by placi ng a
resistor (RFS) from this pin to GND. The internal oscillator
will lock to an external frequency source if this pin is
connected to a switching square pulse waveform, typically
the CLKOUT input signal from another ISL8120 or an
external clock. The internal oscillator synchronizes with the
leading edge of the input signal.
EN/FF1, EN/FF2 (Pins 4, 6)
These pins have triple functions. The voltage on EN/FF_ pin
is compared with a precision 0.8V threshold for system
enable to initiate soft-start. With a voltage lower than the
threshold, the corresponding channel can be disabled
independently. By connecting these pins to the input rail
through a voltage resistor divider, the input voltage can be
monitored for UVLO (undervoltage lockout ) function. The
undervoltage lockout and its hysteresis levels can be
programmed by these resistor dividers. The voltages on
these pins are also fed into the controller to adjust the
sawtooth amplitude of each channel independently to realize
the feed-forward function.
Furthermore, during fault (such as overvolt age, overcurre nt,
and over-temperature) conditions, these pins (EN/FF_) are
pulled low to communica te the information to other cascade d
ICs.
PGOOD (Pin 8)
Provides an open drain Power-Good signal when both
channels are within 9% of the nominal output regulation
point with 4% hysteresis (13%/9%) and soft-start complete.
PGOOD monitors the outputs (VMON1/2) of the internal
differential amplifiers.
ISEN1A, ISEN2A (Pins 27, 15)
These pins are the non-inverting (+) inputs of the current
sensing amplifiers to provide rDS(ON), DCR, or precisio n
resistor current sensing together with the ISEN1B, ISEN2B
pins.
ISEN1B, ISEN2B (Pins 28, 14)
These pins are the inverting (-) inputs of the current sensing
amplifiers to provide rDS(ON), DCR, or precision resistor
current sensing together with the ISEN1A, ISEN2A pins.
Refer to “Typical Application III (2-Phase Operation with
rDS(ON) Sensing and Voltage Trimming)” on page 7 for
rDS(ON) sensing set up and “ Typical Application V (4 Phase
Operation with DCR Sensing)” on page 9 for DCR sensing
set up.
ISET (Pin 2)
This pin sources a 15µA offset current plus the average current
of both channels in multiphase mode or only Channel 1’s
current in independent mode. The voltage (VISET) set by an
external resistor (RISET) represents the average current level of
the local active channel(s).
ISHARE (Pin 3)
This pin is used for current sharing purposes and is
configured to current share bus representing all module s ’
ISL8120
19 March 20, 2009
FN6641.0
average current. It sources 15µA offset current plus the
average current of both channels in multiphase mode or
Channel 1’s current in independent mode. The share bus
(ISHARE pins connected together) voltage (VISHARE) set by
an external resistor (RISHARE) represents the average
current level of all active channel(s). The ISHARE bus
voltage compares with each reference voltage set by each
RISET and generates current share error signal for current
correction block of each cascaded controller. The share bus
impedance RISHARE should be set as RISET/NCTRL (RISET
divided by number of active current sharing controllers).
There is a 1.2V threshold for average overcurrent protection
on this pin. VISHARE is compare d wi t h a 1. 2V threshold for
average overcurrent protections. For full-scale current,
RISHARE should be 1.2V/123µA = ~10kΩ. Typically 10kΩ is
used for RSHARE and RSET.
CLKOUT/REFIN (Pin 7)
This pin has a dual function depending on the mode in which
the chip is operating. It provides a clock signal to
synchronize with other ISL8120(s) with its VSEN2- pulled
within 700mV of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or
12-phase) operation. When the VSEN2- pin is not within
700mV of VCC, ISL8120 is in dual mode (dual independent
PWM output). The clockout signal of this pin is not available
in this mode, but the ISL8120 can be synchronized to
external clock. In dual mode, this pin works as th e following
two functions:
1. An external reference (0.6V target only) can be in place
of the Channel 2’s internal reference through this pin for
DDR/tracking applications (see “Internal Reference and
System Accuracy” on pag e 33).
2. The ISL8120 operates as a dual-PWM controller for two
independent regulators with selectable phase degree
shift, which is programmed by the voltage level on REFIN
(see “DDR and Dual Mode Operation” on page 32).
FB1, FB2 (Pins 32, 10)
These pins are the inverting inp uts of the error amplifiers.
These pins should be connected to VMON1, 2 with the
compensation feedback network. No direct connection
between FB and VMON pins is allowed. With VSEN2- pulled
within 700mV of VCC, the corresponding error amplifier is
disabled and the amplifier’s output is high impedance. FB2 is
one of the two pins to determine the relati ve phase
relationship between the internal clock of both channels and
the CLKOUT signal. See “DDR and Dual Mode Operation”
on page 32.
COMP1, COMP2 (Pins 1, 9)
These pins are the error amplifier outputs. They should be
connected to FB1, FB2 pins through desired compensation
networks when both channels are operating independently.
When VSEN1-, VSEN2- are pulled within 700mV of VCC,
the corresponding error amplifier is disabled and its output
(COMP pin) is high impedance. Thus, in multiphase
operations, all other SLAVE phases ’ COMP pins can tie to
the MASTER phase’s COMP1 pin (1st phase), which
modulates each phase’s PWM pulse with a single voltage
feedback loop. While the error amplifi er is no t disabled, an
independent compensation network is required for each
cascaded IC.
VSEN1+, VSEN2+ (Pins 29, 13)
These pins are the positive inputs of the standard unity gain
operational amplifier for differential remote sense for the
corresponding channel (Channels 1 and 2), and should be
connected to the positive rail of the load/processor. Th ese
pins can also provide precisio n output voltage trimming
capability by pulling a resistor from this pin to the positive rail
of the load (trimming down) or the return (typical VSEN1-,
VSEN2- pins) of the load (trimming up). The typical input
impedance of VSEN+ with respect to VSEN- is 500kΩ. By
setting the resistor divider connected from the output voltage
to the input of th e differentia l amplifier, the desired output
voltage can be programmed. To minimize the system
accuracy error introduced by the input impe dance of the
differential amplifier, a resistor below 1k is recommended to
be used for the lower leg (ROS) of the feedba ck resistor
divider.
With VSEN2- pulled within 700mV of VCC, the
corresponding error amplifier is disabled and VSEN2+ is one
of the two pins to determine th e relative phase relationship
between the internal clock of both channels and the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 32 for details.
VSEN1-, VSEN2- (Pins 30, 12)
These pins are the negative inputs of standard unity gain
operational amplifier for differential remote sense for the
corresponding regulator (Channels 1and 2), and should be
connected to the negative rail of the load/processor.
When VSEN1-, VSEN2- are pulled within 700mV of VCC,
the corresponding error amplifier and differential amplifier
are disabled and their outputs are high impedance. Both
VSEN2+ and FB2 input signal levels determine the relative
phases between the internal controllers as well as the
CLKOUT signal. See “DDR and Dual Mode Operation” on
page 32 for details.
When configured as multiple power modules (each modu le
with independent voltage loop) operating in parallel, in order
to implement the current sharing control, a resistor (100Ω
typ) needs to be inserted between the VSEN1- pin and the
output voltage negative sense point (between VSEN1- and
lower voltage sense resistor), as shown in the “Typical
Application VIII (Multiple Power Modules in Parallel with
Current Sharing Control)” on page 11. This introduces a
correction voltage for the modules with lower load current to
keep the current distribution balanced among modules. The
module with the highest load current will automaticall y
become the master module. The recommended value for the
ISL8120
20 March 20, 2009
FN6641.0
VSEN1- resistor is 100Ω and it should not be large in order
to keep the unit gain amplifier input impedance compatibility.
VMON1, VMON2 (Pins 31, 11)
These pins are outputs of the unity gain amplifiers. They are
connected internally to the OV/UV/PGOOD comp ara tors.
These pins should be connected to the FB1, FB2 pins by a
standard fee dback network when both channels are operating
independently. When VSEN1-, VSEN2- are pulled within
700mV of VCC, the corresponding dif ferenti al amplifier is
disabled and it s output (VMON pin) is high imp edance. In
such an event, the VMON pin can be used as an additional
monitor of the output vol t age wi th a resistor divider to pro tect
the system against single point of failure, which occurs in the
system using the same resistor divider for both of th e UV/OV
comparator and output vol t age feed back.
Modes of Operation
There are 9 typical operation modes depen ding upon the
signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-,
FB2, and CLKOUT/REFIN.
MODE 1: The IC is completely disabled when EN1/FF1 and
EN2/FF2 are pulled below 0.8V.
MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high
(Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low
(Mode 2B), the ISL8120 operates as a single phase
regulator. The current sourcing out from the ISHARE pin
represents the first channel current plus 15µA offset current.
MODE 3: When VSEN2- is used as a negative sense line,
both channels’ phase shift depends upon the voltage level of
CLKOUT/REFIN. When the CLKOUT/REFIN pin is within
29% to 45% of VCC, Channel 2 delays 0° over Channel 1
(Mode 3A); when within 45% to 62% of VCC, 90°delay
(Mode 3B); when greater than 62% to VCC, 180° delay
(Mode 3C). Refer to the “DDR and Dual Mode Operation” on
page 32.
MODE 4: When VSEN2- is used as a negative remote sense
line, and CLKOUT/REFIN is connected to an external
voltage ramp lower than the internal soft-start ramp and
lower than 0.6V, the external ramp signal will replace
Channel 2’s internal soft-st art ramp to be tracked at st art-up,
controller operating in DDR mode. The controller will use the
lowest voltage among the internal 0.6V reference, the
external voltage in CLKOUT/REFIN pin and the soft-start
ramp signal. Channel 1 is delayed 60° behind Channel 2.
Refer to the “DDR and Dual Mode Operation” on page 32.
MODE 5: With VSEN2- pulled within 700mV of VCC and
FB2 pulled to ground, the internal channels are 180°
out-of-phase and operate in 2-phase single output mode
(5A). The CLKOUT/REFIN pin (rising edge) also signals out
clock with 60° phase shift relative to the Channel 1’s clock
signal (falling edge of PWM) for 6-phase operation with two
other ISL8120s (5B). When the share pins are not
connected to each other for the three ICs in sync, two of
which can operate in Mode 5A (3 independent outputs can
be generated (Mode 5D)) and Modes 3 and 4 (to generate 4
independent outp uts (Mode 5C)) respectively.
MODE 6: With VSEN2- pulled within 700mV of VCC, FB2
pulled high and VSEN2+ pulled low, the internal channels
(as 1st and 3rd Phase, respectively) are 240° out-of-phase
and operate in 3-phase single ou tput mode, combined with
another ISL8120 at MODE 2B. The CLKOUT/REFIN pin
signals out 120° relative phases to the falling edge of
Channel 1’s clock signal to synchronize with the second
ISL8120’s Channel 1 (as 2nd Phase).
MODE 7: With VSEN2- pulled within 700mV of VCC and
FB2 and VSEN2+ pulled high, the internal channel is 180°
out-of-phase. The CLKOUT/REFIN pin (rising edge) signals
out 90° relative phase to the Channel 1’s clock signal (falling
edge of PWM) to synchronize with another ISL8120, which
can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output
converter can be constructed with two ISL8120s operating in
Mode 5A or 7A (Mode 7A). If the share bus is not connected
between ICs, each IC could generate an independent output
(Mode 7B). When the second ISL8120 operates as two
independent regulators (Mode 3) or in DDR mode (Mode 4),
then a three independent output system is generated (Mode
7C). Both ICs can also be constructed as a 3-phase
converter (0°, 90°, and 180°, not a equal phase shift for
3-phase) with a single phase regulator (270°).
MODE 8: The output CLKOUT signal allows expansion for
12-phase operation with the cascad ed sequencing, as
shown in Table 1. No external clock is required in this mode
for the desired phase shift.
MODE 9: With an external clock, the part can be expa nded
for 5, 7, 8, 9 10 and 11 phase single output operation with
the desired phase shift.
ISL8120
21 March 20, 2009
FN6641.0
TABLE 1.
1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, Bi-DIRECTION) MODES OF OPERATION
OUTPUT (See
Description
for Details)
OPERATION
MODE
of 2ND IC
OPERATION
MODE
of 3RD ICMODE
EN1/
FF1
(I)
EN2/
FF2
(I) VSEN2-
(I) FB2 (I) VSEN2
+ (I)
CLKOUT/REFIN
WRT 1ST
(I or O)
ISHARE (I/O)
REPRESENTS
WHICH
CHANNEL(S)
CURRENT 2ND CHANNEL
WRT 1ST (O)*
100 - - -- - - - - DISABLED
2A 0 1 ACTIVE ACTIVE ACTIVE - N/A VMON1 =
VMON2 to Keep
PGOOD Valid
--SINGLE
PHASE
2B 1 0 - - - - 1ST CHANNEL VMON1 =
VMON2 to Keep
PGOOD Valid
--SINGLE
PHASE
3A - - <VCC -
0.7V ACTIVE ACTIVE 29% to 45% of
VCC (I) 1ST CHANNEL 0° - - DUAL
REGULATOR
3B - - <VCC -
0.7V ACTIVE ACTIVE 45% to 62% of
VCC (I) 1ST CHANNEL 90° - - DUAL
REGULATOR
3C - - <VCC -
0.7V ACTIVE ACTIVE > 62% of VCC (I) 1ST CHANNEL 180° - - DUAL
REGULATOR
4 - - <VCC-
0.7V ACTIVE ACTIVE < 29% of VCC (I) 1ST CHANNEL -60° - - DDR MODE
5A - - VCC GND - 60° BOTH CHANNELS 180° - - 2-PHASE
5B - - VCC GND - 60° BOTH CHANNELS 180° 5A 5A or 7A 6-PHASE
5C - - VCC GND - 60° BOTH CHANNELS 180° 5A 5A or 7A 3 OUTPUTs
5D - - VCC GND - 60° BOTH CHANNELS 180° 5A 3 or 4 4 OUTPUTs
6 - - VCC VCC GND 120° BOTH CHANNELS 240° 2B - 3-PHASE
7A - - VCC VCC VCC 90° BOTH CHANNELS 180° 5A or 7A - 4-PHASE
7B - - VCC VCC VCC 90° BOTH CHANNELS 180° 5A or 7A - 2 OUTPUTs
(1st IC in Mode
7A)
7C - - VCC VCC VCC 90° BOTH CHANNELS 180° 3, 4 - 3 OUTPUTs
(1st IC in Mode
7A)
8 Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required 12-PHASE
9 External Clock or External Logic Circuits Required for Equal Phase Interval 5, 7, 8, 9, 10,
11, or (PHASE
>12)
NOTE: “2ND CHANNEL WRT 1ST” is referred to as “channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells”.
For example, 90° with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90 degree; -60° with 2ND CHANNEL WRT 1ST means channel 2
leads channel 1 by 60 degree.
ISL8120
22 March 20, 2009
FN6641.0
VSEN2- VSEN2+ VMON2
UV/OV
700mV
VCC
FIGURE 3. SIMPLIFIED RELATIVE PHASES CONTROL
DIFF ERROR
AMP2 COMP2 AMP2
COMP2
CHANNEL 1
PWM CONTROL
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
VREF2 = VREF
FB2
CLOCK GENERATOR
AND
RELATIVE PHASES CONTROL
CLKOUT/REFIN
CH1 UG (1ST IC)
D 1-D
CLKOUT (1ST IC)
CH2 UG (1ST IC)
CH2 UG (2ND IC)
50%
D
D
180°
D
CH1 UG (2ND IC)
90°
180°
CH1 UG (1ST IC)
D 1-D
CLKOUT (1ST IC)
CH2 UG (1ST IC)
CH2 UG(2ND IC, OFF, EN2/FF2 = 0)
50%
D
240°
CH1 UG (2ND IC)
120°
3-PHASE TIMING DIAGRAM (MODE 6)
D 1-D
120°
90°
4 PHASE TIMING DIAGRAM (MODE 7A)
ISL8120
23 March 20, 2009
FN6641.0
Functional Description
Initialization
Initially, the ISL8120 Power-On Rese t (POR) circuits
continually monito r the bias voltages (PVCC and VCC) and
the voltage at the EN pin. The POR function initiate s
soft-st art operation 384 clock cycles after the EN pin volt age
is pulled to be above 0.8V, all input supplies exceed their
POR thresholds and the PLL locking time expires, as shown
in Figure 4. The enable pin can be used as a voltage monitor
and to set desired hysteresis with an internal 30µA sinking
current going through an external resistor divider. The
sinking current is disengaged after the system is enabled.
This feature is especially designed for applications that
require higher input rail POR for better undervoltage
protection. For example, in 12V applications, RUP = 53.6k
and RDOWN = 5.23k will set the turn-on threshold
(VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V,
with 1.6V hysteresis (VEN_HYS).
During shutdow n or fault condition s, the sof t-st art is reset
quickly while UGATE and LGATE change states immediately
(<100ns) upon the input drop below falling POR.
Voltage Feed-forward
Other than used as a voltage monitor described in the
previous section, the voltages applied to the EN/FF pins are
also fed to adjust the amplitude of each channel’s individual
sawtooth. The amplitude of each channel’s sawtooth is set to
1.25 times the corresponding EN/FF voltage upon its enable
(above 0.8V). This helps to maintain a constant gain
( ) contributed by the modulator
and the input voltage to achieve optimum loop response
over a wide input voltage range. The sawtooth ramp offset
voltage is 1V (equal to 0.8V*1.25), and the peak of the
sawtooth is limited to VCC - 1.4V. With VCC = 5.4V, the
ramp has a maximum peak-to-peak amplitude of VCC - 2.4V
(equal to 3V); so the feed-forward voltage effective range is
typically 3x as the ramp amplitude ranges from 1V to 3V.
A 384 cycle delay is added after the system reaches its
rising POR and prior to the soft-start. The RC timing at the
EN/FF pin should be sufficiently small to ensure that the
input bus reaches its static state and the internal ramp
circuitry stabilizes before soft-start. A large RC could cause
the internal ramp amplitude not to synchronize with the input
bus voltage during output start-up or when recovering from
faults. It is recommended to use open drain or open collector
to gate this pin for any system delay, as shown in Figure 5.
The multiphase system can immediately turn off all ICs
under fault conditions of one or more phases by pulling all
EN/FF pins low. Thus, no bouncing occurs among channels
at fault and no single phase could carry all current and be
over stressed.
FIGURE 4. SOFT-START INITIALIZATION LOGIC
VCC POR
PVCC POR
EN1/FF1 POR
SOFT-START
HIGH = ABOVE POR; LOW = BELOW POR
OF CHANNEL 1
AND 384
VCC POR
PVCC POR
EN2/FF2 POR
SOFT-START
OF CHANNEL 2
AND
PLL LOCKING
Cycles
384
Cycles
FIGURE 5. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT
0.8V
IEN_HYS = 30µA
RUP
RDOWN
SOFT-START
RDOWN
RUP V•EN_REF
VEN_FTH VEN_REF
–
---------------------------------------------------------------
=
VEN_FTH VEN_RTH VEN_HYS
–=
VIN
GRAMP = 1.25
LIMITER SAWTOOTH
AMPLITUDE
VΔRAMP LIMIT(VCC_FF GRAMP, VCC - 1.4V - VRAMP_OFFSET)×=
(ΔVRAMP)
EN/FF
OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1)
RUP VEN_HYS
IEN_HYS
-----------------------------
=
SYSTEM DELAY
VCC_FF
VCC
0.8V
∑
VRAMP_OFFSET = 1.0V
VCC - 1.4V
LOWER LIMIT
UPPER LIMIT
(RAMP OFFSET)
384 Clock
Cycles
GMVIN DMAX ΔVRAMP
⁄⋅=
ISL8120
24 March 20, 2009
FN6641.0
While EN/FF is pulled to ground, a constant voltage (0.8V) is
fed into the ramp generator to maintain a minimum
peak-to-peak ramp.
Since the EN/FF pins are pulled down under fault conditions,
the pull-up resistor (RUP) should be scaled to sink no more
than 5mA current from EN/FF pin. Essentia lly, the EN/FF
pins cannot be directly connected to VCC.
Soft-start
The ISL8120 has two independent digital soft-start circuitry
with fixed 1280 switching cycles. The soft-st a rt time is
inversely proportional to the switching freque ncy and is
determined by the 1280-cycle digital counter. Refer to
Figure 7. The full soft-start time from 0V to 0.6V can be
estimated using Equation 1.
The ISL8120 has the ability to work under a pre-charged
output (see Figure 8). The output voltage would not be
yanked down during pre-charged start-up. If the pre-charged
output voltage is greater than the final target level but prior to
113% setpoint, the switching will not start until the output
voltage reduces to the target voltage and the first PWM
pulse is generated (see Figure 9). The maximum allowable
pre-charged level is 113%. If the pre-charged level is above
113% but below 120%, the output will hiccup between 113%
(LGATE turns on) and 87% (LGATE turns off) while EN/FF is
pulled low. If the pre-charged load voltage is above 120% of
the targeted output voltage, then the controller will be
latched off and not be able to power-up.
For above-target level pre-ch arged start-up, the output
voltage would not change until the end of the soft-start. If the
initial dip is below the UV level, the LGATE could be turned
off. In such an event, the body-diode drop of the low-side
FET will be sensed and could potentiality cause an OCP
event for rDS(ON) current sensing applications.
Power-Good
FIGURE 6. TYPICAL 4-PHASE WITH FAULT HANDSHAKE
EN/FF1
EN/FF2
2-PHASE
EN/FF1
EN/FF2
2-PHASE
ISL8120 ISL8120
RUP
RDOWN
VIN
RUP VEN_HYS
IEN_HYS NPHASE
⋅
----------------------------------------------------------
=
tSS 1280
fSW
-------------
=(EQ. 1)
VOUT
0.0V
tSS 1280
FSW
-------------
=
FIRST PWM PULSE
-100mV
tSS_DLY 384
FSW
------------
≈
FIGURE 7. SOFT-START WITH VOUT = 0V
SS Settling at VREF + 100mV
UV VOUT
FIRST PWM PULSE
-100mV
SS Settling at VREF + 100mV
FIGURE 8. SOFT-START WITH VOUT = UV
OV = 113%
VOUT TARGET VOLTAGE
FIRST PWM PULSE
FIGURE 9. SOFT -START WITH VOUT BELOW OV BUT
ABOVE FINAL TARGET VOLTAGE
FIGURE 10. POWER-GOOD THRESHOLD WINDOW
-13%
-9%
VREF
+9%
+13%
VMON1, 2
CHANNEL 2 UV/OV
END OF SS1
AND
PGOOD
CHANNEL 1 UV/OV
END OF SS2 OR
+20%
PGOOD PGOOD latch off after 120% OV
SS1_PERIOD
AND
SS2_PERIOD
ISL8120
25 March 20, 2009
FN6641.0
Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulatio n will pull-down the
PGOOD pin. The Power-Good comparators monitor the
voltage on the VMON pins. The trip points are shown in
Figure 10. PGOOD will not be asserted until after the
completion of the soft-start cycle of both channels. If
Channels 1 or 2 are not used, the Power-Good can stay in
operation by connecting 2 channels’ VMON pins together.
The PGOOD pulls low upon both EN/FF’s disabling it if one
of the VMON pins’ voltage is out of the threshold window.
PGOOD will not pull low until the fault presents for three
consecutive clock cycles. In Dual/DDR application, if the
turn-off channel pre-charges its VMON within the PGOOD
threshold window, it could indicate Powe r-Good, however,
the PGOOD signal can pull low with an external PNP or
PMOS transistor via the EN/FF of the corresponding off
channel.
Overvoltage and Undervoltage Protection
The Overvoltage (OV) and Undervoltage (UV) protection
circuitry monitor the voltage on the VMON pins.
OV protection is active from the beginning of soft-start. An
OV condition (>120%) would latch IC off (the high-side
MOSFET to latch off permanently; the low-side MOSFET
turns on immediately at the time of OV trip and then turns off
permanently after the output voltage drops below 87%). The
EN/FF and PGOOD are also latched low at OV event. The
latch condition can be reset only by recycling VCC. In
Dual/DDR mode, each channel is responsible for its own OV
event with the corresponding VMON as the monitor. In
multiphase mode, both channels respond simultaneously
when either triggers an OV event.
There is another non-latch OV protection (113% of target
level). At the condition of EN/FF low and the output over
113% OV, the lower side MOSFET will turn on until the
output drops below 87%. This is to protect the overall power
trains in case of only one channel of a multiphase system
detecting OV. The low-si de MOSF ET always turns on at the
conditions of EN/FF = LOW and the output voltage above
113% (all VMON pins and EN pins are tied together) and
turns off after the outp ut drops below 87%. Thus, in a high
phase count application (Multiphase Mode), al l cascaded
ICs can latch off simultaneously via the EN pins (EN pins are
tied together in multiphase mode), and each IC shares the
same sink current to reduce the stress and eliminate the
bouncing among phases.
The UV functionality is not enabled until the end of soft-start.
In a UV event, if the output drops below -13% of the target
level due to some reason (cases when EN/FF is not pulled
low) other than OV, OC, OT, and PLL faults, the lower
MOSFETs will turn off to avoid any negative voltage ringing.
PRE-POR Overvoltage Protection (PRE-POR-OVP)
When both the VCC and PVCC are below PORs (not
including EN POR), the UGA T E is low and LGATE is floating
(high impedance). EN/FF has no control on LGATE when
below PORs. When above PORs, the LGATE would not be
floating but toggling with its PWM pulses. An internal 10kΩ
resistor, connected in between PHASE and LGATE nodes,
implements the PRE-POR-OVP circuit. The output of the
converter that is equal to phase node voltage via output
inductors is then effectively clamped to the low-side
MOSFET’s gate threshold voltage, which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during start-up, shutdown, or normal operations. For
complete protect io n , the l ow -si d e MOS FET shou ld hav e a
gate threshold that is much smaller than the maximum
voltage rating of the load.
The PRE-POR-OVP works against pre-biased start-up when
pre-charged output voltage is higher than the threshold of
the low-side MOSFET, however, it can be disabled by
placing a 2k resistor from LGATE to ground.
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than
+150°C (typically), both EN/FF pins pull low to inform other
cascaded channels via their EN/FF pins. All connected
EN/FFs stay low and release after the IC’s junction
temperature drops below +125°C (typically), with a +25°C
hysteresis (typical).
FIGURE 11. FORCE LGATE HIGH LOGIC
EN/FF1
FORCE
VMON1
LGATE1
HIGH
113%
87%
EN/FF2
FORCE
VMON2
LGATE2
HIGH
113%
87%
VMON1>120%
VMON2 > 120%
multiphase
MODE = HIGH
OR
OR
OR
AND
AND
AND
FIGURE 12. PGOOD TIMING UNDER UV AND OV
UV OV LATCH
3 CYCLES
VOUT
PGOOD
UGATE AND EN/FF LATCH LOW
3 CYCLES
120%
ISL8120
26 March 20, 2009
FN6641.0
Current Loop
When the ISL8120 operates in 2-ph ase mode, the current
control loop keeps the channel’s current in balance. After
175ns blanking period with respect to the falling edge of the
PWM pulse of each channel, the voltage developed across
the DCR of the inductor, rDS(ON) of the low-side MOSFETs,
or a precision resistor , is filtered and sampled for 175ns. The
current (ICS1/ICS2) is scaled by the RISEN resistor and
provides feedback proportional to the average output current
of each channel.
For DCR sensing, the sampling current ICS can be derived
from Equation 2:
where IL is the inductor DC current, DCR is its DC
resistance, and tMIN_OFF is 350ns.
For low-side MOSFET rDS(ON) sensing, the ICS can be
derived from Equation 3:
In multiphase mode (VSEN2- pulled high), the scaled output
currents from both active channels are combined to create
an average current reference (IAVG) which represents
average current of both channel outputs as calculated in
Equation 4.
ISEN1B
ISEN1A
700mV
VCC DCR1 DCR2
AMP AMP
VSEN2-
∑
+
+
ISHARE
ICS2
ICS1
CURRENT
SHARE
BLOCK
IAVG
CURRENT
CORRECTION
BLOCK
CURRENT
CORRECTION
BLOCK
VSEN2+
∑
2
+
-
CHANNEL 1
PWM CONTROL
BLOCK
CHANNEL
2
PWM CONTROL
BLOCK
CHANNEL 1
SOFT-START &
CHANNEL 2
SOFT-START &
FAULT LOGIC
AVG_OC
COMP OC2
COMP
FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION
ITRIP=108µA
ICSH_ERR
--
-
+
IAVG_CS
VISHARE
ISET
1.2V
RISET
ICSH_ERR = (VISARE - VISET)/GCS
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
7 CYCLES
DELAY
ITRIP=108μA
7 CYCLES
DELAY
E/A
ISEN2B
ISEN2A
RC
RISEN2
VOUT
PHASE2 IOUT2
DCR2 L2
FAULT LOGIC
CHANNEL 1
CHANNEL 2
R
C
RISEN1
VOUT PHASE1
IOUT1
DCR1
L1
VOUT PHASE1
IOUT1
L1
ISEN1A
DCR SENSING
RISEN1
ISEN1B
DCR1
rDS(ON) SENSING
OC1
COMP
IAVG_CS +15µA
IAVG_CS +15µA
ICS
IL VOUT
L
----------------1D–
2FSW
---------------- tMIN_OFF
–
⎝⎠
⎛⎞
•+
⎝⎠
⎜⎟
⎛⎞
DCR•
RISEN
-----------------------------------------------------------------------------------------------------------------
=(EQ. 2)
ICS
IL VOUT
L
----------------1D–
2FSW
---------------- tMIN_OFF
–
⎝⎠
⎛⎞
•+
⎝⎠
⎜⎟
⎛⎞
rDS ON()
•
RISEN
--------------------------------------------------------------------------------------------------------------------------
=
(EQ. 3)
IAVG ICS1 ICS2+
2
-----------------------------------
=(EQ. 4)
ISL8120
27 March 20, 2009
FN6641.0
The signal IAVG is then subtracted from the individual
channel’s scaled current (ICS1 or ICS2) to produce a current
correction signal for each channel. The current correction
signal keeps each channel’s output current contribution
balanced relative to the other active channel.
For multiphase operation, th e share bus (VISHARE)
represents the average current of all active channels and
compares with each IC’s average current (IAVG_CS equals to
IAVG or ICS1 depending upon the configuration, represented
by VISET) to generate current share error signal (ICS_ERR)
for each individual channel. Each current correction signal is
then subtracted from the error amplifier output and fed to the
individual channel PWM circuits.
When both channels operate independently, the average
function is disabled and generates zero average current
(IAVG = 0), and the current correction block of Channel 2 is
also disabled. The IAVG_CS is the Channel 1 current ICS1.
The Channel 1 makes any necessary curren t correction by
comparing its channel current (represented by VISET) with
the share bus (VISHARE). When the share bus does not
connect to other ICs, the ISET and ISHARE pins can be
shorted together and grounded via a single resistor to
ensure zero share error.
Note that the common mode input voltage range of the
current sense amplifiers is VCC - 1.8V. Therefore, the
rDS(ON) sensing should be used for applications with output
voltage greater than VCC - 1.8V. For example, an
application of 3.3V output is suggested to use rDS(ON)
sensing.
In addition, the R-C network components (for DCR sensing)
are selected such that the RC time cons tant matches the
inductor L/DCR time constant. Otherwise, it could cause
undershoot/overshoot during load transient and start-up. C is
typically set to 0.1µF or higher, while R is calculated with
Equation 5.
Figure 13 shows a simple and flexible configuration for both
rDS(ON) and DCR sensing.
Current Share Control in Multiphase Single Output
The IAVG_CS is the average current of both channels (IAVG,
2-phase mode) or only Channel 1 (ICS1, any oth er modes).
ISHARE and ISET pins source a copy of IAVG_CS with 15µA
offset, for example, the full-scale will be 123µA. If one single
external resistor is used as RISHARE connecting the
ISHARE bus to ground for all the ICs in parallel, RISHARE
should be set equal to RISET/NCTRL (where NCNTL is the
number of the ISL8120 controllers in parallel or multiphase
operations), and the share bus voltage (VISHARE) set by the
RISHARE represents the average current of all active
channels. Another way to set RISHARE is to put one resistor
in each IC’ s ISHARE pin and use the same value with
RISET ( RISHARE = RISET), in which case the total
equivalent resistance value is also RISET/NCTRL. The
voltage (VISET) set by RISET represents the average current
of the corresponding device and compared with the share
bus (VISHARE). The current share error signal (ICSH_ERR) is
then fed into the current correction block to adjust each
channel’s PWM pulse accordingly.
The current share function prov ides at least 10% overall
accuracy between ICs, 5% within the IC when using a 1%
resistor to sense a 10mV signal. The current share bus
works for up to 12-phase.
RL
CDCR•
------------------------
=(EQ. 5)
FIGURE 14. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION
ISHARE
CURRENT
MIRROR
BLOCK
IAVG_CS
ISET
VERROR1
+
-
ICS1
∑
-
∑
ERROR
AMP 1
VERROR2
+
-
ICS2
∑
-
∑
ERROR
AMP 2
CURRENT
MIRROR
BLOCK
IAVG_CS
700mV
VCC
VSEN2-
--
+
+
I
CSH_ERR
ICSH_ERR
SHARE BUS
RISET
RISHARE
RISHARE=RISET/NCTRL
IDROOP + 15
µ
A = IAVG_CS + 15
µ
A = ISET = ISHARE
IAVG_CS = IAVG or ICS1
IAVG = (ICS1 + ICS2) / 2
ISL8120
28 March 20, 2009
FN6641.0
For multiphase implementation, one single error amplifier
should be used for the voltage loop. Therefore, all other
channels’ error amplifiers should be disabled with their
corresponding VSEN- pulled to VCC, as shown in Figure 16.
Current Share Control Loop in Multi-Module with
Independent Voltage Loop
The power module controlled by ISL8120 with its own
voltage loop can be paralleled to supply one common output
load with its integrated Master-Slave current sharing control,
as shown in “Typical Application VIII (Multiple Power
Modules in Parallel with Current Sharing Control)” on
page 11. A resistor RCSR needs to be inserted between
VSEN1- pin and the lower resistor of the voltage sense
resistor divider for each module. With this resistor, the
correction current sourcing from VSEN1- pin will create a
voltage offset to maintain even current sharing among
modules. The recommended value for the VSEN1- resistor
RCSR is 100Ω and it should not be large in order to keep the
unity gain amplifier input pin impe dance compatibility. The
maximum source current from VSEN1- pin is 350µA, which
is combined with RCSR to determine the current sharing
regulation range. The generated correction voltage on RCSR
is suggested to be within 5% of VREF (0.6V) to avoid fault
triggering of UV/OV and PGOOD during dyn amic events.
There are basically two options for the configuration of the
communication wires between the modules. Each of option
has its own unique features.
One option is to synchronize all the modules where the
system has 3 analog signal communication wires (CLKOUT-
SYNC, ISHARE, EN/FF). In this option, all the modules are
synchronized and the phase shift can also be configured to
optimal to reduce the input current rippl e by interleaving
effects. The connections of these three wires allows the
system to be started at the same time and achieve good
current balance in start-up without overcurrent trip. To have
different phase shift, each module has different circuitry
configuration to program the ph ase shift, thus to make only
one standard module is difficult.
1k
R1 R3
3.3k
R2
10k 10k
R4
Q1 Q2 Q3
COMP ISHARE BUS
VCC
GND
ISL8120
ISHARE
Q1: MMBT3904
Q2: MMBT3904
Q3: 2N7002
MODULE 1
1k
R1 R3
3.3k
R2
10k 10k
R4
Q1 Q2 Q3
COMP ISHARE BUS
VCC
GND
ISL8120
ISHARE
MODULE 2
GND
GND
VOUT
GND
FIGURE 15. SINGLE COMMUNICATION WIRE CONNECTION
ISL8120
29 March 20, 2009
FN6641.0
The second option for multi-module parallel system is to
have only one signal (ISHARE) wire connection. The signal
wire connection scheme is targeted for a N+1 system, where
each module is a standard one that can be paralleled to build
up power systems with different capacity, and each module
can start-up at different time, and each module can be shut
down and removed without the system shutdown. Figure 15
shows some extra circuits needed for such a parallel module
system (each module with independant voltage feedback
loop where only one analog signal (ISHARE) wire is
connected between the module) besides the circuits shown
in “Typical Application VIIII (4 Outputs Operation with DCR
Sensing)” on page 13. The circuitry shown in Figure 15 is to
ensure the successful start-up of the system with the
individual module starting up at different time. With this
circuitry, each module’s local ISHARE signal is connected to
the system share bus only when it starts switching (finishing
of pre-biased start-up). In addition, when the module is shut
off, its ISHARE signal will be removed from the ISHARE bus.
The validated signal transistors shown in Fi gure 15 are:
MMBT3904 for Q1 and Q2; 2N7002 for Q3.
With the circuits of Figure 15 implemented, the system can
also be further implemented with the CLKOUT-SYNC
connection to have the modules synchornized and phase-
shifted, which is the third option of system configuration.
However, the lose of CLKOUT signal will caus e the
shutdown of the other module receiving the signal.
Compared with the second option (single wire (ISHARE)
connection), this option has one more wire connection, but
all the modules are synchronized and phase-shifted.
In summary, the communication wire connection in parallel
systems offers flexibility. Each co nfiguration option has its
own unique features. The selection of the connections of the
conmmunication wire should be based up on evaluation of
the priorities of system requirements and features, such as
reliability, number of wire connections, synchronizations and
fault tolerance, etc.
In dual mode, the current sharing block for current sharing of
modules with independant voltage loop is disabled.
Overcurrent Protection
The OCP function is enabled at start-up. When both
channels operate independently, the av erage function is
disabled and generates zero average current (IAVG = 0).
The Channel 2 current (ICS2) is compared with ITRIP
(108µA) as its own independent overcurrent protectio n and
the 7 clock cycles delay is bypassed. The Channel 1’s
current (ICS1) plus 15µA offset forms a voltage (VISHARE)
with an external resistor RISHARE and compares with a
precision 1.2V threshold for OCP; while the 108µA OCP
comparator with 7-cycle delay is also activated.
In multiphase operation, the VISHARE represents the average
current of all active channels and compares with the ISHARE
pin precision 1.2V threshold to determine the overcurrent
condition. At the same time, each channel has additional
overcurrent trip point at 108µA with 7-cycle delay for phase
overcurrent protection. This scheme helps protect against loss
of channel(s) in multi-phase mode so that no single channel
could carry more than 108µA in such event. See Figure 13.
Note that it is not necessary for the RISHARE to be scaled to trip
at the same level as the 108µA OCP comparator if the
application allows. T ypically the ISHARE pin average current
protection level should be higher than the phase current
protection level. For instance, when Channel 1 operates
independently , the OC trip set by 1.2V comparator can be lower
than 108µA trip point as shown in Equation 6.
where N is the number of phases; NCNTL is the number of
the ISL8120 controllers in parallel or multiphase operations;
FIGURE 16. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION
ISHARE
ISET
SHARE BUS
RISET1
RISHARE1
ISL81201
VSEN1/2- COM1/2
ISHARE
ISET
RISET3
RISHARE3
ISL81203
VSEN1/2- COM1/2
ISHARE
ISET
RISET2
RISHARE2
ISL81202
VSEN2- COM1/2
VCC
VSEN1+
VSEN1-
RISHARE_ = RISET_
RISEN1
IOC
N
----------VOUT
L
----------------1D–
2FSW
---------------- tMIN_OFF
–
⎝⎠
⎛⎞
•+
⎝⎠
⎜⎟
⎛⎞
DCR•
ITRIP
----------------------------------------------------------------------------------------------------------------------
=
RISHARE 1.2V
ITRIP
---------------
=RISET RISHARE NCNTL
⋅=
(EQ. 6)
ISL8120
30 March 20, 2009
FN6641.0
ITRIP = 108µA; IOC is the load overcurrent trip point;
tMIN_OFF is the minimum Ugate turn off time that is 350ns;
RISHARE in Equation 6 represents the total equivalent
resistance in ISHARE pin bus of all ICs in multiphase or
module parallel operation.
For the RISEN chosen for OCP setting, the final value is
usually higher than the number calculated from Equation 6.
The reason of which is practical especially for low DCR
applications since the PCB and inductor pad soldering
resistance would have large effects in total impedance,
affecting the DCR voltage to be sensed.
When OCP is triggered, the controller pulls EN/FF low
immediately to turn off UGATE and LGATE.
For overload and hard short condition, the overcurrent
protection reduces the regulator RMS output current much
less than full load by putting the controller into hiccup mode.
A delay time, equal to 3 soft-start intervals, is inserted to
allow the disturbance to be cleared out. After the delay time,
the controller then initiates a soft-start interval. If the output
voltage comes up and returns to the regulation, PGOOD
transitions high. If the OC trip is exceeded during the
soft-st art interval, the controller pulls EN/VFF low again. The
PGOOD signal will remain low and th e soft-start interval will
be allowed to expire. Another soft-start interval will be
initiated after the delay interval. If an overcurrent trip occurs
again, this same cycle repeats until the fault is removed.
Internal Seri es Lin e ar and Power Dissipation
The VIN pin is connected to PVCC with an internal series
linear regulator. The PVC C and VIN pins should have the
recommended bypass ceramic capacitors (10µF) connected
to GND for proper operation. The internal linear regulator’s
input (VIN) can range between 3V to 22V. PVCC pin is the
output of the internal linear regulator and it provides power
for both the internal MOSFET drivers through the PVCC pin.
VCC pin is the bias input for the IC small signal analog
circuitry. By connecting PVCC to VCC pin, the internal linear
regulator supplies bias power to VCC. The VCC pin should
be connected to the PVCC pin with an RC filter to prevent
high frequency driver switching noise from the analog
circuitry. When VIN drops below 5.0V, the pass element will
saturate; PVCC will track VIN with a dropout of the linear
regulator. When used with an external 5V supply , the VIN pin
is recommended to be tied directly to PVCC.
The LDO is capable of supplying 250mA with regulated 5.4V
output. In 3.3V input applications, when the VIN pin voltage
is 3V, the LDO can still supply 150mA while maintaining LDO
output voltage higher than VCC falling threshold to keep IC
operating. Figure 18 shows the LDO voltage drop under
different load current. However, its thermal capability should
not be exceeded. The power dissipation inside the IC could
be estimated with Equation 7.
FIGURE 17. INTERNAL REGULATOR IMPLEMENTATION
5V
Z1
3V TO 26.4V
2.65V TO 5.6V
PVCC VINVCC
Z2
2Ω
1µF
10µF
PIC VIN PVCC–()IVIN
⋅PDR
+= (EQ. 7)
IVIN QG1 NQ1
•
VGS1
------------------------------QG2 NQ2
•
VGS2
------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PVCC F•SW IQ_VIN
+•=
FIGURE 18. PVCC vs VIN VOLTAGE
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VIN PIN VOLTAGE (V)
PVCC (V)
Iq IS AROUND 15mA
PVCC @ 250mA + Iq PVCC @ 100mA + Iq
PVCC @ 140mA + Iq
ISL8120
31 March 20, 2009
FN6641.0
where the gate charge (QG1 and QG2) is defined at a
particular gate to source voltage (VGS1and VGS2) in the
corresponding MOSFET datasheet; IQ_VIN is the driver’s
total quiescent current with no load at drive outputs; NQ1 and
NQ2 are number of upper and lower MOSFETs, respectively.
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offs e t of 1. 0V.
Each channel’s peak-to-peak of the ramp amplitude is set
proportional the voltage applied to its corresponding EN/FF
pin. See “Voltage Feed-forward” on page 23.
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronize d frequency operation. By tying a
resistor (RFSYNC) to GND from the FSYNC pin, the switching
frequency can be set a t any frequen cy between 150kHz and
1.5MHz. The frequency setting curve shown in Figure 21 is
provided to assist in selecting the correct value for RFSYNC.
By connecting the FSYNC pin to an external square pulse
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120), the ISL 8120 will synchronize
its switching frequency to the fundamental frequency of the
input waveform. The maximum voltage to the FSYNC pin is
VCC + 0.3V. The Frequency Synchronization feature will
synchronize the leading edge of CLKOU T sign al with the
falling edge of Channel 1’s PWM clock signal. The CLKOUT
is not available until the PLL locks.
The locking time is typically 130µs for FSW = 500kH z.
EN/VFF1 is released for a soft-start cycle until the FSYNC
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns locking, at
which point a soft-start cycle is initiated and normal
operation resumes. Holding FSYNC low will disable the IC.
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
PDR PDR_UP PDR_LOW
+= (EQ. 8)
PDR_UP RHI1
RHI1 REXT1
+
-------------------------------------- RLO1
RLO1 REXT1
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q1
2
---------------------
•=
PDR_LOW RHI2
RHI2 REXT2
+
-------------------------------------- RLO2
RLO2 REXT2
+
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
PQg_Q2
2
---------------------
•=
REXT2 RG1 RGI1
NQ1
-------------
+= REXT2 RG2 RGI2
NQ2
-------------
+=
PQg_Q1 QG1 PVCC2
•
VGS1
---------------------------------------FSW
•NQ1
•=
PQg_Q2 QG2 PVCC2
•
VGS2
---------------------------------------FSW
•NQ2
•=
Q1
D
S
G
RGI1RG1
BOOT
RHI1 CDS
CGS
CGD
RLO1
PHASE
PVCC
UGATE
PVCC
Q2
D
S
G
RGI2
RG2
RHI2 CDS
CGS
CGD
RLO2
GND
LGATE
FIGURE 21. RFS vs SWITCHING FREQUENCY
0
200
400
600
800
1,000
1,200
1,400
1,600
20 40 60 80 100 120 140 160 180 200 220 240 260
R_FS (kΩ)
SWITCHING FREQUENCY (kHz)
ISL8120
32 March 20, 2009
FN6641.0
Differential Amplifier for Remote Sense
The differential remote sense buffer has a precision unity
gain resistor matching network, which has a ultra low offset
of 1mV. This true remote sensing scheme helps compensate
the droop due to load on the positive and negative rails and
maintain the high system accuracy of ±0.6%.
The output of the remote sense buffer is connected directly
to the internal OV/UV comparator. As a result, a resistor
divider should be placed on the input of the buffer for proper
regulation, as shown in Figure 24. The VMON pin should be
connected to the FB pin by a standard feedback network.
Since the input impedance of VSEN+ pin in respect to
VSEN- pin is about 500kΩ, it is highly recommended to
include this impedance into calculation and use 100Ω or less
for the lower leg (ROS) of the feedback resistor divider to
optimize system accuracy. Note that any RC filter at the
inputs of the differential amplifier will contribute as a pole to
the overall loop compensation.
As some applications will not need the differential remote
sense, the output of the remote sense buffer can be disabled
and be placed in high impedance by pulling VSEN- within
700mV of VCC. In such an event, the VMON pin can be
used as an additional monitor of the output voltage with a
resistor divider to protect the system against single point of
failure, which occurs in the system using the same resistor
divider for the UV/OV comparator and the output regulation.
The resistor divider ratio should be the same as the one for
the output regulation so that the correct voltage information
is provided to the OV/UV comparator. Figure 23 shows the
differential sense amplifier can be directly used as a monitor
without pulling VSEN- high.
DDR and Dual Mode Operation
If the CLKOUT/REFIN is less than 800mV, an external
soft-st art ramp (0.6V) can be in parallel with the Channel 2’s
internal soft-start ramp for DDR/tracking applications (DDR
Mode).
The output voltage (typical VTT output) of Channel 2 tra cks
with the input voltage (typical VDDQ*(1+k) from Channel 1)
at the CLKOUT/REFIN pin. As for the external input signal
and internal reference signal (ramp and 0.6V), the one with
the lowest voltage will be the one to be used as the
reference comparing with FB signal. So in DDR
configuration, VTT channel should start-up later after its
internal soft-start ramp in which way the VTT will track the
voltage on REFIN pin derived from VDDQ. This can be
achieved by adding more filtering at EN//FF1 compared with
EN/FF2.
FIGURE 22. EQUIVALENT DIFFERENTIAL AMPLIFER
20k
20k
20k
20k
RDIF = 500k
VSEN-
VSEN+
GND
VSEN+ VSEN- FB
VMON
RFB
ROS
OV/UV ERROR AMP
COMP
700mV
VCC
FIGURE 23. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION
VREF
VOUT
GAIN=1
PGOOD
PGOOD
ZCOMP
ROS
COMP
RFB
ISL8120
33 March 20, 2009
FN6641.0
Since the UV/OV comparator uses the same internal reference
0.6V, to guarantee UV/OV and Pre-charged start-up functions
of Channel 2, the target voltage derived from Channel 1
(VDDQ) should be scaled close to 0.6V, and it is suggested to
be slightly above (+2%) 0.6V with an external resistor divider ,
which will have Channel 2 use the internal 0.6V reference after
soft-st art. Any capacitive load at REFIN pin should not slow
down the ramping of this input 150mV lower than the Channel
2’ internal ramp. Otherwise, the UV protection could be fault
triggered prior to the end of the soft-start. The start-up of
Channel 2 can be delayed to avoid such situation happening, if
high capacitive load presents at REFIN pin for noise
decoupling. During shutdown, Channel 2 will follow Channel 1
until both channels drops below 87%, at which point both
channels enter UV protection zone. Depending on the loading,
Channel 1 might drop faster than Channel 2. To solve this race
condition, Channel 2 can either power up from Channel 1 or
bridge the Channel 1 with a high current Schottky diode. If the
system requires to shutdown both channels when either has a
fault, tying EN/FF1 and EN/FF2 will do the job. In DDR mode,
Channel 1 delays 60° over Channel 2.
In Dual mode, depending up on the resistor divider level of
REFIN from VCC, the ISL8120 operates as a dual-PWM
controller for two independent regulators with a phase shift,
as shown in Table 2. The phase shift is latched as VCC
raises above POR and cannot be changed on the fly.
Internal Reference and System Accuracy
The internal reference is set to 0.6V. Including bandgap
variation and offset of differential and error amplifiers, it has
an accuracy of ±0.6% over commercial temperature range,
and 0.9% over industrial temperature range. Wh ile the
remote sense is not used, its offset (VOS_DA) should be
included in the tolerance calculation. Equations 9 and 10
show the worst case of system accuracy calculation.
VOS_DA should set to zero when the differential amplifier is
in the loop, the differential amplifier’s input impedance
(RDIF) is typically 500kΩ with a tolerance of 20% (RDIF%)
and can be neglected when ROS is less than 100Ω. To set a
precision setpoint, ROS can be scaled by two paralleled
resistors.
Figure 26 shows the tolerance of various output voltage
regulation for 1%, 0.5%, and 0.1% feedback resistor
VSEN- VSEN+ COMP
FB
VMON
RFB
ROS
ZFB ZCOMP
OV/UV ERROR AMP
COMP
CSEN
700mV
VCC
FIGURE 24. SIMPLIFIED REMOTE SENSING IMPLEMENTATION
VREF
10Ω
10Ω
VOUT (LOCAL)
GND (LOCAL)
VSENSE+ (REMOTE)
GAIN=1
VSENSE- (REMOTE)
PGOOD
PGOOD
TABLE 2.
MODE DECODING
REFIN RANGE PHASE for CHANNEL
2 WRT CHANNEL 1 REQUIRED
REFIN
DDR <29% of VCC -60° 0.6V
Dual 29% to 45% of VCC 0° 37% VCC
Dual 45% to 62% of VCC 90° 53% VCC
Dual 62% to VCC 180° VCC
700mV
FIGURE 25. SIMPLIFIED DDR IMPLEMENTAION
PHASE-SHIFTED
CLOCK
VCC
CLKOUT/REFIN
VSEN2-
VDDQ
R
kVTT
0.6V
------------ 1–=
k*R
Internal SS
ISL8120
STATE
MACHINE
E/A2
0.6V
FB2
ISL8120
34
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April 7, 2009
dividers. Note that the farther the output voltage setpoint
away from the internal reference voltage, the larger the
tolerance; the lower the resisto r tolerance (R%), the tighter
the regulation.
%min Vref 1 Ref%–()⋅VOS_DA
–()1RFB 1R%–()⋅
ROSMAX
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=
(EQ. 9)
ROSMAX 1
1
ROS 1R%+()⋅
----------------------------------------- 1
RDIF 1R
DIF%+()⋅
----------------------------------------------------
+
-----------------------------------------------------------------------------------------------------
=
%max Vref 1 Ref%–()⋅VOS_DA
–()1RFB 1R%–()⋅
ROSMIN
----------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=
(EQ. 10)
ROSMIN 1
1
ROS 1R–%()⋅
---------------------------------------1
RDIF 1R
DIF
–%()⋅
-------------------------------------------------
+
-----------------------------------------------------------------------------------------------
=FIGURE 26. OUTPUT REGULA TION WITH DIFFERENT
RESISTOR TOLERANCE FOR Ref% = ±0.6%
OUTPUT REGULATION (%)
OUTPUT VOLTAGE (V)
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
1%
0.5%
0.5%
0.1%
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
R% = 1%
0.1%
ISL8120
35 March 20, 2009
FN6641.0
ISL8120
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
located within the zone indicated . Th e pin #1 identifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
BOTTOM VIEW
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
5.00 A
5.00
B
INDEX AREA
PIN 1
6
(4X) 0.15
32X 0.40 ± 0.10 4
A
32X 0.23
M0.10 C B
16 9
4X
0.50
28X
3.5
6
PIN #1 INDEX AREA
3 .30 ± 0 . 15
0 . 90 ± 0.1
BASE PLANE
SEE DETAIL "X"
SEATING PLANE
0.10 C
C
0.08 C
0 . 2 REF
C
0 . 05 MAX.
0 . 00 MIN.
5
( 3. 30 )
( 4. 80 TYP ) ( 28X 0 . 5 )
(32X 0 . 23 )
( 32X 0 . 60)
+ 0.07
- 0.05
17
25
24
8
1
32
