LTC1863L/LTC1867L
1
1863l7lfc
BLOCK DIAGRAM
DESCRIPTION
FEATURES
APPLICATIONS
n Industrial Process Control
n High Speed Data Acquisition
n Battery Operated Systems
n Multiplexed Data Acquisition Systems
n Imaging Systems
n Sample Rate: 175ksps
n 16-Bit No Missing Codes and ±3LSB Max INL
n 8-Channel Multiplexer with:
Single Ended or Differential Inputs and
Unipolar or Bipolar Conversion Modes
n SPI™/MICROWIRE™ Serial I/O
n 2.7V Guaranteed Supply Voltage
n Pin Compatible with LTC1863/LTC1867
n True Differential Inputs
n On-Chip or External Reference
n Low Power: 750μA at 175ksps, 300μA at 50ksps
n Sleep Mode
n Automatic Nap Mode Between Conversions
n 16-Pin Narrow SSOP Package
The LTC
®
1863L/LTC1867L are pin compatible, 8-channel
12-/16-bit A/D converters with serial I/O and an internal
reference.
The 8-channel input multiplexer can be confi gured for
either single-ended or differential inputs and unipolar or
bipolar conversions (or combinations thereof). The ADCs
convert 0V to 2.5V unipolar inputs or ±1.25V bipolar
inputs. The ADCs typically draw only 750μA from a single
2.7V supply. The automatic nap and sleep modes benefi t
power sensitive applications.
The LTC1867L’s DC performance is outstanding with a
±3LSB INL specifi cation and 16-bit no missing codes
over temperature.
Housed in a compact, narrow 16-pin SSOP package, the
LTC1863L/LTC1867L can be used in space-sensitive as
well as low power applications.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
1863L7L BD
SERIAL
PORT
ANALOG
INPUT
MUX
REFCOMP
9
INTERNAL
1.25V REF
LTC1863L/LTC1867L
12-/16-BIT
175ksps
ADC
+
–
Integral Nonlinearity vs Output Code
(LTC1867L)
OUTPUT CODE
0
INL (LSB)
0
0.5
1.0
65536
1863L7L G01
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
Micropower, 3V,
12-/16-Bit, 8-Channel
175ksps ADCs
LTC1863L/LTC1867L
2
1863l7lfc
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1863LCGN#PBF LTC1863LCGN#TRPBF 1863L 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1863LIGN#PBF LTC1863LIGN#TRPBF 1863L 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867LCGN#PBF LTC1867LCGN#TRPBF 1867L 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867LIGN#PBF LTC1867LIGN#TRPBF 1867L 16-Lead Narrow Plastic SSOP –40°C to 85°C
LTC1867LACGN#PBF LTC1867LACGN#TRPBF 1867L 16-Lead Narrow Plastic SSOP 0°C to 70°C
LTC1867LAIGN#PBF LTC1867LAIGN#TRPBF 1867L 16-Lead Narrow Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Supply Voltage (VDD) ................................... –0.3V to 6V
Analog Input Voltage
CH0-CH7/COM (Note 3) ...........–0.3V to (VDD + 0.3V)
V
REF, REFCOMP (Note 4) ......... –0.3V to (VDD + 0.3V)
Digital Input Voltage (SDI, SCK, CS/CONV)
(Note 4) ................................................. –0.3V to 10V
Digital Output Voltage (SDO) ....... –0.3V to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1863LC/LTC1867LC/LTC1867LAC ..... 0°C to 70°C
LTC1863LI/LTC1867LI/LTC1867LAI .....–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
(Notes 1, 2)
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
REFCOMP
TJMAX = 110°C, θJA = 95°C/W
Consult LTC Marketing for parts specifi ed with wider operating temperature
ranges.
PARAMETER CONDITIONS
LTC1863L LTC1867L LTC1867LA
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Resolution l12 16 16 Bits
No Missing Codes l12 15 16 Bits
Integral Linearity Error Unipolar (Note 7)
Bipolar
l
l
±1
±1
±4
±4
±3
±3
LSB
LSB
Differential Linearity Error l±1 –2 –1 LSB
Transition Noise 0.1 1.6 1.6 LSBRMS
Offset Error Unipolar (Note 8)
Bipolar
l
l
±3
±4
±32
±64
±32
±64
LSB
LSB
Offset Error Match Unipolar
Bipolar
±1
±1
±4
±4
±3
±3
LSB
LSB
Offset Error Drift ±0.5 ±0.5 ±0.5 ppm/°C
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6)
LTC1863L/LTC1867L
3
1863l7lfc
CONVERTER CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VDD = 2.7V, external VREF = 1.25V (Notes 5, 6)
PARAMETER CONDITIONS
LTC1863L LTC1867L LTC1867LA
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Gain Error Unipolar
Bipolar
±6
±6
±96
±96
±64
±64
LSB
LSB
Gain Error Match Unipolar
Bipolar
±1
±1
±4
±4
±3
±3
LSB
LSB
Gain Error Tempco Internal Reference
External Reference
±20
±3
±20
±3
±20
±3
ppm/°C
ppm/°C
Power Supply Sensitivity VDD = 2.7V – 3.6V ±1 ±3 ±3 LSB
DYNAMIC ACCURACY
VDD = 3V, external VREF = 1.25V (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863L LTC1867L/LTC1867LA
UNITSMIN TYP MAX MIN TYP MAX
SNR Signal-to-Noise Ratio 1kHz Input Signal 73.1 83.7 dB
S/(N+D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal 73 83.1 dB
THD Total Harmonic Distortion 1kHz Input Signal, Up to 5th Harmonic –91.8 – 92.3 dB
Peak Harmonic or Spurious Noise 1kHz Input Signal –94.8 –95.1 dB
Channel-to-Channel Isolation 100kHz Input Signal –100 –112 dB
Full Power Bandwidth –3dB Point 1.25 1.25 MHz
ANALOG INPUT
SYMBOL PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
Analog Input Range Unipolar Mode (Note 9)
Bipolar Mode
●
●
0 to 2.5
±1.25
V
V
CIN Analog Input Capacitance for CH0 to
CH7/COM
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
32
4
pF
pF
tACQ Sample-and-Hold Acquisition Time ●2.01 1.68 μs
Input Leakage Current On Channels, CHX = 0V or VDD ●±1 μA
The ● denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 5)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
VIH High Level Input Voltage VDD = 3.6V ●1.9 V
VIL Low Level Input Voltage VDD = 2.7V ●0.45 V
The ● denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
VREF Output Voltage IOUT = 0 1.235 1.25 1.265 V
VREF Output Tempco IOUT = 0 ±20 ppm/°C
VREF Line Regulation 2.7V ≤ VDD ≤ 3.6V 0.3 mV/V
VREF Output Resistance ⏐IOUT ⏐ ≤0.1mA 3 kΩ
REFCOMP Output Voltage IOUT = 0 2.5 V
(Note 5)
LTC1863L/LTC1867L
4
1863l7lfc
DIGITAL INPUTS AND DIGITAL OUTPUTS
The ● denotes the specifi cations which apply over the
full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
IIN Digital Input Current VIN = 0V to VDD ●±10 μA
CIN Digital Input Capacitance 2pF
VOH High Level Output Voltage (SDO) VDD = 2.7V, IO = –10μA
VDD = 2.7V, IO = –200μA ●23
2.68
2.65
V
V
VOL Low Level Output Voltage (SDO) VDD = 2.7V, IO = 160μA
VDD = 2.7V, IO = 1.6μA ●
0.05
0.15 0.4
V
V
ISOURCE Output Source Current SDO = 0V –9.7 mA
ISINK Output Sink Current SDO = VDD 6mA
Hi-Z Output Leakage
Hi-Z Output Capacitance
CS/CONV = High, SDO = 0V or VDD
CS/CONV = High (Note 10)
●
●
±10
15
μA
pF
Data Format Unipolar
Bipolar
Straight Binary
Two’s Complement
POWER REQUIREMENTS
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
VDD Supply Voltage (Note 9) 2.7 3.6 V
IDD Supply Current fSAMPLE = 175ksps, Internal REF
NAP Mode
SLEEP Mode
●
●
0.75
170
0.2
1
3
mA
μA
μA
PDISS Power Dissipation fSAMPLE = 175ksps ●22.7mW
TIMING CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS
LTC1863L/LTC1867L/LTC1867LA
UNITSMIN TYP MAX
fSAMPLE Maximum Sampling Frequency ●175 kHz
tCONV Conversion Time ●3.2 3.7 μs
tACQ Acquisition Time ●2.01 1.68 μs
fSCK SCK Frequency 20 MHz
t1CS/CONV High Time Short CS/CONV Pulse Mode ●40 100 ns
t2SDO Valid After SCK↓CL = 25pF (Note 11) ●22 47 ns
t3SDO Valid Hold Time After SCK↓CL = 25pF ●517 ns
t4SDO Valid After CS/CONV↓CL = 25pF ●20 40 ns
t5SDI Setup Time Before SCK↑●15 –6 ns
t6SDI Hold Time After SCK↑●15 6 ns
t7SLEEP Mode Wake-Up Time CREFCOMP = 10μF, CVREF = 2.2μF 80 ms
t8Bus Relinquish Time After CS/CONV↑CL = 25pF ●30 50 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
LTC1863L/LTC1867L
5
1863l7lfc
TYPICAL PERFORMANCE CHARACTERISTICS
TIMING CHARACTERISTICS
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 5)
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
clamped to VDD.
Note 5: VDD = 2.7V, fSAMPLE = 175ksps and fSCK = 20MHz at 25°C,
tr = tf = 5ns and VIN– = 1.25V for bipolar mode unless otherwise specifi ed.
Note 6: Linearity, offset and gain error specifi cations apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code fl ickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000
and 0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage
measured from –1/2LSB when output code fl ickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863L.
Note 9: Recommended operating conditions. The input range of ±1.25V
for bipolar mode is measured with respect to VIN– = 1.25V. For unipolar
mode, common mode input range is 0V to VDD for the positive input and
0V to 1.5V for the negative input. For bipolar mode, common mode input
range is 0V to VDD for both positive and negative inputs.
Note 10: Guaranteed by design, not subject to test.
Note 11: t2 of 47ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 3ns
setup time for the receiving logic).
(LTC1867L)
OUTPUT CODE
0
INL (LSB)
0
0.5
1.0
65536
1863L7L G01
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
OUTPUT CODE
0
DNL (LSB)
0
0.5
1.0
65536
1863L7L G02
–0.5
–1.0
–2.0 16384 32768 49152
–1.5
2.0
1.5
V
DD
= 2.7V
f
SAMPLE
= 175ksps
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G03
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
4096 Points FFT Plot
(VDD = 2.7V, Internal REF)
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G04
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 84.7dB
SINAD = 83.5dB
THD = 90dB
ACTIVE CHANNEL INPUT FREQUENCY (kHz)
–120
RESULTING AMPLITUDE ON
SELECTED CHANNEL (dB)
–100
–90
–70
–60
0.1 10 100 1000
1863L7L G05
–140
1
–80
–110
–130
V
DD
= 3V
f
SAMPLE
= 175ksps
ADJACENT PAIR
NONADJACENT
PAIR
INPUT FREQUENCY (kHz)
1
20
AMPLITUDE (dB)
40
60
100
10 100
1863L7L G06
80
30
50
90
70
V
DD
= 3V
INTERNAL REF
f
SAMPLE
= 175ksps
SNR
SINAD
4096 Points FFT Plot
(VDD = 3V, REFCOMP = Ext 3V) Crosstalk vs Input Frequency
Signal-to-(Noise + Distortion)
Ratio vs Input Frequency
LTC1863L/LTC1867L
6
1863l7lfc
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1867L)
(LTC1863L/ LTC1867L)
INPUT FREQUENCY (kHz)
1
–20
AMPLITUDE (dB)
–40
–60
–100
10 100
1863L7L G07
–80
–30
–50
–90
–70
V
DD
= 3V
INTERNAL REF
f
SAMPLE
= 175ksps
THD
SFDR
Power Supply Feedthrough
vs Ripple Frequency
Supply Current vs fSAMPLE
(LTC1863L/LTC1867L)
Total Harmonic Distortion
vs Input Frequency
Supply Current vs Supply Voltage Supply Current vs Temperature
Histogram for 4096 Conversions
(LTC1867L)
SUPPLY VOLTAGE (V)
2.7
600
SUPPLY CURRENT (μA)
700
800
900
1000
1200
3 3.3
1963L7L G10
3.6
1100
f
SAMPLE
= 175ksps
TEMPERATURE (°C)
–50
500
SUPPLY CURRENT (μA)
750
1000
1250
1500
–25 0 25 50
1863L7L G11
75 100
3.6V
DD
3.3V
DD
2.7V
DD
3V
DD
f
SAMPLE
= 175ksps
INTERNAL REF
CODE
20
7
0
COUNTS
200
400
600
800
1200
22 24 26 28
1863L7L G12
3021 23 25 27 29 31
1000
58
465
1044
895
830
261
23 91
170
333
VDD = 2.7V
INTERNAL REF
LOAD CURRENT (mA)
0
2.495
2.500
2.510
1.5
1863L7L G13
2.490
2.485
0.5 1 2
2.480
2.475
2.505
REFCOMP (V)
V
DD
= 2.7V
TEMPERATURE (°C)
–50
–10
UNIPOLAR OFFSET (LSB)
–5
0
5
10
–25 0 25 50
1863L7L G14
75 100
BIPOLAR
MODE
UNIPOLAR
MODE
V
DD
= 2.7V
f
SAMPLE
= 175ksps
EXT V
REF
= 1.25V
TEMPERATURE (°C)
–50
–15
UNIPOLAR OFFSET (LSB)
–10
–5
0
5
15
–25 02550
1863L7L G15
75 100
10
V
DD
= 2.7V
f
SAMPLE
= 175ksps
EXT V
REF
= 1.25V
UNIPOLAR/BIPOLAR
REFCOMP vs Load Current
Offset Drift (LTC1867L)
vs Temperature
Gain Error Drift (LTC1867L)
vs Temperature
LTC1863L/LTC1867L
7
1863l7lfc
PIN FUNCTIONS
TYPICAL PERFORMANCE CHARACTERISTICS
(LTC1863L/ LTC1867L)
CODE
0
INL (LSB)
0
0.50
4096
1863L7L G16
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
CODE
0
DNL (LSB)
0
0.50
4096
1863L7L G17
–0.50
–1.00 1024 2048 3072
512 1536 2560 3584
1.00
–0.25
0.25
–0.75
0.75
Differential Nonlinearity
vs Output Code (LTC1863L)
Integral Nonlinearity
vs Output Code (LTC1863L)
CHO-CH7/COM (Pins 1-8): Analog Input Pins. Analog
i n p u t s m u s t b e f r e e o f n o i s e w i t h r e s p e c t t o G N D. C H 7/ C O M
can be either a separate channel or the common minus
input for the other channels. Unused channels should be
tied to ground.
REFCOMP (Pin 9): Reference Buffer Output Pin. Bypass
to GND with 10μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor (2.5V Nominal). To overdrive REFCOMP,
tie VREF to GND.
VREF (Pin 10): 1.25V Reference Output. This pin can also
be used as an external reference buffer input for improved
accuracy and drift. Bypass to GND with 2.2μF tantalum
capacitor in parallel with 0.1μF ceramic capacitor.
CS/CONV (Pin 11): This input provides the dual function
of initiating conversions on the ADC and also frames the
serial data transfer.
SCK (Pin 12): Shift Clock. This clock synchronizes the
serial data transfer.
SDO (Pin 13): Digital Data Output. The A/D conversion
result is shifted out of this output. Straight binary format
for unipolar mode and two’s complement format for
bipolar mode.
SDI (Pin 14): Digital Data Input Pin. The A/D confi guration
word is shifted into this input.
GND (Pin 15): Analog and Digital GND.
VDD (Pin 16): Analog and Digital Power Supply. Bypass to
GND with 10μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor.
LTC1863L/LTC1867L
8
1863l7lfc
TEST CIRCUITS
TIMING DIAGRAMS
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
VDD
GND
SDI
SDO
SCK
CS/CONV
VREF
REFCOMP
LTC1863L/
LTC1867L
–
+
+
DIGITAL
I/O
2.7V TO 3.6V
10μF
2.5V
10μF
2.2μF
1.25V
±1.25V
DIFFERENTIAL
INPUTS
2.5V
SINGLE-ENDED
INPUT
1863L7L TCD
TYPICAL CONNECTION DIAGRAM
Load Circuits for Access Timing Load Circuits for Output Float Delay
3k
(A) Hi-Z TO VOH AND VOL TO VOH
CL
3k
2.7V
SDOSDO
(B) Hi-Z TO VOL AND VOH TO VOL
CL
1863L7L TC01
3k
(A) VOH TO Hi-Z
CL
3k
2.7V
SDOSDO
(B) VOL TO Hi-Z
CL
1863L7L TC02
t1 (For Short Pulse Mode)
t2 (SDO Valid After SCK↓)
t3 (SDO Valid Hold Time After SCK↓)
t4 (SDO Valid After CS/CONV↓)
t5 (SDI Setup Time Before SCK↑)
t6 (SDI Hold Time After SCK↑)
t7 (SLEEP Mode Wake-Up Time) t8 (BUS Relinquish Time)
1863L7L TD01a
t1
CS/CONV 50%
50%
t3
0.45V
1.9V
0.45V
SDO
1863L7L TD01b
t2
SCK
t4
CS/CONV
SDO 1.9V
0.45V
0.45V
1863L7L TD01c
Hi-Z
t6
1.9V
0.45V
t5
SCK
SDI 1.9V
1.9V
0.45V
1863L7L TD01d
50%
50%
t7
SCK
CS/CONV
1863L7L TD01e
SLEEP BIT (SLP = 0)
READ-IN
t8
CS/CONV
SDO
1.9V
1863L7L TD01f
10%
90% Hi-Z
LTC1863L/LTC1867L
9
1863l7lfc
APPLICATIONS INFORMATION
Overview
The LTC1863L/LTC1867L are complete, low power, multi-
plexed ADCs. They consist of a 12-/16-bit, 175ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a confi gurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 2.01μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signifi cant bit (MSB) to the least signifi cant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low power, differential
comparator that rejects common mode noise. At the end
of a conversion, the DAC output balances the analog input.
The SAR content (a 12-/16-bit data word) that represents
the analog input is loaded into the 12-/16-bit output latches.
Analog Input Multiplexer
The analog input multiplexer is controlled by a 7-bit input
data word. The input data word is defi ned as follows:
SD OS S1 S0 COM UNI SLP
SD = SINGLE/DIFFERENTIAL BIT
OS = ODD/SIGN BIT
S1 = ADDRESS SELECT BIT 1
S0 = ADDRESS SELECT BIT 0
COM = CH7/COM CONFIGURATION BIT
UNI = UNIPOLAR/BIPOLAR BIT
SLP = SLEEP MODE BIT
Examples of Multiplexer Options
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
GND (
–
)
8 Single-Ended
+
+
+
+
+
+
+
4 Differential
+
(
–
)
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM (
–
)
7 Single-Ended
to CH7/COM
+
+
+
+
+
+
+
+
(
–
)
+
(
–
)
+
(
–
)
–
(
+
)
–
(
+
)
–
(
+
)
–
(
+
)
GND (
–
)
Combinations of Differential
and Single-Ended
+
+
+
+
+
+
–
–
{
{
{
{
{
{
1863L7L
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7/COM
Tables 1 and 2 show the confi gurations when COM = 0,
and COM = 1.
Table 1. Channel Confi guration (When COM = 0, CH7/COM Pin
Is Used as CH7)
SD OS S1 S0 COM
Channel Confi guration
“+” “–”
000 0 0 CH0 CH1
000 1 0 CH2 CH3
001 0 0 CH4 CH5
001 1 0 CH6 CH7
010 0 0 CH1 CH0
010 1 0 CH3 CH2
011 0 0 CH5 CH4
011 1 0 CH7 CH6
100 0 0 CH0 GND
100 1 0 CH2 GND
101 0 0 CH4 GND
101 1 0 CH6 GND
110 0 0 CH1 GND
110 1 0 CH3 GND
111 0 0 CH5 GND
111 1 0 CH7 GND
CH7/COM
(UNUSED) CH7/COM (
–
)
1st Conversion 2nd Conversion
+
–
+
–
+
–
+
+
{
{
{
{
CH2
CH3
CH4
CH5
CH2
CH3
CH4
CH5
1863L7L AI02
Changing the MUX Assignment “On the Fly”
LTC1863L/LTC1867L
10
1863l7lfc
Table 2. Channel Confi guration (When COM = 1, CH7/COM Pin
Is Used as COMMON)
SD OS S1 S0 COM
CHANNEL CONFIGURATION
“+” “–”
100 0 1 CH0 CH7/COM
100 1 1 CH2 CH7/COM
101 0 1 CH4 CH7/COM
101 1 1 CH6 CH7/COM
110 0 1 CH1 CH7/COM
110 1 1 CH3 CH7/COM
111 0 1 CH5 CH7/COM
Driving the Analog Inputs
The analog inputs of the LTC1863L/LTC1867L are easy to
drive. Each of the analog inputs can be used as a single-
ended input relative to the GND pin (CH0-GND, CH1-GND,
etc) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5,
CH6 and CH7) for differential inputs. In addition, CH7 can
act as a COM pin for both single-ended and differential
modes if the COM bit in the input word is high. Regard-
less of the MUX confi guration, the “+” and “–” inputs are
sampled at the same instant. Any unwanted signal that is
common mode to both inputs will be reduced by the com-
mon mode rejection of the sample-and-hold circuit. The
inputs draw only one small current spike while charging
the sample-and-hold capacitors during the acquire mode.
In conversion mode, the analog inputs draw only a small
leakage current. If the source impedance of the driving
circuit is low then the LTC1863L/LTC1867L inputs can be
driven directly. More acquisition time should be allowed
for a higher impedance source.
The following list is a summary of the op amps that are
suitable for driving the LTC1863L/LTC1867L. More detailed
information is available in the Linear Technology data
books or Linear Technology website.
1863L7L F01a
CH0
GND
LTC1863L/
LTC1867L
REFCOMP
2000pF
10μF
50Ω
ANALOG
INPUT
1000pF
1863L7L F01b
CH0
CH1
LTC1863L/
LTC1867L
REFCOMP
1000pF
1000pF
10μF
50Ω
50Ω
DIFFERENTIAL
ANALOG
INPUTS
Figure 1a. Optional RC Input Filtering for Single-Ended Input Figure 1b. Optional RC Input Filtering for Differential Inputs
LT
®
1468: 90MHz, 22V/μs 16-bit accurate amplifi er
LT1469: Dual LT1468
LT1490A/LT1491A: Dual/quad micropower amplifi ers,
50μA/amplifi er max, 500μV offset, common mode range
extends 44V above V– independent of V+, 3V, 5V and ±15V
supplies.
LT1568: Very low noise, active RC fi lter building block,
cutoff frequency up to 10MHz, 2.7V to ±5V supplies.
LT1638/LT1639: Dual/quad 1.2MHz, 0.4V/μs amplifi ers,
230μA per amplifi er, 3V, 5V and ±15V supplies.
LT1881/LT1882: Dual and quad, 200pA bias current, rail-
to-rail output op amps, up to ±15V supplies.
LTC1992-2: Gain of 2 fully differential input/output am-
plifi er/driver, 2.5mV offset, CLOAD stable, 2.7V to ±5V
supplies.
LT1995: 30MHz, 1000V/μs gain selectable amplifi er, pin
confi gurable as a difference amplifi er, inverting and non-
inverting amplifi er, ±2.5V to ±15V supplies.
LTC6912: Dual programmable gain amplifi ers with SPI
serial interface, 2mV offset, 2.7V to ±5V supplies.
LTC6915: Zero drift, instrumentation amplifi er with SPI
programmable gain, 125dB CMRR, 0.1% gain accuracy,
10μV offset.
Input Filtering
The noise and the distortion of the input amplifi er and
other circuitry must be considered since they will add to
the LTC1863L/LTC1867L noise and distortion. Noisy input
circuitry should be fi ltered prior to the analog inputs to
minimize noise. A simple 1-pole RC fi lter is suffi cient for
APPLICATIONS INFORMATION
LTC1863L/LTC1867L
11
1863l7lfc
many applications. For instance, Figure 1 shows a 50Ω
source resistor and a 2000pF capacitor to ground on the
input will limit the input bandwidth to 1.6MHz. The source
impedance has to be kept low to avoid gain error and
degradation in the AC performance. The capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can also generate
distortion from self heating and from damage that may
occur during soldering. Metal fi lm surface mount resistors
are much less susceptible to both problems.
DC Performance
One way of measuring the transition noise associated
with a high resolution ADC is to use a technique where
a DC signal is applied to the input of the ADC and the
resulting output codes are collected over a large number
of conversions. For example, in Figure 2 the distribution
of output codes is shown for a DC input that had been
digitized 4096 times. The distribution is Gaussian and the
RMS code transition noise is about 1.6LSB.
APPLICATIONS INFORMATION
Dynamic Performance
FFT (Fast Fourier Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
Figure 2. LTC1867L Histogram for 4096 Conversions
Figure 3a. LTC1867L Nonaveraged 4096 Point
FFT Plot with 2.7V Supply
Figure 3b. LTC1867L Nonaveraged 4096 Point
FFT Plot with 3V Supply
CODE
20
7
0
COUNTS
200
400
600
800
1200
22 24 26 28
1863L7L G12
3021 23 25 27 29 31
1000
58
465
1044
895
830
261
23 91
170
333
VDD = 2.7V
INTERNAL REF
algorithm, the ADC’s spectral content can be examined
for frequencies outside the fundamental.
Signal-to-Noise Ratio
The Signal-to-Noise and Distortion Ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 3a shows a typical SINAD of 81.4dB
with a 175kHz sampling rate and a 1kHz input. Higher
SINAD can be obtained with a 3V supply. For example,
when an external 3V is applied to REFCOMP (tie VREF to
GND), a SINAD of 83.5dB can be achieved as shown in
Figure 3b.
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L G03
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 82.9dB
SINAD = 81.4dB
THD = 86.8dB
FREQUENCY (kHz)
0
–60
–40
0
65.625
1863L7L F03b
–80
–100
21.875 43.75 87.5
–120
–140
–20
AMPLITUDE (dB)
f
SAMPLE
= 175ksps
f
IN
= 1kHz
SNR = 84.7dB
SINAD = 83.5dB
THD = 90dB
REFCOMP = EXT 3V
LTC1863L/LTC1867L
12
1863l7lfc
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD VVV V
V
N
=++ +
20 2232422
1
log ...
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
Internal Reference
T
h e LT C 18 6 3 L a n d LT C 18 6 7 L h a v e a n o n - c h i p , t e m p e r a t u r e
compensated, curvature corrected, bandgap reference that
is factory trimmed to 1.25V. It is internally connected to
a reference amplifi er and is available at VREF (Pin 10). A
3k resistor is in series with the output so that it can be
easily overdriven by an external reference if better drift
and/or accuracy are required as shown in Figure 4. The
reference amplifi er gains the VREF volt age by 2 x to 2.5 V at
REFCOMP (Pin 9). This reference amplifi er compensation
APPLICATIONS INFORMATION
pin, REFCOMP, must be bypassed with a 10μF ceramic or
tantalum in parallel with a 0.1μF ceramic for best noise
performance.
Digital Interface
The LTC1863L and LTC1867L have a very simple digital
interface that is enabled by the control input, CS/CONV.
A logic rising edge applied to the CS/CONV input will initi-
ate a conversion. After the conversion, taking CS/CONV
low will enable the serial port and the ADC will present
digital data in two’s complement format in bipolar mode
or straight binary format in unipolar mode, through the
SCK/SDO serial port.
Internal Clock
The internal clock is factory trimmed to achieve a typical
conversion time of 3.2μs and a maximum conversion time,
3.7μs, over the full operating temperature range. The typi-
cal acquisition time is 1.68μs, and a throughput sampling
rate of 175ksps is tested and guaranteed.
Automatic Nap Mode
The LTC1863L and LTC1867L go into automatic nap
mode when CS/CONV is held high after the conversion
is complete. With a typical operating current of 750μA
and automatic 170μA nap mode between conversions, the
power dissipation drops with reduced sample rate. The
ADC only keeps the VREF and REFCOMP voltages active
when the part is in the automatic nap mode. The slower
the sample rate allows the power dissipation to be lower
(see Figure 5).
Figure 4b. Using the LT1790A-1.25 as an External Reference
Figure 4a. LTC1867L Reference Circuit
Figure 5. Supply Current vs fSAMPLE
R2
R3
REFERENCE
AMP
10μF
2.2μF
REFCOMP
GND
VREF
R1
3k
10
9
15
1.25V
2.5V
LTC1863L/LTC1867L
1863L7L F04a
BANDGAP
REFERENCE
10
0.1μF10μF
1863L7L F04b
LT1790A-1.25
VOUT
VIN
3V
VREF
LTC1863L/
LTC1867L
GND
REFCOMP
15
9
+
2.2μF
fSAMPLE (ksps)
1
500
SUPPLY CURRENT (μA)
600
700
800
10 100 1000
1863L7L G09
400
300
200
100
VDD = 2.7V
LTC1863L/LTC1867L
13
1863l7lfc
APPLICATIONS INFORMATION
If the CS/CONV returns low during a bit decision, it can
create a small error. For best performance ensure that the
CS/CONV returns low either within 100ns after the conver-
sion starts (i.e. before the fi rst bit decision) or after the
conversion ends. If CS/CONV is low when the conversion
ends, the MSB bit will appear on SDO at the end of the
conversion and the ADC will remain powered up.
Sleep Mode
If the SLP = 1 is selected in the input word, the ADC will
enter SLEEP mode and draw only leakage current (pro-
vided that all the digital inputs stay at GND or VDD). After
release from the SLEEP mode, the ADC needs 80ms to
wake up (charge the 2.2μF/10μF bypass capacitors on
VREF/REFCOMP pins).
Board Layout and Bypassing
To obtain the best performance, a printed circuit board
with a ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital signal alongside
an analog signal.
All analog inputs should be screened by GND. VREF, REF-
COMP and VDD should be bypassed to this ground plane
as close to the pin as possible; the low impedance of the
common return for these bypass capacitors is essential
to the low noise operation of the ADC. The width for these
tracks should be as wide as possible.
Timing and Control
Conversion start is controlled by the CS/CONV digital in-
put. The rising edge transition of the CS/CONV will start a
conversion. Once initiated, it cannot be restarted until the
conversion is complete. Figures 6 and 7 show the timing
diagrams for two types of CS/CONV pulses.
Example 1 (Figure 6) shows the LTC1863L/LTC1867L
operating in automatic nap mode with CS/CONV signal
staying HIGH after the conversion. Automatic nap mode
provides power reduction at reduced sample rate.
The ADCs can also operate with the CS/CONV signal
returning LOW before the conversion ends. In this mode
(Example 2, Figure 7), the ADCs remain powered up. The
digital output, SDO, will go HIGH immediately after the
conversion is complete if the analog inputs are above
half scale in unipolar mode or below half scale in bipolar
mode. This is a way to measure the conversion time of
the A/D converter.
F o r b e s t p e r f o r m a n c e , i t i s r e c o m m e n d e d t o k e e p S C K , S D I ,
and SDO at a constant logic high or low during acquisition
and conversion, even though these signals may be ignored
by the serial interface (DON’T CARE). Communication
with other devices on the bus should not coincide with
the conversion period (tCONV).
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar mode.
S0SD 0S S1 COM UNI SLP
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1/f
SCK
t
ACQ
CS/CONV
SCK
SDI
SDO
(LTC1863)
Hi-Z
D12D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
12345678910111213141516
1863L7L F06
DON'T CARE
NOT NEEDED FOR LTC1863
t
CONV
NAP MODE
SDO
(LTC1867)
MSB
MSB
DON'T CARE
DON'T CARE
DON'T CARE
Figure 6. Example 1, CS/CONV Starts a Conversion and Remains HIGH Until Next Data Transfer. With CS/CONV
Remaining HIGH After the Conversion, Automatic Nap Modes Provides Power Reduction at Reduced Sample Rate
LTC1863L/LTC1867L
14
1863l7lfc
APPLICATIONS INFORMATION
Figure 7. Example 2, CS/CONV Starts a Conversion With Short Active HIGH Pulse.
With CS/CONV Returning LOW Before the Conversion, the ADC Remains Powered Up
INPUT VOLTAGE (V)
OUTPUT CODE
1863L7L F09
111...111
111...110
100...001
100...000
000...000
000...001
011...110
011...111
FS – 1LSB0V
UNIPOLAR
ZERO
FS = 2.5V
1LSB = FS/2
n
1LSB (LTC1863L) = 610μV
1LSB (LTC1867L) = 38.1μV
Figure 8. LTC1863L/LTC1867L Bipolar Transfer
Characteristics (Two’s Complement)
Figure 9. LTC1863L/LTC1867L Unipolar Transfer
Characteristics (Straight Binary)
S0SD 0S S1 COM UNI SLP
MSB = D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CS/CONV
SCK
SDI
SDO
(LTC1867)
Hi-Z
12345678910111213141516
tCONV
D12MSB = D15 D14 D13 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
1863L7L F07
tCONV
DON'T CAREDON'T CARE
NOT NEEDED FOR LTC1863
tACQ
SDO
(LTC1863)
DON'T CARE
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
1863L7L F08
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FS/2 – 1LSB–FS/2
FS = 2.5V
1LSB = FS/2
n
1LSB (LTC1863L) = 610μV
1LSB (LTC1867L) = 38.1μV
LTC1863L/LTC1867L
15
1863l7lfc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibilit y is assumed for its use. Linear Technology Corporation makes no representa-
t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s .
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LTC1863L/LTC1867L
16
1863l7lfc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
LT 0209 REV C • PRINTED IN USA
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