MC74VHCT244A Octal Bus Buffer/Line Driver with 3-State Outputs The MC74VHCT244A is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHCT244A is a noninverting 3-state buffer, and has two active-low output enables. This device is designed to be used with 3-state memory address drivers, etc. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT244A input and output (when disabled) structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage-input/output voltage mismatch, battery backup, hot insertion, etc. http://onsemi.com MARKING DIAGRAMS 20 1 SOIC-20WB SUFFIX DW CASE 751D Features * * * * * * * * * * * * High Speed: tPD = 5.6 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 V to 5.5 V Operating Range Low Noise: VOLP = 1.1 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Chip Complexity: 112 FETs or 28 Equivalent Gates These Devices are Pb-Free and are RoHS Compliant VHCT244A AWLYYWWG 1 20 1 VHCT 244A ALYWG G TSSOP-20 SUFFIX DT CASE 948E 1 20 1 SOEIAJ-20 SUFFIX M CASE 967 74VHCT244 AWLYWWG 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. (c) Semiconductor Components Industries, LLC, 2011 May, 2011 - Rev. 7 1 Publication Order Number: MC74VHCT244A/D MC74VHCT244A A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 2 18 4 16 6 14 8 12 11 9 13 7 15 5 17 3 YA1 YA2 YA3 YA4 YB1 NONINVERTING OUTPUTS YB2 YB3 YB4 1 OEA 19 OEB OUTPUT ENABLES Figure 1. Logic Diagram FUNCTION TABLE OEA 1 20 VCC A1 2 19 OEB YB4 3 18 YA1 OEA, OEB A, B A2 4 17 B4 YB3 5 16 YA2 L L H LL HH XZ A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 Inputs Figure 2. Pin Assignment http://onsemi.com 2 Outputs YA, YB MC74VHCT244A IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage -0.5 to +7.0 V Vin DC Input Voltage -0.5 to +7.0 V Vout DC Output Voltage -0.5 to +7.0 -0.5 to VCC + 0.5 V IIK Input Diode Current -20 mA IOK Output Diode Current (VOUT < GND; VOUT > VCC) 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature -65 to +150 C Output in 3-State High or Low State SOIC Packages TSSOP Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating - SOIC Packages: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIII IIIIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIII III III II III IIII III III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III II III IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIIIIIIIIII IIIIIIIII IIIIII IIIII IIIII IIIIIII IIIIIII IIIIII IIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIII III III II III IIII III III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage Vin DC Input Voltage Vout DC Output Voltage TA Operating Temperature tr, tf Input Rise and Fall Time Output in 3-State High or Low State VCC = 5.0 V 0.5 V Min Max Unit 4.5 5.5 V 0 5.5 V 0 0 5.5 VCC V -40 +125 C 0 20 ns/V DC ELECTRICAL CHARACTERISTICS TA = 25C Min Symbol Parameter VIH Minimum High-Level Input Voltage 4.5 to 5.5 VIL Maximum Low-Level Input Voltage 4.5 to 5.5 VOH Minimum High-Level Output Voltage Vin = VIH or VIL IOH = -50 mA 4.5 4.4 IOH = -8 mA 4.5 3.94 Maximum Low-Level Output Voltage Vin = VIH or VIL IOL = 50 mA 4.5 IOL = 8 mA VOL Test Conditions VCC V Typ TA = - 40 to 85C Max 2.0 Min Max 2.0 0.8 4.5 0.0 TA = 85 to 125C Min Max 2.0 0.8 V 0.8 4.4 4.4 3.80 3.66 Unit V V 0.1 0.1 0.1 4.5 0.36 0.44 0.52 V Iin Maximum Input Leakage Current Vin = 5.5 V or GND 0 to 5.5 0.1 1.0 1.0 mA IOZ Maximum 3-State Leakage Current Vin = VIL or VIH Vout = VCC or GND 5.5 0.25 2.5 2.5 mA ICC Maximum Quiescent Supply Current Vin = VCC or GND 5.5 4.0 40.0 40.0 mA ICCT Quiescent Supply Current Per Input: VIN =3.4 V Other Input: VCC or GND 5.5 1.35 1.50 1.65 mA IOPD Output Leakage Current VOUT = 5.5 V 0 0.5 5.0 10 mA http://onsemi.com 3 MC74VHCT244A IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIII IIIIII IIIIII IIIIIIIII IIIIII IIIIII IIII IIIIIII IIIIIIII III II III IIII III III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIIII III II III IIII III III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIII IIIIIIII III II III IIII III III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 25C Symbol Parameter Min Test Conditions TA = - 40 to 85C TA = 85 to 125C Typ Max Min Max Min Max Unit tPLH, tPHL Maximum Propagation Delay A to YA or B to YB VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF 5.4 5.9 7.4 8.4 1.0 1.0 8.5 9.5 11.0 1.0 9.5 10.5 ns tPZL, tPZH Output Enable Time OEA to YA or OEB to YB VCC = 5.0 0.5 V CL = 15 pF RL = 1 kW CL = 50 pF 7.7 8.2 10.4 11.4 1.0 1.0 12.0 13.0 1.0 1.0 13.5 14.5 ns tPLZ, tPHZ Output Disable Time OEA to YA or OEB to YB VCC = 5.0 0.5 V CL = 50 pF RL = 1 kW 8.8 11.4 1.0 13.0 1.0 14.5 ns Output to Output Skew VCC = 5.0 0.5 V CL = 50 pF (Note 1) 1.0 ns tOSLH, tOSHL 1.0 1.0 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) Typical @ 25C, VCC = 5.0 V Symbol Min Parameter Typ Max Unit IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII CPD Power Dissipation Capacitance (Note 2) 18 Cin Maximum Input Capacitance 4 Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) 9 pF 10 pF pF 1. Parameter guaranteed by design. tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V) TA = 25C Symbol Parameter Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.9 1.1 V VOLV Quiet Output Minimum Dynamic VOL -0.9 -1.1 V VIHD Minimum High Level Dynamic Input Voltage 2.0 V VILD Maximum Low Level Dynamic Input Voltage 0.8 V ORDERING INFORMATION Package Shipping MC74VHCT244ADWRG SOIC-20WB (Pb-Free) 1000 / Tape & Reel MC74VHCT244ADTG TSSOP-20* 75 Units / Rail MC74VHCT244ADTRG TSSOP-20* 2500 / Tape & Reel MC74VHCT244AMELG SOEIAJ-20 (Pb-Free) 2000 / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 4 MC74VHCT244A 3V 1.5 V A or B GND tPLH tPHL VOH 1.5 V YA or YB VOL Figure 3. Switching Waveform 3V OEA or OEB 1.5 V tPZL YA or YB HIGH IMPEDANCE 1.5 V tPZH YA or YB GND tPLZ VOL +0.3 V tPHZ VOH -0.3 V 1.5 V HIGH IMPEDANCE Figure 4. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 5. Test Circuit TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 6. Test Circuit http://onsemi.com 5 MC74VHCT244A PACKAGE DIMENSIONS SOIC-20 WB DW SUFFIX CASE 751D-05 ISSUE G A 20 11 X 45 _ E h 1 10 20X B B 0.25 M T A S B S A L H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. q B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ MC74VHCT244A PACKAGE DIMENSIONS TSSOP-20 CASE 948E-02 ISSUE C 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V IIII IIII IIII K K1 S J J1 11 B -U- PIN 1 IDENT SECTION N-N 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A -V- N F DETAIL E C G D H DETAIL E 0.100 (0.004) -T- SEATING NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C 1.20 0.047 ----D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC -W- H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ PLANE SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 MC74VHCT244A PACKAGE DIMENSIONS SOEIAJ-20 M SUFFIX CASE 967-01 ISSUE A 20 LE 11 Q1 E HE 1 M_ L 10 DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.15 0.25 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0_ _ 0.70 0.90 --0.81 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.006 0.010 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.032 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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