7C
6C
5C
4C
3C
2C
1C
COM
7
6
5
4
3
2
1
7B
6B
5B
4B
3B
2B
1B
10
11
12
13
14
15
16
9
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ULN2003B
SLRS064B –JUNE 2014–REVISED AUGUST 2016
ULN2003B High-Voltage, High-Current Darlington Transistor Array
1
1 Features
1• Greater Than 4x Reduction in Output Leakage
(ICEX) over ULN2003A
• 500-mA Rated Collector Current (Single Output)
• High-Voltage Outputs 50 V
• Output Clamp Diodes
• Inputs Compatible With Various Types of Logic
• Relay-Driver Applications
2 Applications
• Relay Drivers
• Lamp Drivers
• Display Drivers (LED and Gas Discharge)
• Line Drivers
• Logic Buffers
3 Description
The ULN2003B device is a high-voltage, high-current
Darlington transistor array. This device consists of
seven NPN Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads. The collector-current rating
of a single Darlington pair is 500 mA. The Darlington
pairs can be paralleled for higher current capability.
The ULN2003B has a 2.7-kΩseries base resistor for
each Darlington pair for operation directly with TTL or
CMOS devices.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
ULN2003BN PDIP (16) 19.30 mm × 6.35 mm
ULN2003BD SOIC (16) 9.90 mm × 3.91 mm
ULN2003BPW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics, TA= 25°C ....................... 5
6.6 Electrical Characteristics, TA= –40°C to +105°C .... 5
6.7 Switching Characteristics, TA= 25°C........................ 5
6.8 Switching Characteristics, TA= –40°C to +105°C .... 5
6.9 Typical Characteristics.............................................. 6
7 Parameter Measurement Information .................. 9
8 Detailed Description............................................ 10
8.1 Overview................................................................. 10
8.2 Functional Block Diagram....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support................. 14
12.1 Receiving Notification of Documentation Updates 14
12.2 Community Resources.......................................... 14
12.3 Trademarks........................................................... 14
12.4 Electrostatic Discharge Caution............................ 14
12.5 Glossary................................................................ 14
13 Mechanical, Packaging, and Orderable
Information........................................................... 14
4 Revision History
Changes from Revision A (September 2014) to Revision B Page
• Deleted Hammer Drivers from Applications ........................................................................................................................... 1
• Updated Pin Functions table .................................................................................................................................................. 3
• Deleted Package Themal Information from Absolute Maximum Ratings............................................................................... 4
• Moved Storage temperature, Tstg to Absolute Maximum Ratings .......................................................................................... 4
• Deleted VIfrom Recommended Operating Conditions........................................................................................................... 4
• Updated Thermal Information table ....................................................................................................................................... 4
• Moved Operating free-air temperature, TAto Recommended Operating Conditions............................................................. 4
• Deleted Output Current vs Input Current graph from Typical Characteristics section........................................................... 6
• Added hFE vs IOUT to Typical Characteristics section.............................................................................................................. 6
• Deleted Thermal Information graphs section and updated Typical Characteristics section with new thermal graphs
Figure 6 through Figure 14..................................................................................................................................................... 6
• Added Receiving Notification of Documentation Updates section and Community Resources section.............................. 14
Changes from Original (June 2014) to Revision A Page
• Initial release of full version. .................................................................................................................................................. 1
• Added Pin Functions table...................................................................................................................................................... 3
• Added Thermal Information table........................................................................................................................................... 4
11B 16 1C
22B 15 2C
33B 14 3C
44B 13 4C
55B 12 5C
66B 11 6C
77B 10 7C
8E 9 COM
Not to scale
3
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(1) I = Input, O = Output
5 Pin Configuration and Functions
D, N, or PW Package
16-Pin SOIC, PDIP, or TSSOP
Top View
Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
1B 1
I Channel 1 through 7 darlington base input
2B 2
3B 3
4B 4
5B 5
6B 6
7B 7
1C 16
O Channel 1 through 7 darlington collector output
2C 15
3C 14
4C 13
5C 12
6C 11
7C 10
COM 9 — Common cathode node for flyback diodes (required for inductive loads)
E 8 — Common Emmitter shared by all channels (typically tied to ground)
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD= (TJ(max) – TA)/θJA. Operating at the absolute maximum TJof 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
6 Specifications
6.1 Absolute Maximum Ratings
at 25°C free-air temperature (unless otherwise noted)(1)
MIN MAX UNIT
VCC Collector-emitter voltage 50 V
Clamp diode reverse voltage(2) 50 V
VIInput voltage(2) 30 V
Peak collector current(3)(4) 500 mA
IOK Output clamp current 500 mA
Total emitter-terminal current –2.5 A
TJOperating virtual junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) 500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply Voltage 0 50 V
TAOperating free-air temperature –40 105 °C
TJJunction Temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) ULN2003B
UNITPW (TSSOP) D (SOIC) N (PDIP)
16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 105.5 81.2 49.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.3 40 36.2 °C/W
RθJB Junction-to-board thermal resistance 50.9 38.6 29.2 °C/W
ψJT Junction-to-top characterization parameter 4.1 10.5 20.2 °C/W
ψJB Junction-to-board characterization parameter 50.3 38.3 29.5 °C/W
5
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6.5 Electrical Characteristics, TA= 25°C
PARAMETER TEST FIGURE TEST CONDITIONS MIN TYP MAX UNIT
VI(on) On-state input voltage Figure 19 VCE = 2 V IC= 200 mA 2.4 VIC= 250 mA 2.7
IC= 300 mA 3
VCE(sat) Collector-emitter saturation
voltage Figure 18 II= 250 μA, IC= 100 mA 0.9 1.1 VII= 350 μA, IC= 200 mA 1 1.3
II= 500 μA, IC= 350 mA 1.2 1.6
ICEX Collector cutoff current Figure 15 VCE = 50 V, II= 0 10 μA
VFClamp forward voltage Figure 21 IF= 350 mA 1.7 2 V
II(off) Off-state input current Figure 16 VCE = 50 V, IC= 500 μA 50 65 μA
IIInput current Figure 17 VI= 3.85 V 0.93 1.35 mA
IRClamp reverse current Figure 20 VR= 50 V 50 μA
CiInput capacitance VI= 0, f = 1 MHz 15 25 pF
6.6 Electrical Characteristics, TA= –40°C to +105°C
PARAMETER TEST FIGURE TEST CONDITIONS MIN TYP MAX UNIT
VI(on) On-state input voltage Figure 19 VCE = 2 V IC= 200 mA 2.7 VIC= 250 mA 2.9
IC= 300 mA 3
VCE(sat) Collector-emitter saturation voltage Figure 18 II= 250 μA, IC= 100 mA 0.9 1.2 VII= 350 μA, IC= 200 mA 1 1.4
II= 500 μA, IC= 350 mA 1.2 1.7
ICEX Collector cutoff current Figure 15 VCE = 50 V, II= 0 20 μA
VFClamp forward voltage Figure 21 IF= 350 mA 1.7 2.2 V
II(off) Off-state input current Figure 16 VCE = 50 V, IC= 500 μA 30 65 μA
IIInput current Figure 17 VI= 3.85 V 0.93 1.35 mA
IRClamp reverse current Figure 20 VR= 50 V 100 μA
CiInput capacitance VI= 0, f = 1 MHz 15 25 pF
6.7 Switching Characteristics, TA= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 0.25 1 μs
tPHL Propagation delay time, high- to low-level output 0.25 1 μs
VOH High-level output voltage after switching VS= 50 V, IO≈300 mA VS– 20 mV
6.8 Switching Characteristics, TA= –40°C to +105°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output 1 10 μs
tPHL Propagation delay time, high- to low-level output 1 10 μs
VOH High-level output voltage after switching VS= 50 V, IO≈300 mA VS– 50 mV
Output Current IOUT
DC Current Transfer Ratio - hFE
10
20
30
50
100
200
300
500
1000
2000
3000
5000
500 mA1 mA 10 mA 100 mA
D001
TA = 25 qC
TA = -40 qC
TA = 105 qC
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
IC- Collector Current - mA
VCE(sat) - Collector-Emitter Saturation Voltage - V
0 50 100 150 200 250 300 350 400 450 500
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
D001
Iin = 250uA
Iin = 350uA
Iin = 500uA
6
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6.9 Typical Characteristics
Figure 1. Collector-Emitter Saturation Voltage vs Collector
Current (One Darlington) Figure 2. Collector-Emitter Saturation Voltage vs Total
Collector Current (Two Darlingtons in Parallel)
Figure 3. Input Current vs Input Voltage Figure 4. Collector-Emitter Saturation Voltage vs Collector
Current
Figure 5. hFE vs IOUT
TA= 25ºC
Figure 6. D Package Maximum Collector Current
vs Duty Cycle
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
7
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Typical Characteristics (continued)
TA= 25ºC
Figure 7. PW Package Maximum Collector Current
vs Duty Cycle
TA= 25ºC
Figure 8. N Package Maximum Collector Current
vs Duty Cycle
TA= 70ºC
Figure 9. D Package Maximum Collector Current
vs Duty Cycle
TA= 70ºC
Figure 10. PW Package Maximum Collector Current
vs Duty Cycle
TA= 70ºC
Figure 11. N Package Maximum Collector Current
vs Duty Cycle
TA= 105ºC
Figure 12. D Package Maximum Collector Current
vs Duty Cycle
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
Duty Cycle (DC)
Maximum Current per Channel (A)
0 20% 40% 60% 80% 100%
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
D001
1 Ch
2 Ch
3 Ch
4 Ch
5 Ch
6 Ch
7 Ch
8
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Typical Characteristics (continued)
TA= 105ºC
Figure 13. PW Package Maximum Collector Current
vs Duty Cycle
TA= 105ºC
Figure 14. N Package Maximum Collector Current vs Duty
Cycle
IF
VF
Open
Open
VCE IC
VI(on)
VR
Open
IR
Open
VCE IC
II
hFE = IC
II
Open
Open
II(on)
VI
Open VCE
IC
II(off)
Open VCE
Open
ICEX
9
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7 Parameter Measurement Information
Figure 15. ICEX Test Circuit Figure 16. II(off) Test Circuit
Figure 17. IITest Circuit Figure 18. hfe , VCE(sat) Test Circuit
Figure 19. VI(on) Test Circuit Figure 20. IRTest Circuit
Figure 21. VFTest Circuit
Output C
COM
E
3 k
2.7 k
Input B
7.2 k
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10
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8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to it's
integration of 7 Darlington transistors that are capable of sinking up to 500 mA and wide GPIO range capability.
The ULN2003B comprises seven high voltage, high current NPN Darlington transistor pairs. All units feature a
common emitter and open collector outputs. To maximize their effectiveness, these units contain suppression
diodes for inductive loads. The ULN2003B has a series base resistor to each Darlington pair, thus allowing
operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2003B offers
solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs.
Applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling
the outputs.
This device can operate over a wide temperature range (–40°C to +105°C).
8.2 Functional Block Diagram
All resistor values shown are nominal.
Figure 22. Schematic (Each Driver)
8.3 Feature Description
Each channel of ULN2003B consists of Darlington connected NPN transistors. This connection creates the effect
of a single transistor with a very high current gain. This beta can be high at certain currents see Figure 5.
The GPIO voltage is converted to base current through the 2.7-kΩresistor connected between the input and
base of the pre-driver Darlington NPN. The 7.2-kΩand 3-kΩresistors connected between the base and emitter
of each respective NPN act as pull-downs and suppress the amount of leakage that may occur from the input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diode are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
ULN2003B
IN3
IN4
OUT1
OUT2
OUT3
OUT4
IN5
IN6
IN7
GND
OUT5
OUT6
OUT7
COM
IN1
IN2
3.3V Logic
VSUP
3.3V Logic
3.3V Logic
VSUP
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11
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8.4 Device Functional Modes
8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2003B is able to drive inductive loads and suppress the
kick-back voltage through the internal free wheeling diodes.
8.4.2 Resistive Load Drive
When driving a resistive load, a pull-up resistor is needed in order for ULN2003B to sink current and for there to
be a logic high level. The COM pin can be left floating for these applications.
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
ULN2003B will typically be used to drive a high voltage and/or current peripheral from an MCU or logic device
that cannot tolerate these conditions. The following design is a common application of ULN2003B, driving
inductive loads. This includes motors, solenoids and relays. Figure 23 is a typical block diagram representation of
this application.
9.2 Typical Application
Figure 23. ULN2003B as Inductive Load Driver
( )
J(MAX) A
(MAX) JA
T T
PD -
=q
N
D OLi Li
i 1
P V I
=
= ´
å
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Typical Application (continued)
(1) These test conditions can not be run simultaneously.
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER (1) EXAMPLE VALUE
GPIO Voltage 3.3 V or 5 V
Coil Supply Voltage 12 V to 48 V
Number of Channels 7
Output Current (RCOIL) 20 mA to 300 mA per channel (See Figure 5)
Duty Cycle See Figure 6 to Figure 14
9.2.2 Detailed Design Procedure
When using ULN2003B in a coil driving application, determine the following:
• Input Voltage Range
• Temperature Range
• Output and Drive Current
• Power Dissipation
9.2.2.1 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance and output low voltage (VOL or
VCE(SAT)).
ICOIL = (VSUP – VCE(SAT)) / RCOIL (1)
9.2.2.2 Output Low Voltage
The output low voltage (VOL) is the same thing as VCE(SAT) and can be determined by, Figure 1,Figure 2, or
Figure 4.
9.2.2.3 Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by Figure 6 or Figure 7.
For a more accurate determination of number of coils possible, use Equation 2 to calculate ULN2003B on-chip
power dissipation PD:
where
• N is the number of channels active together.
• VOLi is the OUTipin voltage for the load current ILi. This is the same as VCE(SAT) (2)
In order to guarantee reliability of ULN2003B and the system the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by Equation 3.
where
• TJ(MAX) is the target maximum junction temperature.
• TAis the operating ambient temperature.
•θJA is the package junction to ambient thermal resistance. (3)
1
2
3
4
8
VCOM
7
6
5
16
E
9
15
14
13
12
11
10
1B
2B
3B
4B
7B
6B
5B
1C
2C
3C
4C
7C
6C
5C
GND
Time (s)
Output voltage - V
-0.004 0 0.004 0.008 0.012 0.016
0
1
2
3
4
5
6
7
8
9
10
11
12
13
D001
Time (s)
Output voltage - V
-0.004 0 0.004 0.008 0.012 0.016
0
2
4
6
8
10
12
14
D001
13
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TI recommends to limit ULN2003B IC’s die junction temperature to less than 125°C. The IC junction temperature
is directly proportional to the on-chip power dissipation.
9.2.3 Application Curves
The following curves were generated with ULN2003B driving an OMRON G5NB relay – Vin = 5.0V; Vsup= 12 V
and RCOIL= 2.8 kΩ
Figure 24. Output Response With Activation
of Coil (Turn On) Figure 25. Output Response With De-activation
of Coil (Turn Off)
10 Power Supply Recommendations
This part does not need a power supply; however, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to make sure that the output voltage does not exceed the COM pin
voltage. This will heavily forward bias the fly-back diodes and cause a large current to flow into COM, potentially
damaging the on-chip metal or over-heating the part.
11 Layout
11.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive UNL2003B. Care
must be taken to separate the input channels as much as possible, as to eliminate cross-talk. Thick traces are
recommended for the output, in order to drive whatever high currents that may be needed. Wire thickness can be
determined by the trace material's current density and desired drive current.
Since all of the channels currents return to a common emitter, it is best to size that trace width to be very wide.
Some applications require up to 2.5 A.
11.2 Layout Example
Figure 26. Package Layout
14
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ULN2003BDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 105 ULN2003B
ULN2003BN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU SN N / A for Pkg Type -40 to 105 ULN2003BN
ULN2003BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 105 UN2003B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 13-Jun-2016
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ULN2003BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
ULN2003BDR SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1
ULN2003BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
ULN2003BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ULN2003BDR SOIC D 16 2500 367.0 367.0 38.0
ULN2003BDR SOIC D 16 2500 364.0 364.0 27.0
ULN2003BPWR TSSOP PW 16 2000 367.0 367.0 35.0
ULN2003BPWR TSSOP PW 16 2000 364.0 364.0 27.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2016
Pack Materials-Page 2
IMPORTANT NOTICE
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Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
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Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
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ULN2003BN ULN2003BPWR ULN2003BDR