Document Number: 91210 www.vishay.com
S11-0445-Rev. B, 21-Mar-11 1
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Power MOSFET
IRFP240, SiHFP240
Vishay Siliconix
FEATURES
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Isolated Central Mounting Hole
•Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The TO-247AC package is preferred for
commercial-industrial applications where higher power
levels preclude the use of TO-220AB devices. The
TO-247AC is similar but superior to the earlier TO-218
package because its isolated mounting hole. It also provides
greater creepage distances between pins to meet the
requirements of most safety specifications.
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 1.9 mH, Rg = 25 , IAS = 20 A (see fig. 12).
c. ISD 18 A, dI/dt 150 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
PRODUCT SUMMARY
VDS (V) 200
RDS(on) ()V
GS = 10 V 0.18
Qg (Max.) (nC) 70
Qgs (nC) 13
Qgd (nC) 39
Configuration Single
N-Channel MOSFET
G
D
S
TO-247AC
G
D
S
Available
RoHS*
COMPLIANT
ORDERING INFORMATION
Package TO-247AC
Lead (Pb)-free IRFP240PbF
SiHFP240-E3
SnPb IRFP240
SiHFP240
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER SYMBOL LIMIT UNIT
Drain-Source Voltage VDS 200 V
Gate-Source Voltage VGS ± 20
Continuous Drain Current VGS at 10 V TC = 25 °C ID
20
A
TC = 100 °C 12
Pulsed Drain CurrentaIDM 80
Linear Derating Factor 1.2 W/°C
Single Pulse Avalanche EnergybEAS 510 mJ
Repetitive Avalanche CurrentaIAR 20 A
Repetitive Avalanche EnergyaEAR 15 mJ
Maximum Power Dissipation TC = 25 °C PD150 W
Peak Diode Recovery dV/dtcdV/dt 5.0 V/ns
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C
Soldering Recommendations (Peak Temperature) for 10 s 300d
Mounting Torque 6-32 or M3 screw 10 lbf · in
1.1 N · m
* Pb containing terminations are not RoHS compliant, exemptions may apply
www.vishay.com Document Number: 91210
2S11-0445-Rev. B, 21-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width 300 μs; duty cycle 2 %.
THERMAL RESISTANCE RATINGS
PARAMETER SYMBOL TYP. MAX. UNIT
Maximum Junction-to-Ambient RthJA -40
°C/WCase-to-Sink, Flat, Greased Surface RthCS 0.24 -
Maximum Junction-to-Case (Drain) RthJC -0.83
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 200 - - V
VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.29 - V/°C
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-Source Leakage IGSS V
GS = ± 20 V - - ± 100 nA
Zero Gate Voltage Drain Current IDSS
VDS = 200 V, VGS = 0 V - - 25 μA
VDS = 160 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-Source On-State Resistance RDS(on) V
GS = 10 V ID = 12 Ab--0.18
Forward Transconductance gfs VDS = 50 V, ID = 12 Ab6.9 - - S
Dynamic
Input Capacitance Ciss VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
- 1300 -
pFOutput Capacitance Coss - 400 -
Reverse Transfer Capacitance Crss - 130 -
Total Gate Charge Qg
VGS = 10 V ID = 18 A, VDS = 160 V,
see fig. 6 and 13b
--70
nC Gate-Source Charge Qgs --13
Gate-Drain Charge Qgd --39
Turn-On Delay Time td(on)
VDD = 100 V, ID = 18 A,
Rg = 9.1 , RD = 5.4,
see fig. 10b
-14-
ns
Rise Time tr -51-
Turn-Off Delay Time td(off) -45-
Fall Time tf -36-
Internal Drain Inductance LD Between lead,
6 mm (0.25") from
package and center of
die contact
-5.0-
nH
Internal Source Inductance LS-13-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS
MOSFET symbol
showing the
integral reverse
p - n junction diode
--20
A
Pulsed Diode Forward CurrentaISM --80
Body Diode Voltage VSD TJ = 25 °C, IS = 20 A, VGS = 0 Vb--2.0V
Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 18 A, dI/dt = 100 A/μsb- 300 610 ns
Body Diode Reverse Recovery Charge Qrr -3.47.1μC
Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
D
S
G
S
D
G
Document Number: 91210 www.vishay.com
S11-0445-Rev. B, 21-Mar-11 3
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
www.vishay.com Document Number: 91210
4S11-0445-Rev. B, 21-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91210 www.vishay.com
S11-0445-Rev. B, 21-Mar-11 5
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10a - Switching Time Test Circuit
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
R
D
V
GS
R
G
D.U.T.
10 V
+
-
V
DS
V
DD
VDS
90 %
10 %
VGS
td(on) trtd(off) tf
www.vishay.com Document Number: 91210
6S11-0445-Rev. B, 21-Mar-11
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit
R
G
I
AS
0.01 Ω
t
p
D.U.T
L
VDS
+
-V
DD
10 V
Vary t
p
to obtain
required I
AS
IAS
VDS
VDD
VDS
tp
QGS QGD
QG
V
G
Charge
10 V
Document Number: 91210 www.vishay.com
S11-0445-Rev. B, 21-Mar-11 7
This datasheet is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DATASHEET ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFP240, SiHFP240
Vishay Siliconix
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91210.
P.W. Period
dI/dt
Diode recovery
dV/dt
Ripple ≤ 5 %
Body diode forward drop
Re-applied
voltage
Reverse
recovery
current
Body diode forward
current
VGS = 10 Va
ISD
Driver gate drive
D.U.T. lSD waveform
D.U.T. VDS waveform
Inductor current
D = P.W.
Period
+
-
+
+
+
-
-
-
Peak Diode Recovery dV/dt Test Circuit
VDD
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
D.U.T. Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
Rg
Note
a. VGS = 5 V for logic level devices
VDD
Package Information
www.vishay.com Vishay Siliconix
Revision: 08-Jan-2020 1Document Number: 91360
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TO-247AC (High Voltage)
VERSION 1: FACILITY CODE = 9
Notes
(1) Package reference: JEDEC® TO247, variation AC
(2) All dimensions are in mm
(3) Slot required, notch may be rounded
(4) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the
outermost extremes of the plastic body
(5) Thermal pad contour optional with dimensions D1 and E1
(6) Lead finish uncontrolled in L1
(7) Ø P to have a maximum draft angle of 1.5° to the top of the part with a maximum hole diameter of 3.91 mm
(8) Dimension b2 and b4 does not include dambar protrusion. Allowable dambar protrusion shall be 0.1 mm total in excess of b2 and b4
dimension at maximum material condition
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.83 5.21 D1 16.25 16.85 5
A1 2.29 2.55 D2 0.56 0.76
A2 1.50 2.49 E 15.50 15.87 4
b 1.12 1.33 E1 13.46 14.16 5
b1 1.12 1.28 E2 4.52 5.49 3
b2 1.91 2.39 6 e 5.44 BSC
b3 1.91 2.34 L 14.90 15.40
b4 2.87 3.22 6, 8 L1 3.96 4.16 6
b5 2.87 3.18 Ø P 3.56 3.65 7
c 0.55 0.69 6 Ø P1 7.19 ref.
c1 0.55 0.65 Q 5.31 5.69
D 20.40 20.70 4 S 5.54 5.74
Package Information
www.vishay.com Vishay Siliconix
Revision: 08-Jan-2020 2Document Number: 91360
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VERSION 2: FACILITY CODE = Y
Notes
(1) Dimensioning and tolerancing per ASME Y14.5M-1994
(2) Contour of slot optional
(3) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
(4) Thermal pad contour optional with dimensions D1 and E1
(5) Lead finish uncontrolled in L1
(6) Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154")
(7) Outline conforms to JEDEC outline TO-247 with exception of dimension c
MILLIMETERS MILLIMETERS
DIM. MIN. MAX. NOTES DIM. MIN. MAX. NOTES
A 4.58 5.31 D2 0.51 1.30
A1 2.21 2.59 E 15.29 15.87
A2 1.17 2.49 E1 13.72 -
b 0.99 1.40 e 5.46 BSC
b1 0.99 1.35 Ø k 0.254
b2 1.53 2.39 L 14.20 16.25
b3 1.65 2.37 L1 3.71 4.29
b4 2.42 3.43 Ø P 3.51 3.66
b5 2.59 3.38 Ø P1 - 7.39
c 0.38 0.86 Q 5.31 5.69
c1 0.38 0.76 R 4.52 5.49
D 19.71 20.82 S 5.51 BSC
D1 13.08 -
ECN: E19-0614-Rev. E, 08-Jan-2020
DWG: 5971
0.10 AC
M M
E
E/2
(2)
(4)
R/2
B
2 x R
S
D
See view B
2 x e
b4
3 x b
2 x b2
L
C
L1
123
Q
D
A
A2
A
A
A1
C
Ø k BD
M M
A
ØP (Datum B)
ØP1
D1
4
E1
0.01 BD
M M
View A - A
Thermal pad
D2
DDE E
CC
View B
(b1, b3, b5) Base metal
c1
(b, b2, b4)
Section C - C, D - D, E - E
(c)
Planting
4
3
5
7
4
4
4
Lead Assignments
1. Gate
2. Drain
3. Source
4. Drain
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Revision: 01-Jan-2019 1Document Number: 91000
Disclaimer
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