6.4 mm (0.252") 4-Character 5 x 7 Dot Matrix X-Y Stackable Industrial Alphanumeric Programmable DisplayTM with Built-in CMOS Control Functions RoHS Compliant - By Exemption (see page 10) High Efficiency Red IPD2545A Green IPD2547A Yellow IPD2548A FEATURES * Four 6.4 mm (0.252") Dot Matrix Characters in Hermetic Package * Built-in Memory, Decoders, Multiplexer and Drivers * Viewing Angle, X axis 40, Y axis 75 * 128 Character ASCII Format (Upper and Lower Case Characters) * Rugged Ceramic Package, Hermetic Sealed Flat Glass Window * Wide Temperature Operating Range for Industrial Use, -55C to +100C * 8-bit Bidirectional Data BUS * READ/WRITE Capability * Built-in Character Generator ROM * TTL Compatible * Easily Cascaded for Multidisplay Operation * Less CPU Time Required * Software Controlled Features: * Programmable Highlight Attribute (Blinking, Non-Blinking) * Asynchronous Memory Clear Function * Lamp Test * Display Blank Function * Single or Multiple Character Blinking Function * Three Programmable Brightness Levels DESCRIPTION The IPD2545A (high efficiency red), IPD2547A (green), and IPD2548A (yellow) are four digit, High Reliability/Industrial, dot matrix, Programmable Displays that are aimed at satisfying the most demanding industrial display requirements. They are designed for use in harsh environments. The devices are constructed in a hermetic package using four 6.4 mm (0.252'') high 5 x 7 dot matrix displays. The devices incorporate the latest in CMOS technology which is the heart of the device intelligence. The CMOS controller chip is controlled by a user supplied eight bit data word on the bidirectional BUS. The ASCII data and attribute data are word driven. This approach allows the IPD254XA to interface using the same techniques as a microprocessor peripheral. Applications include: control panels, night viewing applications (red light), cockpit monitors, night vision goggle viewable displays (green), portable and vehicle technology as well as industrial controllers. Ordering Information Type Color of Emission Character Height mm (inch) Ordering Code IPD2545A high efficiency red 6.4 (0.252) Q68000A9883 IPD2547A green 6.4 (0.252) Q68000A9884 IPD2548A yellow 6.4 (0.252) on request 2006-03-03 1 IPD2545A, IPD2547A, IPD2548A 4.83 (0.190) 1) 2.54 (0.100) typ. 1) 0.508 (0.020) x 0.254 (0.010) typ. 2) 4.57 (0.180) typ. 1) Dimensions in mm (inch) 4.32 (0.170) 1) Package Outlines 12.7 (0.500) 1) 3.81 (0.150) ref. 2) 30.48 (1.200) max. 2) 3.81 (0.150) ref. 2) 4.32 (0.170) typ. 2) OSRAM Pin 1 Indicator 6.4 (0.252) 2) 12.45 (0.490) max. 2) 7.62 (0.300) typ. 2) YYWW Part No. Pin 1 Z 1) 2) Tolerance: 0.254 (0.010) Tolerance: 0.127 (0.005) Intensity Code EIA Date Code IDOD5208 Maximum Ratings Parameter Symbol Value Unit Operating temperature range Top - 55 ... +100 C Storage temperature range Tstg - 65 ... +125 C DC Supply Voltage -0.5 to +6.0 Vdc Input Voltage Relative to GND (all inputs) -0.5 to VCC +0.5 Vdc 30 C/W JC Thermal Resistance Important: Refer to Appnote 18, "Using and Handling Intelligent Displays". Since this is a CMOS device, normal precautions should be taken to avoid static damage. 2006-03-03 2 IPD2545A, IPD2547A, IPD2548A Top View Timing Characteristics--Data "Write" Cycle 20 11 2.0 V 0.8 V * CE0, CE1 TCES TCEH TAS TAH 2.0 V 0.8 V * A0, A1 Digit 3 Digit 2 Digit 1 Pin 1 Digit 0 2.0 V 0.8 V * D0-D6 10 TDS TDH RD TRH TRS 2.0 V 0.8 V * WR 2.0 V 0.8 V * Pin Assignments TW 1 RD Read 11 WR Write 2 CLK I/O Clock I/O 12 D7 Data MSB 3 CLKSEL Clock Select 13 D6 Data 4 RST Reset 14 D5 Data 5 CE1 Chip Enable 15 D4 Data 6 CE0 Chip Enable 16 D3 Data 7 A2 Address MSB 17 D2 Data 8 A1 Address 18 D1 Data 9 A0 Address LSB 19 D0 Data LSB 10 GND -- 20 VCC -- TACC Timing Characteristics--Data "Read" Cycle CE0, CE1 TCES TCEH TAS TAH A0-A3 DATA OUT D0-D6 TDD WR 2.0 V 0.8 V * 2.0 V 0.8 V * 2.0 V 0.8 V * 2.0 V 0.8 V * 2.0 V 0.8 V * TDH TRI TWS TWH RD TR TRACC Notes: 1. All input voltages are VIL=0.8 V, VIH=2.0 V. 2. These waveforms are not edge triggered. DC Characteristics Parameter -55C +25C +100C Units Condition 2.5 mA VCC=5.0 V (A2=1; all other inputs low) 125 160 mA VCC=5.0 V, 20 dots/digit (100% brightness) -- 50 80 mA VCC=5.0 V, VIH=0.8 V -- 2.0 -- -- V VCC=5.0 V 0.5 V 0.8 -- -- 0.8 V VCC=5.0 V 0.5 V Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. ICC Blank -- 4.0 10 -- 2.0 5.0 -- 1.0 ICC -- 220 250 -- 160 190 -- IIL (all inputs) -- 70 120 -- 60 100 VIH (all inputs) 2.0 -- -- 2.0 -- VIL (all inputs) -- -- 0.8 -- -- 2006-03-03 3 IPD2545A, IPD2547A, IPD2548A Optical Characteristics High Efficiency Red IPD2545A Symbol Min. Typ.4) Units Test Conditions IV ave 75 150 cd VCC=5.0 V, # sign ''ON'' on all digits at full brightness, TA=25C peak -- 635 nm -- dom -- 626 nm -- Symbol Min. Typ.4) Units Test Conditions IV ave 75 150 cd VCC=5.0 V, # sign ''ON'' on all digits at full brightness, TA=25C Peak Wavelength peak -- 568 nm -- Dominant Wavelength 2) dom -- 574 nm -- Symbol Min. Typ.4) Units Test Conditions IV ave 75 150 cd VCC=5.0 V, # sign ''ON'' on all digits at full brightness, TA=25C peak -- 585 nm -- dom -- 590 nm -- Description Peak Luminous Intensity per LED (Character Average) 1) 3) Peak Wavelength Dominant Wavelength 2) Green IPD2547A Description Peak Luminous Intensity per LED (Character Average) 1) 3) Yellow IPD2548A Description Peak Luminous Intensity per LED (Character Average) Peak Wavelength Dominant Wavelength 2) 1) 3) Notes: 1) The displays are categorized for luminous intensity with the intensity category designated by a letter code on the bottom of the package. 2) Dominant wavelength dom is derived from the CIE chromaticity diagram and represents the single wavelength which defines the color of the device. 3) The luminous stearance of the LED may be calculated using the following relationships. LV (cd/m2) = IV (Candela) /A (Meter)2 LV (Footlamberts) = IV (Candela) /A (Foot)2 A=8.4 x 10-7 ft2, 7.8 x 10-8 m2 4) All typical values specified at VCC=5.0 V and TA=25C unless otherwise noted. 2006-03-03 4 IPD2545A, IPD2547A, IPD2548A Pin Definitions Pin Function Definition Pin Function Definition 1 RD Active low, will enable a processor to read all registers. 11 WR Write. Active low. If the device is selected, a low on the write input loads the data into memory. 2 CLK I/O If CLK SEL (pin 3) is low, then expect an external clock source into this pin. If CLK SEL is high, then this pin will be the master or source for all other devices which have CLK SEL low. 12 D7 Data Bus bit 7 (MSB). 3 CLKSEL CLocK SELect determines the action of pin 2, CLK I/O. See section on Cascading for an example. 13 D6 Data Bus bit 6. 4 RST Reset. The Reset pulse should be less than 1 ms. Reset is used only to synchronize blinking and will not clear the display. 14 D5 Data Bus bit 5. 5 CE1 Chip enable (active high). 15 D4 Data Bus bit 4. 6 CE0 Chip enable (active low). 16 D3 Data Bus bit 3. 7 A2 Address input (MSB). 17 D2 Data Bus bit 2. 8 A1 Address input. 18 D1 Data Bus bit 1. 9 A0 Address input (LSB). 19 D0 Data Bus bit 0 (LSB). 10 GND Ground. 20 VCC Positive power pin. 2006-03-03 5 IPD2545A, IPD2547A, IPD2548A Switching Specifications (VCC=4.5 V) Write Cycle Timing Parameter Description Specification Minimum -55C +25C +100C Units TCLR(1) Clear RAM 1.0 1.0 1.0 s TCLRD(1) Clear RAM Disable 1.0 1.0 1.0 s TAS Address Setup 10 10 10 ns TCES Chip Enable Setup 0 0 0 ns TRS Read Enable Setup 10 10 10 ns TDS Data Setup 20 30 50 ns TW Write Pulse 60 70 90 ns TAH Address Hold 20 30 40 ns TDH Data Hold 20 30 40 ns TCEH Chip Enable Hold 0 0 0 ns TRH Read Enable Hold 20 30 40 ns TACC Total Access Time = Setup Time + Write Time + Hold Time 90 110 140 ns Switching specifications (VCC=4.5 V) Read Cycle Timing Parameter Description Specification Minimum -55C +25C +100C Units TAS Address Setup 0 0 0 ns TCES Chip Enable 0 0 0 ns TWS Write Enable Setup 20 30 40 ns TDD Data Delay Time 100 150 175 ns TR Read Pulse 150 175 200 ns TAH Address Hold 0 0 0 ns TDH Data Hold 0 0 0 ns TTRI Time to Tristate (Max. time) 30 40 50 ns TCEH Chip Enable Hold 0 0 0 ns TWH Write Enable Hold 30 40 50 ns TRACC Total Access Time = Setup Time + Read Time + Time to Tristate 200 245 290 ns TWAIT (1) Wait Time between Reads 0 0 0 ns Notes: 1) Wait 1.0 ms between any Reads or Writes after writing a Control Word with a Clear (D7=1). Wait 1.0 s between any Reads or Writes after Clearing a Control Word with a Clear (D7=0). All other Reads and Writes can be back to back. 2) All input voltages are (VIL=0.8 V, VIH=2.0 V) 3) Data out voltages are measured with 100 pF on the data bus and the ability to source = -40 A and sink=1.6 mA The rise and fall times are 60 ns. VOL=0.4 V, VOH=2.4 V. 2006-03-03 6 IPD2545A, IPD2547A, IPD2548A Block Diagram 8 D0-D7 14 Control Reg 1x8 Display Memory (RAM) 4 x 8 The Control Logic dictates all of the features of the display device and is discussed in the Control Word section of this data sheet. The Character Generator converts the 7-bit ASCII data into the proper dot pattern for the 128 characters shown in the character set chart. The Clock Source can originate either from the internal oscillator clock or from an external source-usually from the output of another IPD2545/7/8A in a multiple module display. The Display Multiplexer controls all display output to the digit drivers so no additional logic is required for a display system. The Column Drivers are connected directly to the display. The Display has four digits. Each of the four digits is comprised of 35 LEDs in a 5 x 7 dot array which makes up the alphanumeric characters. The intensity of the display can be varied by the Control Word in steps of 0% (Blank), 25%, 50%, and full brightness. The Reset pin when activated clears the internal counter. A reset is usually done after power up and is of very short duration-nanoseconds or microseconds. If the reset pin is held low for a longer time (milliseconds) some or all LEDs in the bottom row may light up. The appearance of lit LEDs during a "reset" is not an indication of a malfunctioning part. It is advisable to keep the reset pulse as short as possible to avoid displaying a row of lit LEDs. 128 Char ROM 128 x 5 8 4 CE0, CE1 A0-A2 RD, WR 15 1 Decode and Mux 7 Output Control Logic 5 Output Latch 1 CLK SEL XCLK RST 3 OSC Logic 20 Column Drivers Display Multiplexer 3 3 20 Row Drivers Display IDBD5065 Microprocessor Interface Functional Description The interface to the microprocessor is through the address lines. (A0-A2), the data bus (D0-D7), two chip select lines (CE0, CE1), and read (RD) and write (WR) lines. The CE0 should be held low when executing a read, or write operation. CE1 must be held high. The read and write lines are both active low. During a valid read the data lines (D0-D7) become outputs. A valid write will enable the data lines as inputs. The block diagram includes 5 major blocks and internal registers (indicated by dotted lines). Display Memory consists of a 5 x 8 bit RAM block. Each of the four 8-bit words holds the 7-bits of ASCII data (bits D0-D6) and an attribute select bit (Bit D7). The fifth 8-bit memory word is used as a control word register. A detailed description of the control register and its functions can be found under the heading Control Word. Each 8-bit word is addressable and can be read from or written to. Input Buffering Mode Selection CEO CE1 RD WR Operation 0 1 0 0 None 1 X X X None X 0 X X None X X 1 1 None If a cable length of 6 inches or more is used, all inputs to the display should be buffered with a tri-state non-inverting buffer mounted as close to the display as conveniently possible. Recommended buffers are: 74LS245 for the data lines and 74LS244 for the control lines. 0=Low logic level, 1=High logic level, X=Don't care Data Input Commands CEO CE1 RD WR A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 1 0 X X X X X X X X X X X X X No Change 0 1 0 1 1 0 0 X X X X X X X X Read Digit 0 Data to Bus 0 1 1 0 1 0 0 0 0 1 0 0 1 0 0 ($) Written to Digit 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 (W) Written to Digit 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 (f) Written to Digit 2 0 1 1 0 1 1 1 0 0 1 1 0 0 1 1 (3) Written to Digit 3 0 1 1 0 1 0 0 1 X X X X X X X Char. Written to Digit 0 and Cursor Enabled 2006-03-03 7 IPD2545A, IPD2547A, IPD2548A Programming the IPD2545/7/8A Control Word There are five registers within the IPD2545/7/8A display. Four of these registers are used to hold the ASCII/attribute code of the four display characters. The fifth register is the Control Word, which is used to blink, blank, clear, or dim the entire display, or to change the presentation (attributes) of individual characters. When address bit A2 is taken low, the Control Word is accessed. The same Control Word appears in all four of the lower address spaces of the display. Through the Control Word, the display can be cleared, the lamps can be tested, display brightness can be selected, and attributes can be set for any characters which have been loaded with their most significant bit (D7) set high. Brightness (D0, D1): The state of the lower two bits of the Control Word are used to set the brightness of the entire display, from 0% to 100%. The table below shows the correspondence of these bits to the brightness. Addressing The addresses within the display device are shown below. Digit 0 is the rightmost digit of the display, while Digit 3 is on the left. Although there is only one Control Word, it is duplicated at the four address locations 0-3. Data can be read from any of these locations. When one of these locations is written to, all of them will change together. Address A2 0 1 Contents A1 A0 X X 0 Control Word 0 Digit 0 (rightmost) D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 X X X X 0 0 Blank 0 0 X X X X 0 1 25% brightness 0 0 X X X X 1 0 50% brightness 0 0 X X X X 1 1 Full brightness X=don't care 1 0 1 Digit 1 1 1 0 Digit 2 1 1 1 Digit 3 (leftmost) Attributes (D2-D4): Bits D2, D3, and D4 control the visual attributes (i.e., blinking, alternate) of those display digits which have been written with bit D7 set high. In order to use any of the four attributes, the Cursor Enable bit (D4 in the Control Word) must be set. When the Cursor Enable bit is set, and bit D7 in a character location is set, the character will take on one of the following display attributes. Bit D7 of any of the display digit locations is used to allow an attribute to be assigned to that digit. The attributes are discussed in the next section. If Bit D7 is set to a one, that character will be displayed using the attribute. If bit D7 is cleared, the character will display normally. Control Word Format D7 D6 D5 D4 Clear Lamp Test Blink Attribute Enable D3 D2 Attributes D1 D0 Brightness D1 0 0 D3 D2 Attributes 1 0 0 Display cursor instead 1 of character 0 1 Blink character 1 0 Display blinking cursor instead of character 1 1 Alternate character with cursor D0 0 1 0 1 Brightness 0% (blank) 25% 50% 100% D4 Attribute Enable 0 Disable above attributes 1 Enable above attributes D5 Blink 0 Blink attribute disabled 1 Blink entire display D6 Lamp Test 0 Standard operation 1 Display all dots at 50% brightness D7 Clear 0 Standard operation 1 Clear entire display IDCW5163 2006-03-03 8 IPD2545A, IPD2547A, IPD2548A D7 D6 D5 D4 D3 D2 D1 D0 Operation D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 X X B B Disable highlight attribute 0 1 0 0 X X X X Lamp test 0 0 0 1 0 0 B B Display cursor* instead of character 0 0 0 1 0 1 B B Blink single character 0 0 0 1 1 0 B B Display blinking cursor* instead of character 0 0 0 1 1 1 B B Clear Data (D7): When D7 (D7=1) is set in the Control Word, all display memory bits are reset to zero. A second Control Word must be written into the chip with D7 (D7=0) reset to set up attributes and brightness levels. Alternate character with cursor* D6 D5 D4 D3 D2 D1 D0 Operation 0 1 X X X B B Blinking display D5 D4 D3 D2 D1 D0 Operation 0 X X X X X X Clear Cascading the display (Figure below) is a simple operation. The requirements for cascading are: 1) decoding the correct address to determine the chip select for each additional device, 2) assuring that all devices are reset simultaneously, and 3) selecting one display as the clock source and setting all others to accept clock input (the reason for cascading the clock is to synchronize the flashing of multiple displays). One display as a source is capable of driving six other displays. If more displays are required, a buffer will be necessary. The source display must have pin 3 tied high to output clock signals. All other displays must have pin 3 tied low. Attributes are non-destructive. If a character with bit D7 set is replaced by a cursor (Control Word bit D4 is set, and D3=D2=0) the character will remain in memory and can be revealed again by clearing D4 in the Control Word. Blink (D5): The entire display can be caused to blink at a rate of approximately 2.0 Hz by setting bit D5 in the Control Word. This blinking is independent of the state of D7 in all character locations. To synchronize the blink rate in a bank of these devices, it is necessary to tie all devices' clocks and resets together as described in a later section of this data sheet. 0 D6 1 Cascading *"Cursor"= all dots in a single character space lit to half brightness X = don't care B = depends on the selected brightness D7 D7 Voltage Transients It has become common practice to provide 0.01 F bypass capacitors liberally in digital systems. Like other CMOS circuitry, the Intelligent Display controller chip has very low power consumption and the usual 0.01 F would be adequate were it not for the LEDs. To prevent power supply transients, capacitors with low inductance and high capacitance at high frequencies are required. This suggests a solid tantalum or ceramic disc for high frequency bypass. For larger displays, distribute the bypass capacitors evenly, keeping capacitors as close to the power pins as possible. We recommend a 10 F and 0.01 F for every Intelligent Display to decouple the displays themselves, at the display. Lamp Test (D6): When the Lamp Test bit is set, all dots in the entire display are lit at half brightness. When this bit is cleared, the display returns to the characters that were showing before the lamp test. CLK SEL CLK I/O RESET D0-D7 A0-A2 20 VCC WR RD CE1 CE0 0.01 F 10 10 0.01 F L CLK SEL CLK I/O RESET D0-D7 A0-A2 20 VCC WR RD CE1 CE0 10 F L 10 0.01 F L H CLK SEL CLK I/O RESET D0-D7 A0-A2 20 VCC WR RD CE1 CE0 0.01 F 10 10 F CLK SEL CLK I/O RESET D0-D7 A0-A2 20 VCC WR RD CE1 CE0 Cascading the Display RESET D0-D7 A0-A2 WR RD VCC A3 A4 A5 VCC 6 16 74LS138 12 1 13 2 14 3 15 4 8 5 IDCD5039 2006-03-03 9 IPD2545A, IPD2547A, IPD2548A How to Load Information into the IPD25545/7/8A Information loaded into the IPD2545/7/8A can be either ASCII data or Control Word data. The following procedure (see also Typical Loading Sequence) will demonstrate a typical loading sequence and the resulting visual display. The word STOP is used in all of the following examples. Set Brightness Step 1 Set the brightness level of the entire display to your preference (example: 100%). Load Four Characters Step 2 Load a "S" in the left hand digit. Step 3 Load a "T" in the next digit. Step 4 Load an "O" in the next digit. Step 5 Load a "P" in the right hand digit. If you loaded the information correctly, the IPD2545A now should show the word "STOP." Blink a Single Character Step 6 Into the digit, second from the right, load the hex code "CF," which is the code for an "O" with the D7 bit added as a control bit. Note: The "O" is the only digit which has the control bit (D7) added to normal ASCII data. Step 7 Load enable blinking character into the control word register. The display now should show "STOP" with a flashing "O". Add Another Blinking Character Step 8 Into the left hand digit, load the hex code "D3" which gives an "S" with the D7 bit added as a control bit. The display should show "STOP" with flashing "O" and a flashing "S." Alternate Character/Cursor Enable Step 9 Load enable alternate character/cursor into the control word register. The display now should show "STOP" with the "O" and the "S" alternating between the letter and cursor (all dots lit). Initiate Four Character Blinking (Regardless of Control Bit setting) Step 10 Load enable display blinking. The display now should show the entire word "STOP" blinking. Electrical and Mechanical Considerations The CMOS IC of the IPD2545/7/8A are designed to provide resistance to both Electrostatic and Discharge Damage and Latch Up due to voltage or current surges. Several precautions are strongly recommended for the user, to avoid overstressing these built-in safeguards. ESD Protection Users of the IPD2545/7/8A should be careful to handle the devices consistent with standard ESD protection procedures. Operators should wear appropriate wrist, ankle or feet ground straps and avoid clothing that collects static charges. Work surfaces, tools and transport carriers that come into contact with unshielded devices or assemblies also should be appropriately grounded. Latch up Protection Latch up is condition that occurs in CMOS ICs after the input protection diodes have been broken down. These diodes can be reversed through several means. VIN<GND, VIN>VCC +0.5 V, or through excessive currents begin forced on the inputs. When these situations exist, the IC may develop the response of an SCR and begin conducting as much as one amp through the VCC pin. This destructive condition will persist (latched) until device failure or the device is turned off. The Voltage Transient Suppression Techniques and buffer interfaces for longer cable runs help considerably to prevent latch conditions from occurring. Additionally, the following Power Up and Power Down sequence should be observed. RoHS Compliance The IPD2547A, IPD2545A, IPD2548A Intelligent DisplaysTM are hermetically sealed displays using a ceramic and glass construction. These components are not lead (Pb) free but are RoHS Compliant based on the RoHS Compliance Directive's Annex, paragraphs 5 and 7. These exemptions allow for lead (Pb) in glass and ceramic electronic components. Refer to the following excerpts from the RoHS Compliance Directive Annex: Applications of lead, mercury, cadmium and hexavalent chromium, which are exempted from the requirements of Article 4(1) 5. Lead in glass of cathode ray tubes, electronic components and fluorescent tubes. 7. Lead in electronic ceramic parts (e.g. piezoelectronic devices). Typical Loading Sequence CEO CE1 RD WR A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1. L H H L L X X 0 0 0 0 0 0 1 1 2. L H H L H H H 0 1 0 1 0 0 1 1 S 3. L H H L H H L 0 1 0 1 0 1 0 0 ST 4. L H H L H L H 0 1 0 0 1 1 1 1 STO 5. L H H L H L L 0 1 0 1 0 0 0 0 STOP 6. L H H L H L H 1 1 0 0 1 1 1 1 STOP 7. L H H L L X X 0 0 0 1 0 1 1 1 STO*P 8. L H H L H H H 1 1 0 1 0 0 1 1 S*TO*P 9. L H H L L X X 0 0 0 1 1 1 1 1 STOP 10. L H H L L X X 0 0 1 0 0 0 1 1 S*T*O*P* * Blinking character, Character alternating with cursor (all dots lit) 2006-03-03 10 Display IPD2545A, IPD2547A, IPD2548A Power up Sequence 1. 2. 3. Float all active signals by tri-stating the inputs to the displays. Apply VCC and GND to the display. Apply active signals to the displays by enabling all input signals per applications. Power Down Sequence 1. 2. Float all active signals by tri-stating the inputs to the displays. Turn off the power to the display. Character Set D0 D1 D2 D3 D6 D5 D4 HEX ASCII CODE 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 0 0 0 0 0 1 0 0 0 1 0 1 0 0 2 1 1 0 0 3 0 0 1 0 4 1 0 1 0 5 0 1 1 0 6 1 1 1 0 7 0 0 0 1 8 1 0 0 1 9 0 1 0 1 A 1 1 0 1 B 0 0 1 1 C 1 0 1 1 D 0 1 1 1 E 1 1 1 1 F IDCS5087 Notes: 1.High=1 level 2.Low=0 level 3.Upon power up, the device will initialize in a random state. 4.A2 must be held high for ASCII data. 5.Bit D7=1 enables attributes for the assigned digit. 2006-03-03 11 IPD2545A, IPD2547A, IPD2548A Revision History: 2006-03-03 Previous Version: 2004-11-11 Page Subjects (major changes since last revision) Date of change all complete rework 2004-09-16 all RoHS Compliant - By Exemption 2006-03-03 Published by OSRAM Opto Semiconductors GmbH Wernerwerkstrasse 2, D-93049 Regensburg www.osram-os.com (c) All Rights Reserved. Attention please! The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact our Sales Organization. If printed or downloaded, please find the latest version in the Internet. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS. 1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system. 2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered. 2006-03-03 12