Publication Number S29AL016D_00 Revision A Amendment 2 Issue Date December 17, 2004
PRELIMINARY
S29AL016D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write op-
erations for battery-powered applications
Manufactured on 200nm process technology
— Fully compatible with 0.23 µm Am29LV160D and
MBM29LV160E de vi ces
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-
one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 K word, one 16 Kword, and thirty-
one 32 Kword sectors (word mode)
Sector Protection features
— A hardware method of locking a sector to prevent any
program or erase operati o ns withi n that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
Top or bottom boot block configurations
available
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Performance Characteristics
High perfo r mance
— Access times as fast as 70 ns
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
Cycling endurance: 1,000,000 cycles per
sector typical
Data retention: 20 years typical
Package Options
48-ball FBGA
48-pin TSOP
44-pin SOP
Soft w a re Feat ures
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend/ Er as e Re su me
— Suspends an eras e ope ration to read data fro m, or
progr a m da ta to, a sector that is not bei ng erased,
then resumes the erase operation
Data# Polling and toggle bits
— Provides a software me thod of detecting program or
erase operation completion
Hardware Features
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
2S29AL016DS29AL016D_00_A2 December 17, 2004
Preliminary
General Description
The S29AL016D i s a 16 Mbit, 3.0 Volt-only Flash memory orga nized as 2,097,152
bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP
packages. The word-wi de data (x16) a ppears on DQ15–D Q0; the byte-wide ( x8)
data appears on DQ7 –DQ0. This device is design ed to be programmed in-system
with th e standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not
required for write or erase operations. The device can also be programmed in
standard EPROM programmers.
The device offers access times of 70 ns and 90 ns allowing high speed micropro-
cessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a single 3.0 volt power supply for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations.
The S29AL016D is entirely command set compatible with the JEDEC single-
power-su pp ly F lash s tanda rd. Commands are written to the command regis-
ter us ing standard mi croprocesso r write timings. R egister content s serve a s input
to an internal stat e-machine that c ontrols the erase and programming circui try.
Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from
other Fla sh or EPROM dev i ces.
Device programming occu rs by ex ecuti ng the progr a m command sequence . This
initiates the Embedded Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass mo de facilita tes fast er progra mming times b y requiri ng only two
write cy cles to program data ins tead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the Em bedded Erase algorithm—an internal algorithm tha t automatically pre-
progra ms t he array (if it is no t alr e ad y programmed) before execut ing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifi es proper cell margi n.
The host system can detect whether a program or erase operation is complete by
observing t he RY /BY# pi n, or by rea ding t he DQ7 (Dat a# P oll in g) and DQ6 (t og -
gle) status bits . After a progr am or er ase c yc le has been completed, the devi ce
is ready to read array data or accept another command.
The sector er as e archi tec tu re allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data p rotect ion measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. The hard ware sector
protection feature disabl es both progr am and er ase operati ons in any c ombina-
tion of the sectors of memory. This can be achieved in-system or via
progra mmi ng equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on
hold for any peri od of time to read data from, or program da ta to, any sect or that
is not selected for eras ure. True background erase can t hus be achiev ed.
December 17, 2004 S29AL016D_00_A2 S29AL016D 3
Preliminary
The hardware RESET# pin terminates any operation in progress and resets the
internal sta te machine to readi ng arra y data. The RESET# pin ma y be tied to the
syste m rese t ci rc uit ry. A system reset woul d th us al so re set the devi ce, enab li ng
the system microprocess or to read the boot-up firmware fro m the Flash memory.
The device offers two power-saving features. When addresses have been stable
for a specified amount of time, the device enters the automatic sleep mode.
The system can also place the device into the standby mode. Power consump-
tion is gre atly reduced in both these modes.
Spansio n’ s Flash tech nology combi nes y ears o f Fl ash me mory m anufa ctur ing ex -
perience to produce the highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot electron
injection.
4S29AL016DS29AL016D_00_A2 December 17, 2004
Preliminary
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide. . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions ...............................................................7
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
S29AL016D Standard Products ........................................................... 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. S29AL 016D Dev ice Bu s Op e rations .........................10
Word/Byte Configuration ...................................................................10
Requirements for Reading Array Data ............................................ 11
Writing Commands/Command Sequences .................................... 11
Program and Erase Operation Status ............................................... 11
Standby Mode ......................................................................................... 12
Automatic Sleep Mode ......................................................................... 12
RESET#: Hardware Reset Pin ............................................................ 12
Output Disable Mode ........................................................................... 13
Ta ble 2. Sect or Add res s Ta bles (To p Bo ot Dev ice) .................13
Ta ble 3. Sect or Ad dres s Ta bles (B ot to m Bo o t Devic e ) ............14
Autoselect Mode ................................................................................... 14
Table 4. S29AL016D Autoselect Codes (High Voltage Method) .15
Sector Protection/Unprotection ....................................................... 15
Temporary Sector Unprotect ........................................................... 15
Figu re 1. Temporary Se cto r Unp ro tec t Op e ration................... 16
Figure 2. In-S ys tem Sec to r Prot ect/U n pro tect Alg o rithms....... 17
Common Flash Memory Interface (CFI). . . . . . . 18
Ta ble 5. CFI Q u ery Ide n tificat ion S tring ...............................18
Table 6. System Interface String .........................................19
Ta ble 7. D evic e Geometry Defin ition ....................................19
Table 8. Prim ar y Ve nd or-Sp ec ific Ext end ed Q uer y .................20
Hardware Data Protection ................................................................20
Low VCC Write Inhibit .......................................................................20
Write Pulse “Glitch” Protection ......................................................20
Logical Inhibit .......................................................................................... 21
Power-Up Write Inhibit ...................................................................... 21
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 22
Reading Array Data ............................................................................. 22
Reset Command ................................................................................... 22
Autoselect Command Sequence ...................................................... 23
Word/Byte Program Command Sequence ................................... 23
Unlock Bypass Command Sequence ............................................... 24
Figu re 3. Prog r am O pe rat ion .............................................. 24
Chip Erase Command Sequence ...................................................... 25
Sector Erase Command Sequence .................................................. 25
Erase Suspend/Erase Resume Commands .................................... 26
Figure 4. Erase Operation .................................................. 27
Command Definitions ......................................................................... 28
Table 9. S29AL 016D Co m mand Definitions ...........................28
Write Operation Status . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling .............................................................................. 29
Fig u re 5. Data# P o llin g A lgo r ithm ....................................... 30
RY/BY#: Ready/Busy# ......................................................................... 30
DQ6: Toggle Bit I ................................................................................... 31
DQ2: Toggle Bit II ................................................................................ 32
Reading Toggle Bits DQ6/DQ2 ........................................................ 32
Figu re 6. To ggle B it Algo rit hm ............................................ 33
DQ5: Exceeded Timing Limits ...........................................................33
DQ3: Sector Erase Timer .................................................................. 34
Table 10. Write Opera tio n St atus ....................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 35
Figu re 7. M aximum Ne ga tive O v e rsh o ot W a v efor m................ 35
Figu re 8. M aximum Posit ive O ve rs ho ot Waveform ................. 35
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .36
Industrial (I) Devices ............................................................................ 36
VCC Supply Voltages ............................................................................ 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Compatible ................................................................................37
Zero Power Flash ................................................................................. 38
Figure 9. I
CC1
Current vs. Time (Showing Active and
Auto matic Sleep Cu rr ents ) ................................................. 38
Figure 10. Typical I
CC1
vs. Freq uen c y .................................. 3 8
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figu re 11. Te st Setup........................................................ 39
Table 1 1. T e st Spec if icatio ns ............................................. 39
Key to Switching Waveforms ...........................................................40
Figure 12. Input Waveforms and Measurement Levels............ 40
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
Read Operations .................................................................................... 41
Figu re 13. R ead O pe rat ion s T im ing s .................................... 41
Hardware Reset (RESET#) ................................................................ 42
Figu re 14. R ES ET # Timings................................................ 4 2
Word/Byte Configuration (BYTE#) ................................................ 43
Figu re 15. BY T E# Timings for Re ad O p erat ion s ..................... 43
Figu re 16. BY T E# Timings for Wr ite O p erations..................... 44
Erase/Program Operations ................................................................ 45
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
Figu re 17. P rog ra m O pe rat ion Tim ing s................................. 4 6
Figu re 18. C hip /Se cto r E ras e Oper atio n T im ing s.................... 47
Figu re 19. D a ta # Po llin g T imings (Du r ing Embed de d
Algo rith m s).............. ................................................... ..... 48
Figure 20. Toggle Bit Timings (During Embedded Algorithms) . 48
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend
Op era tions....................................................................... 49
Temporary Sector Unprotect .......................................................... 49
Figu re 22. Te m p ora ry Se cto r Unp ro tec t/Timing Diagram ........ 49
Figure 23. Sector Protect/Unprotect Timing Diagram.............. 50
Alternate CE# Controlled Erase/Program Operations ............. 51
Figu re 24. Alternate CE# C ontrolled W rite Ope ra tio n Tim in g s.. 52
Erase and Programming Performance . . . . . . . . 53
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . 53
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 54
TS 048—48-Pin Standard TSOP ...................................................... 54
VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm ................................................................................ 56
SO044—44-Pin Small Outline Package (SOP)
28.20 mm x 13.30 mm . . . . . . . . . . . . . . . . . . . . . . .57
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision A (May 4, 2004) ................................................................... 58
Revision A1 (July 28, 2004) ................................................................. 58
Revision A2 (December 17, 2004) ................................................... 58
December 17, 2004 S29AL016D_00_A2 S29AL016D 5
Preliminary
Product Selector Guide
Note: See AC Characteristics for full specifications.
Block Diagram
Family Part Number
S29AL016D
Speed O ption Voltage Range: V
CC
= 2.7–3.6 V
70 90
Max access time, ns (t
ACC
)70 90
Max CE# access time, ns (t
CE
)70 90
Max OE # access time, ns (t
OE
)30 35
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
–
DQ15 ( A-1)
Sector Switc hes
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A19
6S29AL016DS29AL016D_00_A2 December 17, 2004
Preliminary
Connection Diagrams
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
Standard TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
Standard SOP
December 17, 2004 S29AL016D_00_A2 S29AL016D 7
Preliminary
Connection Diagrams
Special Handling Instructions
Special handling is required for Flash Memory products in FBGA packages .
Flash memory devices in FBGA packages may be damaged if exposed to ultra-
sonic c leaning methods. T he pack age and/or data integri ty ma y be compromised
if the pac kage body is exposed to temperatures above 150°C for prol onged peri-
ods of time.
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 VSS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19NCRESET#WE#
DQ11 DQ3DQ10DQ2NCA18NCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSS
CE#A0A1A2A4A3
FBGA
Top View, Balls Facing Down
8S29AL016DS29AL016D_00_A2 December 17, 2004
Preliminary
Pin Configuration
A0–A19 = 20 addresse s
DQ0–DQ14 = 15 data inputs/out puts
DQ15/A-1 = DQ15 (data i nput/output, word mode),
A -1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = W rite enable
RESET# = Hardware reset pin
RY/BY# = Ready/Busy output
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options an d voltage supply tolerances)
VSS =Device ground
NC = Pin not connected internally
Logic Symbol
20 16 or 8
DQ0–DQ15
(A-1)
A0–A19
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
December 17, 2004 S29AL016D_00_A2 S29AL016D 9
Preliminary
Ordering Information
S29AL016D Standard Products
Spansion standard products are available in several packages and operating
rang es. The order number (V al id Combination) is fo rmed by a combination of the
elements below.
Notes:
1. Type 0 is standard. Specify other optio ns as required.
2. TSOP and SOP package markings omit packin g type designator from ordering part number.
3. BGA package marking om it s leading “S29” and packing type designator from ordering part number.
Valid C omb ina t ions
Valid Combinations list configurations planned to be supported in volume for this device. Consult your
loc al sale s office to conf irm avai labili ty of spe cific valid com binat ions an d to ch eck on newly re leas ed
combinations.
S29AL016D 70 T A I 01 0
PACKING TYPE
0=Tray
3 = 13” Tape and Reel
MODEL NUMBER
01 = V
CC
= 2.7 - 3.6V, top boot sector device
02 = V
CC
= 2.7 - 3.6V, bottom boot sector device
TEMPERATURE RANGE
I = Industrial (–40
°
C to +8 5
°
C)
PACKAGE MATERIAL SET
A=Standard
F=Pb-Free
PACKA GE TYP E
T = Thin Small Outl ine Package (TSOP) Standard Pinou t
B = Fine-pitch Ball-Grid Array Package
M = Sm all Outlin e Package (SOP) Standard Pino ut
SPEED OPTION
70 = 70 ns Access Speed
90 = 90 ns Access Speed
DEVICE NUMBER/DESCRIPTION
S29AL016D
16 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
S29AL 016 D Va lid Com binatio ns
Package
Description
Device
Number Speed
Option
Package Type,
Material, and
Temperat ur e Ra nge
Model
Number Packing
Type
S29AL016D 70, 90
TAI, TFI
01, 02 0, 2, 3
(Note 1)
TS048 (Note 2)TSOP
BAI, BFI VBK048 (Note 3)Fine-Pitch BGA
MAI, MFI SO044 (Note 2)SOP
10 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Device Bus Operations
This section describes the requirements and use of the device bus operations,
which are initiated through the internal command register. The command register
itself does not occupy any addressable memory location. The register is com-
posed of latches that store the commands, along with the address and data
information needed to execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the
functi on of the devi ce. Table 1 lis ts the device bus oper ations, the input s and co n-
trol levels they require, and the resulting output. The following subsections
describe each of t hes e operations in further detai l.
Ta b l e 1 . S29AL016D Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Ca r e , A IN = Addre ss In, DIN = Data In, DOUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sect or pro te ct and sect or unpr otect fun cti on s may also be implem ented vi a prog ramming equ ipment. See the
“Sector Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 opera te in
the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If th e BYT E# pi n is set at log ic ‘0’, the de vice i s in byt e conf iguratio n, and only
data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/
O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an in put for the
LSB (A-1) address funct ion.
Operation CE# OE# WE# RESET# Addresses
(Note 1)DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H A
IN
D
IN
D
IN
Standby V
CC
±
0.3 V X X V
CC
±
0.3 V XHigh-Z High-Z High-Z
Output D isable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L D
IN
X X
Sector Unpr otect (Note 2) L H L V
ID
Sector Address,
A6 = H, A 1 = H ,
A0 = L D
IN
X X
Temporary Sector
Unprotect X X X V
ID
A
IN
D
IN
D
IN
High-Z
December 17, 2004 S29AL016D_00_A2 S29AL016D 11
Preliminary
Requirements for Reading Array Data
T o read array data from the outputs, the system must drive the CE# and OE# pins
to VIL. CE# is the power control and selects the device. OE# is the output control
and gates array data to the o utput pins. WE# sho uld remain at VIH. The BYTE#
pin determ ines whether the dev ice o ut puts array data in words or byt es.
The internal state machi ne is set for reading arra y data upon device power-u p,
or after a hardware reset. This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read acc ess until the com-
man d re g i ster co n te n ts ar e a l te r e d.
See Re ad i ng Ar ray D at a for more information. Refer to the AC Re ad Operations
table for timing specific ations and t o Figure 13 for the timing diagra m. ICC1 in the
DC Characteristics table represents the active current specification for reading ar-
ray data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the devi ce and era sing sec tors of memo ry), the sys tem mu st drive WE # and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. See Word/Byte Configuration for more
information.
The device features an Unlock Byp ass mode to facilitate faster programming.
Once the device enters the Unlock Bypass mode, only two write cycles are re-
quired to program a word or by te, instead of f our. W ord/Byte Program Command
Sequence has details on programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Tables 2 and 3 indicate the address space that each sector occupies. A “sector
address” consists of the address bits required to uniquely select a sector. The
Command Definitions section has det ails on erasing a s ector o r the ent ire chi p,
or suspending/resuming the erase oper ation.
After the system wri tes the autoselect c ommand sequence, the device enter s the
autoselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ7–DQ0. Standard read
cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
ICC2 in the DC Characterist ics table represent s the active current s pecification for
the write mode. The AC Characterist ics section contains tim ing specification ta-
bles and timing diagra ms for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the
operation by reading the sta tus bits on DQ7–DQ0. Standard read cycle timings
and I CC read specifications apply. Refer to Write Operation Status for more infor-
mat ion, and to AC Characteristics for timing diagrams.
12 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the st an dby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# pins are
both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than
VIH.) If CE # and RE SET# are held at VIH, bu t not w ithin VCC ± 0.3 V, the devic e
will be in t he standby mode, but the standby current will be greater. The device
requi res sta ndard access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to rea d dat a .
If the device is deselected during erasu re or progr a mmi ng, t he dev ice draws ac-
tive current until the operation is completed.
In the DC Characteristics table, ICC3 and ICC4 represents the standby current
specification.
Automatic Sleep Mode
The automatic sl eep mode minimizes Flash devi ce energy consumptio n. The de-
vice automatically enables this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is inde pendent of the C E#, WE#, and OE# control
signals. Standard address access timings provide new data when addresses are
changed. While in s leep mode, output da ta is latche d and alwa ys av ailable to the
system. ICC4 in the DC Characteristics table represents the automatic s leep mode
current s p ecification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading
arra y data. When the system drives the RESET# pin to VIL for at least a period of
tRP, the device immediately terminates any opera tion in progress, tristates all
data output pins, and ignores all read/write attempts for the duration of the RE-
SET# pulse. The device al so resets the internal sta te machine to readin g array
data. The operation that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held
at V IL but not w ithin VSS±0.3 V, the standby current will be grea ter.
The RESET# pin may be tied to the system reset circuitry. A system reset wo uld
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
ma in s a “0” ( bu sy) unti l t he interna l rese t ope rat io n is c ompl e te, which req uire s
a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/
BY# to determine whether the reset oper ation is complete. If RESET# is asserted
when a program or erase oper ation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of tRE ADY (not during Embedded Algorithms).
The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Ch aracteristics tables for RESET# parameters and to Figure 14
for the timing diagram.
December 17, 2004 S29AL016D_00_A2 S29AL016D 13
Preliminary
Output Disable Mode
When the OE# input is at VIH, output from the device is dis abled. The output pins
are placed in the high impedance st a te.
Ta b l e 2 . Sector Address Tables (Top Boot Device)
Note: A ddr e ss r ang e is A1 9 :A- 1 in by te m o d e and A1 9 :A0 in w o rd mode. See “Wo rd /B y te Co n figuration” s ection .
Sector A19 A18 A17 A16 A15 A14 A13 A12 Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF
SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF
SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF
SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF
SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF
SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF
SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF
SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF
SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF
SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF
SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF
SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF
SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF
SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF
SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF
SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF
SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF
SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF
SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF
SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF
SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF
SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF
SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF
SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF
SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF
SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF
SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF
SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF
SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF
SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF
SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF
SA31111110XX 32/16 1F0000–1F7FFF F8000–FBFFF
SA3211111100 8/4 1F8000–1F9FFF FC000–FCFFF
SA3311111101 8/4 1FA000–1FBFFF FD000–FDFFF
SA341111111X 16/8 1FC000–1FFFFF FE000–FFFFF
14 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Ta b l e 3 . Sector Address Tables (Bottom Boot Device)
Note: A ddr e ss r ang e is A1 9 :A- 1 in by te m o d e and A1 9 :A0 in w o rd mode. See the “W ord/By te C onfig u rat ion” se c tion.
Autoselect Mode
The autoselec t mode pro vides man ufactur er and devic e identi ficat ion, and s ector
protection verification, through identifier codes output on DQ7–DQ0. This mode
is primarily intended for programming equipment to automatically match a device
to be progr ammed with it s correspondi ng programming algorithm. However, the
auto sel ect code s can al so be acce ss ed in-s yst em th roug h the co mman d re giste r.
When using programming equipment, the autoselect mode requires VID (11.5 V
to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Tab le 4. In addition, when verifying sector protection, the sector address must
appear on the appropriate highest order address bits (see Table 2 and Table 3).
Table 4 shows the remain ing address bits that are don’t care. When all ne cessary
bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ7-DQ0.
Sector A19 A18 A17 A16 A15 A14 A13 A12 Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8) Word Mode (x16)
SA0 0000000X 16/8 000000–003FFF 00000–01FFF
SA1 00000010 8/4 004000–005FFF 02000–02FFF
SA2 00000011 8/4 006000–007FFF 03000–03FFF
SA3 000001XX 32/16 008000–00FFFF 04000–07FFF
SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF
SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF
SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF
SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF
SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF
SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF
SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF
SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF
SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF
SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF
SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF
SA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF
SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF
SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF
SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF
SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF
SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF
SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF
SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF
SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF
SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF
SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF
SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF
SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF
SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF
SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF
SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF
SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF
SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF
SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF
SA34 1 1 1 1 1 X X X 64/32 1F0000–1FFFFF F8000–FFFFF
December 17, 2004 S29AL016D_00_A2 S29AL016D 15
Preliminary
To access the autoselect codes in-system, the host system can issue the autose-
lect command via the command register, as shown in Table 9. This method does
not require VID. See Command Definitions for details on using the autoselect
mode.
Ta b l e 4 . S29AL016D Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase opera-
tions in any sector. The hardware sector unprotection feature re-enables both
progra m and erase oper at ions in previous ly protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of
programming and protecting sectors at its factory prior to shipping the device
through Spansion’s ExpressFlash™ Service. Contact a Spansion representative
for d etails.
It is po ssibl e to determine whether a sec tor i s pro tected o r u nprotected. See Au-
toselect Mode for details.
Sector protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be imple-
mented either in-system or via programming equipment. Figure 2 shows the
alg o rithms and Figure 23 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect write cycle.
The alternate meth od int ended on ly for progr a mming e quipment require s VID on
address pin A9 and OE#. This method is compatible with programmer routines
written for earlier 3.0 volt-only Spansion flash devices. Details on this method are
provided in a supplement, publication number 21468. Contact a Spansion repre-
sentative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to
change data in-system. The Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be pro-
grammed or er ased by se lecting th e sector addresses. Once V ID is remov ed from
the RESET# pin , all the p revi ously prote cted se ctors are pr otecte d again. sh ows
the algorithm, and Figure 22 shows the timing diagrams, for this feature.
Description Mode CE# OE# WE# A19
to
A12
A11
to
A10 A9 A8
to
A7 A6 A5
to
A4
A3
to
A2 A1 A0 DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: Spansion L L H X X VID XLXLLL X 01h
Device ID:
S29AL016D
(Top Boot Block)
Word L L H XXV
ID XLXLLH22h C4h
Byte L L H X C4h
Device ID:
S29AL016D
(Bottom Boot Block)
Word L L H XXV
ID XLXLLH22h 49h
Byte L L H X 49h
Sector Prot ection Verification L L H SA X VID XLXLHL X 01h (protected)
X 00h (unprotected)
16 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Figure 1. Temporary Sector Unprotect Operation
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
December 17, 2004 S29AL016D_00_A2 S29AL016D 17
Preliminary
Figure 2. In-System Sector Protect/Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
First Write
Cycle = 60h?
Data = 01h?
Remove VID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
Data = 00h?
Last sector
verified?
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm
Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
18 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Common Flash Memory Interface (CFI)
The Commo n Fl ash In te rf ac e (CF I) spec if i cati on outl in es devi ce an d host sy ste m
software interrogation handshake, which allows specific vendor-specified soft-
ware algorithms to be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and forward- and back-
ward-compatible for the specified flash device families. Flash vendors can
standardize thei r existing in ter faces for long-t erm compatibility.
This device enters the CFI Query mode when the system writes the CFI Query
command, 98h, to address 55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information
at the addres ses gi ven in Tables 5–8. In word mode, the upper addr ess bits ( A7–
MSB) must be all zeros. To terminate reading CFI data, the system must write
the reset command.
The system can also write the CFI query command when the devi ce is in the au -
toselect mode. The device enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 5–8. The sy stem m ust write the reset
command to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication
100, available via the World Wide Web at http://www.amd.com/products/nvd/
overview/cfi.html. Alternatively, contact a Spansion representative for copies of
these documents.
Ta b l e 5 . CFI Query Identification String
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Addres s for Prim ary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none e xists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OE M E xten ded Table (00h = n on e exists)
December 17, 2004 S29AL016D_00_A2 S29AL016D 19
Preliminary
Ta b l e 6 . System Interface String
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
1Bh 36h 0027h V
CC
Min. (w rite/er ase)
D7– D4: volt, D3–D0: 100 m illivolt
1Ch 38h 0036h V
CC
Max. (write/erase )
D7– D4: volt, D3–D0: 100 m illivolt
1Dh 3Ah 0000h V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh 3Ch 0000h V
PP
Max. voltage ( 00h = no V
PP
pin present)
1Fh 3Eh 0004h Typical timeout per single byte/word write 2
N
µs
20h 40h 0000h Typical tim eou t for Min. size buffer write 2
N
µs (00h = n ot su pported)
21h 42h 000Ah Typical timeout per individual block er a s e 2
N
ms
22h 44h 0000h Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h 46h 0005h Max. time out for byt e/word write 2
N
time s t ypical
24h 48h 0000h Max. timeout for buffer write 2
N
times typical
25h 4Ah 0004h Max. time out per individua l block er a s e 2
N
time s ty pical
26h 4Ch 0000h Max. timeout for full ch ip erase 2
N
times typical (00h = not supported)
Ta b l e 7 . Device Geometry Definition
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
27h 4Eh 0015h Device Size = 2
N
byte
28h
29h 50h
52h 0002h
0000h Flash Device Interfac e description (refer to CFI publication 100)
2Ah
2Bh 54h
56h 0000h
0000h Max. numbe r of byte in multi-byte write = 2
N
(00h = not supported)
2Ch 58h 0004h Number of E rase Block Regions within dev ice
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refe r to the C FI specifica tion or CFI pub lication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
Erase Block Region 4 Information
20 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to Table 9 for command
definitions). In addition, the following hardware data protection measures pre-
vent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and power-down transitions,
or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This pro-
tects data during VCC power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is
greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Ta b l e 8 . Primary Vendor-Specific Extended Query
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major v ersion number, ASCII
44h 88h 0030h Minor version number, ASCII
45h 8Ah 0000h Address Se nsitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Su pported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = No t Su pported, X = Number of sector s in per grou p
48h 90h 0001h Sector Temporary U n protect
00 = N o t Supporte d, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 94h 0000h Simu lta ne ous Oper ation
00 = N o t Supporte d, 01 = Supported
4Bh 96h 0000h Burst Mode Type
00 = N o t Supporte d, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
December 17, 2004 S29AL016D_00_A2 S29AL016D 21
Preliminary
Logi ca l I nhibit
Wr ite cycles are inhibi ted by hold ing any one of OE# = VIL, CE# = VIH or WE# =
VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not acce pt
commands on the rising edge of WE#. The internal state machine is automatically
reset to rea ding array data on p ower-up.
22 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Table 9 defines the valid register command
sequences. Writing incorrect address and data values or wr itin g t hem i n t he
improper sequence resets the devi ce to read i n g ar ray data.
All address es ar e lat ched on the f alli ng edge of WE# or CE#, which ev er happ ens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the AC Characteristics section .
Reading Array Data
The device is automatically set to reading array data after device power-up. No
comma nds are req uired to re trieve data. The device is also read y to rea d array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend m ode. The sy stem can read arr ay data using th e standard re ad timings ,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See Erase Suspend/Erase Resume Commands for more information on this mode.
The system must issue the reset command to re-enable the device for reading
arra y data if DQ5 goes high, or while in the autos elect mode. See the Reset Com-
mand section, next.
See also Requirements for Reading Array Data in the Devi ce Bus Ope ra tions sec-
tion for more information. The Read Operations table provides the read
parameters, and Figur e 1 3 shows t he timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data.
Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase
command sequence before erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in a program
command sequence before programming begins. This resets the device to read-
ing array data (also applies to programming in Erase Suspend mode). Once
progra mmi ng begins, however, the device ignores reset commands until the op-
eration is complete.
The reset command may be written between the sequence cycles in an autoselect
command sequence. Once in the autoselect mode, the reset command must be
written to ret urn to readin g array data (also applies to au toselect d uring Erase
Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command
returns the dev ice to reading array data (also applies during Er a se Suspend).
December 17, 2004 S29AL016D_00_A2 S29AL016D 23
Preliminary
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manu-
facturer and devices codes, and determine whether or not a sector is protected.
Table 9 shows the address and data requirements. This method is an alternative
to that shown in Table 4, which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, fol-
lowed by the autoselect command. The device then enters the autoselect mode,
and t he sy s te m ma y rea d at any addres s an y nu mbe r of ti me s , w it hou t ini t ia t ing
another com mand se q u en c e .
A read c ycle at address XX00h retrie ves the manu factur er co de. A rea d cycle at
address XX01h returns the device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in byte mode) re turns 01h if that
sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid
sector addresses .
The system must write the reset command to exit the autoselect mode and return
to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on th e state of
the BYTE# pin. Programming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The system is not requ ired to
provid e further controls or timings. The device automatically generates the pro-
gram pulses and verifies the programmed cell margin. Table 9 shows the address
and data requirements fo r th e byte progra m command sequence.
When the E mb edd ed Pr ogram a lgorith m is compl ete, th e d evice then re turn s to
reading array data and addresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See
Wr ite Operation Status fo r i nformation on these stat us b its.
Any commands written to the device during the Embedded Program Algorithm
are ignored. Note th a t a hardware reset immediately terminates the program-
ming operation. The Byte Program command sequence should be reinitiated once
the device has reset to reading array data, to ensu re da ta integrity.
Programming is allowed in any sequence and across sector boundaries. A bit
cannot be progr amm ed from a “0” back to a “1”. Attempting to do s o may
halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to
indicate the oper at ion was s uccessf ul. Ho wever, a succeedin g read wil l show t hat
the data is still “0”. Only erase operations can con vert a “0” to a “1”.
24 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the
device faster than using the standard program command sequence. The unlock
bypass command sequence is initiated by first writing two unlock cycles. This is
followed by a t hird write cycle containing t he u nlock bypass command, 20h. The
device then enters the u nlock bypas s mode. A t wo-cycle unlock bypa ss progr am
command sequence is all that is required to progra m in this mode. The first cycle
in this sequence contains the unlock bypass program command, A0h; the second
cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispen ses with the initial two unlock cy cles required
in the standard program command sequence, resulting in faster total program-
min g time . Table 9 shows the r equirements for the command sequence.
During the unl ock bypass mode, only t he Unlock Bypass Prog ram and Unlock By -
pass Reset commands are valid. To exit the unlock bypass mode, the system
must issu e the two-c ycle unl ock bypas s reset comma nd sequence. The first cycle
must contain the data 90h; the second cycle the data 00h. Addresses are don’t
care for both cyc les. The device th en returns to reading array data.
Figure 3 illustra tes the algorithm for the program operation. See the Erase/Pro-
gram Operations table in AC Char a ct eristics for parameters, and to Figure 17 for
timing diagrams.
NOTE: S ee Tabl e 9 for program command sequence.
Figure 3. Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
December 17, 2004 S29AL016D_00_A2 S29AL016D 25
Preliminary
Chip Erase Command Sequence
Chip erase is a si x bus cyc le operation. The chip er ase command sequen ce is ini -
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprogr ams and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operat ions. Table 9 shows the address and data requirements
for the chip erase command sequence.
Any commands wr itten to the ch ip during the Embedded E rase algorithm are ig-
nored. Note that a hardware r eset during the chip er ase oper ation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device h as returned to reading arr ay data , to ensure data integrit y.
The system can determin e the statu s of the erase operation by us ing DQ7, DQ6,
DQ2, or RY /BY#. See Wri te Operatio n Status for information on these status bits.
When the Embedded Erase algorithm is complete, the device returns to reading
array data and addres ses are no longer l atched.
Figur e 4 i llustra tes the algorithm for the erase oper ation. See the Erase/Program
Operations tables in AC Ch ar a ct er i st ic s for pa r amete rs, a nd to Figure 18 for tim-
ing diagrams.
Sector Erase Command Sequence
Sector er ase is a six bus cycle operation. The sector er ase command sequence is
initiated by writing two unl ock cycles, followed by a set- up comman d. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Table 9 shows the address and data re-
quirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any con tr ols or timings during these operations.
After the c ommand sequenc e is wri tten, a sector er ase t ime-out of 50 µs begi ns.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between th ese addition al cy cles mus t be l ess than 50 µs, ot herwise the l ast
address and command might not be accepted, and era su re may begin. It is rec -
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. T he syste m must rewr ite the
command sequence and an y additional sector addres ses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed
out. (See DQ3: Sect or Er ase Tim er. ) The ti me-out begi ns from the ris ing edge of
the final WE# pulse in the command sequenc e.
26 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Once the sector er ase o per ation has begun , only the Erase Suspend command is
valid. All other c omma nds ar e ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase
command s equence should be re initiated once the device has returned t o reading
array data, to ensu re da ta integri ty.
When the Embedded Erase algorithm is complete, the device returns to reading
array da ta and addresses are no longer latched . The sy stem c an de termine the
status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to Write
Oper ation S ta tus for information on these status bits.)
Figur e 4 i llus tr ates t he algor ithm for the er ase oper atio n. Refer to the Erase/Pro-
gram Operations tables in the AC Characteristics section for param eters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to inter rupt a sector erase oper -
ation and then read data from, or program data to, any sector not selected for
erasure. This command is v al id only during t he sect or erase operation, including
the 50 µs time-ou t period during t he sector erase c ommand sequence. T he Erase
Suspend command is ignored if written during the chip erase opera tion or Em-
bedded Program algorithm. Writing the Erase Suspend command during the
Sector Er ase time-out immediate ly terminates the ti me-out period and suspe nds
the erase operation. Addresses are “don’t-cares” when writing the Er ase Suspend
command.
When the Erase Suspend command is written during a sector er ase operation, the
device requires a maximum of 20 µs to suspend the erase opera tion. However,
when the Erase Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the system can read array data
from or program data to any sector not selected for erasure. (The device “erase
suspends” all sectors se lected for erasure.) Normal read an d write t imings and
command definit ions apply. Reading at an y address wit hin er ase-suspended s ec -
tors pr oduces statu s data on DQ7–DQ0. The system can use DQ7, o r DQ6 and
DQ2 together, to determine if a sector is actively eras ing or is erase-suspended.
See Write Operation Status for information on these status bits.
After an erase-suspended program operation is complete, the system can once
again read ar ray data wi th in non- su sp e n d e d se ct ors. Th e syste m ca n d e te r m i n e
the status of the program operat ion using the DQ7 or DQ6 status bit s, ju st as in
the standard program operation. See Write Operation Status for more
information.
The system may also write the autoselect command sequence when the device
is in the Erase Suspend mode. The device allows reading autoselect codes even
at addresses within erasing sectors, since the codes are not stored in the memory
arr ay. When the device exits t he autoselect mode, the device revert s to the Era se
Suspend mode, and is ready for another valid operation. See Autoselect Com-
mand Sequence for more inform a ti on.
December 17, 2004 S29AL016D_00_A2 S29AL016D 27
Preliminary
The system must write the Erase Resume command (address bits are “don’t
care”) to exit the erase suspend mode and continue the sector erase operation.
Further writes of the Resume command are ignored. Another Erase Suspend
command can be writ ten after the devi ce has resumed er a sing.
Notes:
1. See Table 9 for erase command sequence.
2. See DQ3: Sector Erase Timer for more information.
Figure 4. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
28 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Command Definitions
Ta b l e 9 . S29AL016D Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.
Note:
1. See Table 1 for descripti on of bu s operations.
2. All valu es are in he xadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect comm and se q uence, all b us cycl es are w r ite cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device
is prov iding status data).
8. The f o urth cycle of th e autoselec t command sequence is a r ea d cycle.
9. The data is 00h fo r an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Byp ass co mmand is r equired prior t o t he Unlock Bypass Program com man d .
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also
acceptable.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase
Susp end c o mmand is valid o nly during a sector erase o p eration.
14. The Erase Resume command is valid only during the Erase Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read ( Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autoselect (Note 8)
Manufact urer ID
Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID,
Top Boot Block Word 4555 AA 2AA 55 555 90 X01 22C4
Byte AAA 555 AAA X02 C4
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 2249
Byte AAA 555 AAA X02 49
Sector Protect Verify
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
CFI Query (Note 10)Word 155 98
Byte AA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 11) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 12) 2 XXX 90 XXX F0
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 13) 1 XXX B0
Erase Resume (Note 14) 1 XXX 30
December 17, 2004 S29AL016D_00_A2 S29AL016D 29
Preliminary
Write Operation Status
The device provides several bits to determine the status of a write operation:
DQ2, DQ3, DQ5, DQ6 , DQ7, and RY /BY#. Table 10 and the following subsectio ns
describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method
for determinin g whether a program or eras e operation is c omplete or in pr ogress.
These three bits are disc ussed f irst.
DQ7: Data# Polling
The Data# Po lling bit, DQ7, indicates to the host system whether an Embedded
Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Pol li ng is va li d after the ri si ng edge of the fina l WE# pulse in the program
or erase command sequence.
During the Embedded Program a lgorithm, the device outputs on DQ7 the com-
plement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Era se Suspend. When the Embedded Program algorithm is
comple t e, th e de vi ce o u tp u ts t he datum p r ogrammed to DQ 7 . The sy ste m must
provide the prog ram address to read valid status infor mation on DQ7. If a pro-
gram address falls within a protected sector, Data# Polling on D Q7 is active for
approximately 1 µs, then the devi ce returns to read ing a rray data.
During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.
When the Embedded Erase algorithm is complete, or if the device enters the
Erase Sus pend mode, Data # P olli ng pr oduces a “1” on D Q7. This i s an alogous t o
the complement/true datum output described for the Embedded Program algo-
rithm: the erase function changes all the bits in a sector to “1”; prior to this, the
device outputs the “complement,” or “0.” The system must provide an address
within any of the sectors selected for erasure to read valid status information on
DQ7.
After an erase command sequence is written, if all sectors selected for erasing
are protect ed, Data# P oll ing on DQ7 is active for appro ximatel y 100 µs, then t he
device returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the se-
lect ed sectors that ar e prot ected.
When the system detects DQ7 has changed from the complement to true data,
it can read valid data at DQ7–DQ0 on the following read c ycles. T his is b ecau se
DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is
asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms),
in the AC Ch aracteristics section il lustrates t his.
Table 10 shows the outputs f or Data # P oll ing on DQ7 . Figure 6 shows the Da ta #
Polling algorithm.
30 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Figure 5. Data# Polling Algorithm
DQ7 = Data? Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operatio n, a valid address i s an address within
any se ctor se lect ed for e ra sure. Dur ing c hip er ase, a
valid address is any non-prot ected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
December 17, 2004 S29AL016D_00_A2 S29AL016D 31
Preliminary
RY/BY#: Ready/Busy#
The RY/BY# is a dedic ated , open- drain output pin t hat indic ates whether an Em-
bedded Algori thm is in progre ss or co mplete. The RY /BY# status i s valid a fter the
rising edge of th e final WE# pulse in the command sequence. Si nce RY/BY# is an
open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to V CC.
If the output is low (Busy), the device is actively erasing or programming. (This
includes progr amming in the Erase Suspend mode.) If the output is high (R eady),
the device is ready to read array data (including during the Erase Suspend
mode), or is in the st andby mode.
Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY#
for read, reset, program, and erase operations, respect ively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates wheth er an Embedded Program or Erase algorithm
is in pro gress or complet e, or whether the device has entered the Er ase Suspend
mode. Toggle Bit I ma y be read at any addr ess, an d is v ali d after the ri si ng edge
of the final WE# pulse in the command sequence (prior to the progr am or er ase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm oper ation, successive read c y-
cles to any address cause DQ6 to toggle. (The system may use either OE# or CE#
to control the read cy cles.) When the oper ation is complete, DQ6 stops toggli ng.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together t o determin e whether a sect or is ac -
tively er asing or is e rase-suspended. When the device i s activel y eras ing (that is,
the Embedded Erase algorit hm is in progress) , DQ6 toggles. When the dev ice en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or er ase-suspended. Alter-
natively, the system can use DQ7 (see the subsectio n on DQ7: Data# Polling).
If a program address falls within a protected sector, DQ6 toggles for approxi-
mately 1 µs after the program command sequence is written, then returns to
reading array da ta .
DQ6 also toggles during the erase-suspend-program mode, and stops toggling
once the Embedded Program algorithm is co mpl ete.
Table 10 shows the outp uts for Toggle Bit I on DQ6. Figure 6 shows the toggle bit
algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 ex-
plains the algorithm. Figure 20 in the AC Characteristics section sh ows the toggle
bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in
graphical fo rm. See also the subsec ti on on DQ2: Toggle Bit I I.
32 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular
sector i s actively er a sing (that is, the Em bedded Er ase a lgorithm is in pro gress),
or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE# pulse in the command sequenc e .
DQ2 toggles when t he system reads at addres ses within those sectors that have
been selected f or erasure. (The system may u se either OE# or CE# to control the
read cy cles.) Bu t DQ2 cannot di stingui sh whether th e sector is actively erasing or
is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for er asure. T hus, both statu s bit s ar e requi red fo r s ector and mode i nformation .
Refe r t o Table 10 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart form, and the section Reading
Togg le Bit s DQ6/DQ 2 explains the algorithm. See also the DQ6: Togg le Bit I sub-
section. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the
differences between DQ2 and DQ 6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refe r to Figur e 6 for the following discussion. Whenever the system initially be-
gins readi ng toggle bit status, it must read DQ 7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the system would note and
store the value of the toggle bit after the first read. After the second read, the
system would compare the new v alue of the toggle bi t with the first. If the t oggle
bit is not toggling, t he device has c ompleted the pr ogram or er ase oper ation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle
bit is s til l toggl in g, the s yst em also sh oul d note whether th e v alue of DQ5 is h igh
(see the section on DQ5). If it is, the system should then determine again
whether t he toggle bit is toggling, si nce the toggle bit may hav e stopped t oggling
just as DQ5 went high. I f the toggle bit is no longer toggling, t he device has su c-
cessfully completed the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initi ally determin es that the toggle bit
is toggli ng an d DQ5 h as not gone h igh . The s ystem ma y co ntinu e to monit or the
toggle bit and DQ5 through success ive read cycles, determi ning the status as de-
scribed in the previous paragraph. Alternatively, it may choose to perform other
syste m tasks. In thi s case, the sy stem mu st start at th e beginni ng of the alg o-
rithm when it returns to determine the status of th e operation (top of Figure 6).
December 17, 2004 S29AL016D_00_A2 S29AL016D 33
Preliminary
Figure 6. Toggle Bit Algorithm
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7–DQ0
Toggle Bit
= Toggle?
Read DQ7–DQ0
Twice
Read DQ7–DQ0
Notes:
1. Read toggle bit twice to determine whether or not it
is toggling. See text.
2. Recheck toggle bit because it may stop toggling as
DQ5 changes to “1”. See text.
(Note 1)
(Notes
1,2)
34 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
DQ5: Exceeded Timing Limits
DQ5 indicates whether the prog ram or erase time has exceeded a specified inter-
nal pulse coun t limit. Under thes e conditions DQ 5 produces a “1.” This is a fail ure
condition that indicates the program or erase cycle was not successfully
completed.
The DQ5 failure condition may a ppear if the system tries to program a “1” to a
location that is previously programmed to “0.” Only an erase operation can
change a “0” back to a “1 .” Und er this co nd itio n, th e d evi ce h alt s th e opera-
tion, and wh en the operation has exceeded the timing limits, DQ5 pro duces a “1.”
Under both these conditio ns, the system must i ssue the reset command to return
the device to rea d ing array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to de-
termine whether or not an erase operation has begun. (The sector erase timer
does not appl y to th e chip er as e command. ) If addi tional sector s are sel ecte d for
erasure, the entire time-out also applies after each additional sector erase com-
mand . Wh en th e ti me- out is c ompl ete , DQ3 swi tch es f rom “0” t o “1 .” The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands will always be less than 50 µs. See also the Sector Erase
Command Sequence section.
After the secto r erase co mmand sequence is writ ten, the system shou ld read the
status on DQ7 (Data# P olli ng) or DQ6 (Toggle Bit I ) to ensure th e device ha s ac -
cepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally
controlled erase cycle has begun; all further commands (other than Erase Sus-
pend) are ignored unti l the erase operation is co mplete. I f DQ3 is “0”, the device
wil l ac cep t ad d it io na l se c to r er a s e co mmands. To ensure the command has been
acc epted , the system softwa re sh ould check the statu s of D Q3 p rior t o and fol-
lowing each subsequent sector erase command. If DQ3 is high on the second
status check, the last command might not have been accepted. Table 10 shows
the out p uts for DQ3.
Ta b l e 1 0. Write Operation Status
Notes:
1. DQ5 swi tc h es to ‘1’ wh en an Embe dd ed Pro g ra m or E mbed d ed E r as e op eration has exceede d th e maxi mu m tim in g
limits. See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
Operation DQ7
(Note 2)DQ6 DQ5
(Note 1)DQ3 DQ2
(Note 2)RY/BY#
Standard
Mode
Embedded Program Algorithm
DQ7# Toggle 0N/A No toggle 0
Emb edded Er ase Algorit hm 0Toggle 0 1 Toggle 0
Erase
Suspend
Mode
R eading with in Erase
Suspended Sector 1No toggle 0N/A Toggle 1
R eading with in Non-Era s e
Suspended Sector Data Data Data Data Data 1
Erase-Suspend-Program DQ7# Toggle 0N/A N/A 0
December 17, 2004 S29AL016D_00_A2 S29AL016D 35
Preliminary
Absolute Maximum Ratings
Storage Temp erature
Pla s tic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .– 6 5°C to +150°C
Ambient Temperature
with Powe r Ap plied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 5°C to +125°C
Vo ltage wit h Respect to Ground
VCC (N o t e 1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .– 0.5 V to +4.0 V
A9, OE#, and RES ET # (N o te 2) . . . . . . . . . . . . . . . .– 0 .5 V to +12 .5 V
All ot h er pin s (N o te 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
Outp u t Sh o rt Circ u it Curre n t (N o te 3) . . . . . . . . . . . . . . . . . . . . . . . . 2 0 0 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. Durin g
voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE #, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V fo r period s of up to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Du ration of the short circuit should not be greater
than one sec ond.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the op-
erational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Figure 7. Maximum Negative Overshoot Waveform
Figure 8. Maximum Positive Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
20 ns
–2.0 V
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
36 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85 °C
VCC Supply Voltag es
VCC for standard volt age range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is
guaranteed.
December 17, 2004 S29AL016D_00_A2 S29AL016D 37
Preliminary
DC Characteristics
CMOS Compatible
Notes:
1. The ICC curr ent listed is typically less than 2 mA/MHz, with O E# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep
mode current is 200 nA.
6. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
I
LI
Input Loa d Current V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
±
1.0 µA
I
LIT
A9 Input Load Current V
CC
= V
CC max
; A9 = 12.5 V 35 µA
I
LO
Output Leakage Current V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC max
±
1.0 µA
I
CC1
V
CC
Active Read Current
(Notes
1
,
2
)
CE# = V
IL,
OE#
=
V
IH,
Byte Mode
10 MHz 15 30
mA
5 MHz 916
1 MHz 2 4
CE# = V
IL,
OE#
=
V
IH,
Word Mode
10 MHz 18 35
5 MHz 916
1 MHz 2 4
I
CC2
V
CC
Activ e Write Current
(Notes
2
,
3
,
5
)CE# = V
IL,
OE# = V
IH
20 35 mA
I
CC3
V
CC
Standby C urren t ( N otes
2
,
4
)CE#, RESET# = V
CC
±
0.3 V 0.2 5µA
I
CC4
V
CC
Standby Cur rent Durin g R eset
(Notes
2
,
4
)RESET # = V
SS
±
0.3 V 0.2 5µA
I
CC5
Auto m a tic Sleep M ode
(Notes
2
,
4
,
6
)V
IH
= V
CC
±
0.3 V;
V
IL
= V
SS
±
0.3 V 0.2 5µA
V
IL
Input Low V oltage –0.5 0.8 V
V
IH
Input H igh Voltage 0.7 x V
CC
V
CC
+ 0.3 V
V
ID
Voltage fo r Autoselect and
Temporary Sector U n prot ect V
CC
= 3.3 V 11.5 12.5 V
V
OL
Outp ut Low Voltage I
OL
= 4.0 mA, V
CC
= V
CC mi n
0.45 V
V
OH1
Output Hi gh Voltag e I
OH
= -2.0 mA, V
CC
= V
CC min
2.4 V
V
OH2
I
OH
= -100 µA, V
CC
= V
CC mi n
V
CC
–0.4 V
V
LKO
Low V
CC
Lock -Out Voltage (Note 4) 2.3 2.5 V
38 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
DC Characteristics (continued)
Zero Power Flash
Note: Addresses are sw itchin g at 1 MHz
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
Note: T = 25 °C
Figure 10. Ty p i c a l I CC1 vs. Frequency
25
20
15
10
5
0
0 500 1000 1500 2000 2500 3000 3500 4000
Supply Current in mA
Time in ns
10
8
2
0
12345
Frequency in MHz
Supply Current in mA
2.7 V
3.6 V
4
6
December 17, 2004 S29AL016D_00_A2 S29AL016D 39
Preliminary
Test Conditions
Figure 11. Te s t S e t u p
Table 11. Test Specifications
Test Condition 70 90 Unit
Output L oa d 1 TTL gate
Output L oa d Ca pa c ita nce, C
L
(including jig capa cita n ce) 30 100 pF
Input Ris e a nd Fall Time s 5ns
Input Pulse Levels 0.0 or V
CC
V
Input tim ing measurement
reference levels 0.5 V
CC
V
Output timing meas urement
reference levels 0.5 V
CC
V
2.7 k
Ω
C
L
6.2 k
Ω
3.3 V
Device
Under
Test
Note: Diodes are IN3064 or equivalent
40 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Key to Switching Waveforms
Figure 12. Input Waveforms and Measurement Levels
WAVEFORM INPUTS OUTPUTS
Steady
Chan ging from H to L
Changing from L to H
Don ’t Care, Any Change Permitted Changing, State Unkn own
Does Not Apply Center Line is High Impedance State (High Z)
VCC
0.0 V
0.5 VCC OutputMeasurement LevelInput 0.5 VCC
December 17, 2004 S29AL016D_00_A2 S29AL016D 41
Preliminary
AC Characteristics
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
Parameter
Description
Speed Options
JEDEC Std Test Setup 70 90 Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)Min 70 90 ns
t
AVQV
t
ACC
Address to Output Delay CE# = V
IL
OE# = V
IL
Max 70 90 ns
t
ELQV
t
CE
Chip Enable to Output Delay OE# = V
IL
Max 70 90 ns
t
GLQV
t
OE
Outp ut Enable to Output Delay Max 30 35 ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)Max 25 30 ns
t
GHQZ
t
DF
Outp u t Enable to Outpu t H igh Z (Note 1)Max 25 30 ns
t
OEH
Output Enable
Hold Time (Note 1)
Read Min 0ns
Toggle and
Da ta# Polling Min 10 ns
t
AXQX
t
OH
Output H old Time From Addresses, CE# or
OE#, W hiche ver Occurs Fir st (Note 1)Min 0ns
tCE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
tRC
tACC
tOEH
tOE
0 V
RY/BY#
RESET#
tDF
tOH
Figure 13. Read Operations Timings
42 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description
All Speed OptionsJEDEC Std Test Setup Unit
t
READY
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note) Max 20 µs
t
READY
RESE T# Pin Low (NOT During Embedded
Algor ithms) to R e ad or Write (See N o te) Max 500 ns
t
RP
RESET# Pulse Width Min 500 ns
t
RH
RESET# H igh T im e Be fore Read (See Note) Min 50 ns
t
RPD
RESE T# L ow to Standby Mode Min 20 µs
t
RB
RY/BY# Recovery Time Min 0ns
RESET#
RY/BY#
RY/BY#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
tReady
CE#, OE#
tRH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
tRP
tRB
Figure 14. RESET# Timings
December 17, 2004 S29AL016D_00_A2 S29AL016D 43
Preliminary
AC Characteristics
Word/Byte Configuration (BYTE#)
Parameter Speed Options
JEDEC Std
Description
70 90 Unit
t
ELFL/
t
ELFH
CE# to BYTE# Switching Low or High Max 5ns
t
FLQZ
BYT E# Sw itching L o w to Output HI G H Z Max 25 30 ns
t
FHQV
BYTE# Switching High to Ou tput Active Min 70 90 ns
DQ15
Output
Data Output
(DQ0–DQ7)
CE#
OE#
BYTE#
t
ELFL
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
t
FLQZ
BYTE#
Sw itchin g
from word
to byte
mode
DQ15
Output
Data Output
(DQ0–DQ7)
BYTE#
t
ELFH
DQ0–DQ14 Data Output
(DQ0–DQ14)
DQ15/A-1 Address
Input
t
FHQV
BYTE#
Sw itchin g
from byte
to word
mode
Figure 15. BYTE# Timings for Read Operations
44 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
Note: Refer to the Erase/Pr ogram Ope rations table for tAS and tAH specifications.
Figure 16. BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge o f the last WE# signal
t
HOLD
(t
AH
)
t
SET
(t
AS
)
December 17, 2004 S29AL016D_00_A2 S29AL016D 45
Preliminary
AC Characteristics
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Parameter Speed Options
JEDEC Std
Description
70 90 Unit
t
AVAV
t
WC
Write Cyc le Time (Note 1)Min 70 90 ns
t
AVWL
t
AS
Address Setup Time Min 0ns
t
WLAX
t
AH
Address Hold Time Min 45 45 ns
t
DVWH
t
DS
Data Set up Time Min 35 45 ns
t
WHDX
t
DH
Data H o ld Time Min 0ns
t
OES
Output E nable Setup T im e Min 0ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# H igh to WE# Low) Min 0ns
t
ELWL
t
CS
CE# Setup Time Min 0ns
t
WHEH
t
CH
CE# H old Time Min 0ns
t
WLWH
t
WP
Write Pulse Width Min 35 35 ns
t
WHWL
t
WPH
Write Pulse W idt h High Min 30 ns
t
WHWH1
t
WHWH1
Progr amming Operation (Note 2)Byte Typ 5µs
Word Typ 7
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)Typ 0.7 sec
t
VCS
V
CC
Setup Tim e (Note 1)Min 50 µs
t
RB
Re covery T im e from RY/BY# Min 0ns
t
BUSY
Program /Erase Valid to R Y /B Y# Delay Max 90 ns
46 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
Notes:
1. PA = program address, PD = program data, DOUT is the tru e data at th e program address.
2. Illustration shows device in word mode.
Figure 17. Program Operation Timings
OE#
WE#
CE#
VCC
Data
Addresses
t
DS
tAH
tDH
tWP
PD
tWHWH1
tWC tAS
tWPH
tVCS
555h PA PA
Read Status Data (last two cycles)
A0h
tCS
Status DOUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
tBUSY
tCH
PA
December 17, 2004 S29AL016D_00_A2 S29AL016D 47
Preliminary
AC Characteristics
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18. Chip/Sector Erase Operation Timings
OE#
CE#
Addresses
VCC
WE#
Data
2AAh SA
tAH
tWP
tWC tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress Complete
tWHWH2
VA
VA
Erase Command Sequence (last two cycles) Read Status Data
RY/BY#
tRB
tBUSY
48 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
WE#
CE#
OE#
High Z
tOE
High Z
DQ7
DQ0–DQ6
RY/BY#
tBUSY
Complement True
Addresses VA
tOEH
tCE
tCH
tOH
tDF
VA VA
Status Data
Complement
Status Data True
Valid Data
Valid Data
tACC
tRC
Note: V A = Valid addres s. Illustration shows first status cycle after comma nd sequence, last status read cycle, and
array data read cycle.
Figure 19. Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA VA
t
ACC
t
RC
Valid DataValid StatusValid Status
(first read) (second read) (stops toggling)
Valid Status
VA
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
December 17, 2004 S29AL016D_00_A2 S29AL016D 49
Preliminary
AC Characteristics
Temporary Sector Unprotect
Note:
Not 100% tested.
Parameter
All Speed OptionsJEDEC Std
Description
Unit
t
VIDR
V
ID
Rise and Fall Tim e (S ee Note) Min 500 ns
t
RSP
RESET# Setup Time for Temporary Sector
Unprotect Min 4µs
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
tVIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
tVIDR
tRSP
Program or Erase Command Sequence
Figure 22. Temporary Sector Unprotect/Timing Diagram
50 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h 60h 40h
Valid* Valid* Valid*
Status
Sector Protect/Unprotect Verify
VID
VIH
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector Protect/Unprotect Timing Diagram
December 17, 2004 S29AL016D_00_A2 S29AL016D 51
Preliminary
AC Characteristics
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the Erase and Programming Performance section for more information.
Parameter Speed Options
JEDEC Std
Description
70 90 Unit
t
AVAV
t
WC
Write Cycle T ime (Note 1)Min 70 90 ns
t
AVEL
t
AS
Address S etup Time Min 0ns
t
ELAX
t
AH
Address Hol d T ime Min 45 45 ns
t
DVEH
t
DS
Data Setup Time Min 35 45 ns
t
EHDX
t
DH
Data Hold T im e Min 0ns
t
OES
Ou tpu t Enable Setup Time Min 0ns
t
GHEL
t
GHEL
Read Recovery Time Be fore Write
(OE# High to WE# Low) Min 0ns
t
WLEL
t
WS
WE# Setup Time Min 0ns
t
EHWH
t
WH
WE# Hold Time Min 0ns
t
ELEH
t
CP
CE# Pulse Width Min 35 35 ns
t
EHEL
t
CPH
CE# Pulse W idth H igh Min 30 ns
t
WHWH1
t
WHWH1
Prog ramming Operati on (Note 2)Byte Typ 5µs
Word Typ 7
t
WHWH2
t
WHWH2
Sector Erase Operation (No te 2)Typ 0.7 sec
52 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
AC Characteristics
tGHEL
tWS
OE#
CE#
WE#
RESET#
tDS
Data
tAH
Addresses
tDH
tCP
DQ7# D
OUT
tWC tAS
tCPH
PA
Data# Polling
A0 for program
55 for erase
tRH
tWHWH1 or 2
RY/BY#
tWH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
tBUSY
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data
written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
Figure 24. Alternate CE# Controlled Write Operation Timings
December 17, 2004 S29AL016D_00_A2 S29AL016D 53
Preliminary
Erase and Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard
data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 9 for furt her information on command definition s.
6. The device has a mini mum erase and program cycle endurance of 100 ,000 cycles per sector .
TSOP and BGA Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25° C, f = 1.0 MHz.
Parameter
Typ (Note 1)Max (Note 2)Unit Comments
Sector Erase Time 0.7 10 sExcludes 00h programming
prior to erasure (Note 4)
Chip Erase Time 25 s
Byte Programm in g Time 5150 µs
Excludes system lev el
overhead (Note 5)
Word Programming Time 7210 µs
Chip Programming Time
(Note 3)
Byte Mode 11 33 s
Word Mode 7.2 21.6 s
Parameter
Symbol Parameter Description Test Setup Package Typ Max Unit
C
IN
Input Capacitance V
IN
= 0 TSOP 67.5 pF
BGA 4.2 5.0 pF
C
OUT
Outp ut Capacitance V
OUT
= 0 TSOP 8.5 12 pF
BGA 5.4 6.5 pF
C
IN2
Control Pin Capacitance V
IN
= 0 TSOP 7.5 9pF
BGA 3.9 4.7 pF
54 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Physical Dimensions
TS 048—48-Pin Standard TSOP
December 17, 2004 S29AL016D_00_A2 S29AL016D 55
Preliminary
* For reference only. BSC is an ANSI standard for Basic Space Centering.
6
2
3
4
5
7
8
9
MO-142 (D) DD
48
MIN
0.05
0.95
0.17
0.17
0.10
0.10
18.30
19.80
0.50
0˚
0.08
11.90
0.50 BASIC
MAX
0.15
1.20
0.27
0.16
0.21
8˚
0.20
18.50
12.10
0.70
20.20
0.23
1.05
0.20
1.00
0.22
18.40
20.00
0.60
12.00
NOM
Symbol
Jedec
b1
A2
A1
A
D
L
e
E
D1
b
c1
c
0
R
N
1
NOTES:
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
N
+1
2
N
1
2
N
3
REVERSE PIN OUT (TOP VIEW)
C
e
A1
A2
2X (N/2 TIPS)
0.10
9
SEATING
PLANE
A
SEE DETAIL A
B
B
AB
E
D1
D
2X
2X (N/2 TIPS)
0.25
2X
0.10
0.10
N
5
+1
N
2
4
5
1
N
2
2
STANDARD PIN OUT (TOP VIEW)
SEE DETAIL B
DETAIL A
(c)
θ°
L
0.25MM (0.0098") BSC
C
R
GAUGE PLANE
PARALLEL TO
SEATING PLANE
b
b1
(c)
76
c1
WITH PLATING
BASE METAL
7
0.08MM (0.0031") M C A - B S
SECTION B-B
DETAIL B
X
e/2
X = A OR B
3355 \ 16-038.10c
56 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Physical Dimensions
VBK048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 mm x 6.15 mm
3338 \ 16-038.25b
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
SIDE VIEW
TOP VIEW
SEATING PLANE
A2
A
(4X)
0.10
10
D
E
C0.10
A1
C
B
A
C0.08
BOTTOM VIEW
A1 CORNER
BA
M
φ 0.15 C
M
7
7
6
e
SE
SD
6
5
4
3
2
A
BCDEFG
1
H
φb
E1
D1
C
φ 0.08
PIN A1
CORNER
INDEX MARK
PACKAGE VBK 048
JEDEC N/A
8.15 mm x 6.15 mm NOM
PACKAGE
SYMBOL MIN NOM MAX NOTE
A --- --- 1.00 OVERALL THICKNESS
A1 0.18 --- --- BALL HEIGHT
A2 0.62 --- 0.76 BODY THICKNESS
D 8.15 BSC. BODY SIZE
E 6.15 BSC. BODY SIZE
D1 5.60 BSC. BALL FOOTPRINT
E1 4.00 BSC. BALL FOOTPRINT
MD 8 ROW MATRIX SIZE D DIRECTION
ME 6 ROW MATRIX SIZE E DIRECTION
N 48 TOTAL BALL COUNT
φb 0.35 --- 0.43 BALL DIAMETER
e 0.80 BSC. BALL PITCH
SD / SE 0.40 BSC. SOLDER BALL PLACEMENT
--- DEPOPULATED SOLDER BALLS
December 17, 2004 S29AL016D_00_A2 S29AL016D 57
Preliminary
SO044—44-Pin Small Outline Package (SOP)
28.20 mm x 13.30 mm
Dwg rev AC; 10/99
58 S29AL016D S29AL016D_00_A2 December 17, 2004
Preliminary
Revision Summary
Revision A (May 4, 2004)
Initial Release.
Revision A1 (July 28, 2004)
Ordering Information
Updated orderin g informat ion: model nu mber, speed o ptions, and val id combinati ons
for TSOP and BGA packages.
DC Characteristics
Updated Max information for ICC2.
Phys i cal Dimen sions
Updated VBK048 and TS 048 drawings.
Revision A2 (December 17, 2004)
Data Sh eet Type
Changed from Advance Information to Preliminary.
Ordering Information
Updated ordering information: Small Outline Package options
Phys i cal Dimen sions
Added SO044 Package.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary
industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that
includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,
medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and
artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-
tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other
abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by
Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided
as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement
of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the
use of the information in this document.
Copyright ©2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof are trademarks of Spansion LLC. Other
company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
