LT8550
1
Rev. 0
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VIN
REG
VIN
POWER STAGE 1
REG
REG REG
+
+
GND 8550 TA01a
ISP
ISN
TG1
BST1
SW1
BG1
ISP1
ISN1
10Ω
1nF
100µF
47µF
×2
47µF
×2
150µF
×2
10Ω
10Ω
33nF
220pF
10µF
10Ω
0.22µF
1nF
SENSEN
SENSEP
HG
CBOOT
SW
LG
100µF
47µF
×2
47µF
×2
150µF
×2
0.22µF
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
VOUT
VOUT
VOUT
ENOUT CLK1 REGSNS TGSR TGSH TGSLBGSHVIN
SHDN
REGIS
REGDRV
REG
PHS1
PHS2
ILIM
VCC
PHS3
SYNC
RT/MS
IAMPP
IAMPN
CTRL1
VREF
CTRL2
VC
RT SS EN/UVLO SYNC VCC_INT GND
FB
VIN
200k 47k
1Ω
10nF 1nF
22µF
1.3µH 2.5mΩ
1.3µH 2.5mΩ
88.7k
12.1k100k
RHOT
45.3k
10k
2.2µF
4.7nF
4.7µF
137k
1µF
RNTC
680k
LT8550
LT3741
PINS FOR
POWER
STAGE2,3,4
24k
62k
4.7µF
1Ω
PINS NOT SHOWN
IN THIS CIRCUIT:
ISP2, ISN2, BST2, TG2, SW2, BG2
ISP3, ISN3, BST3, TG3, SW3, BG3
ISP4, ISN4, BST4, TG4, SW4, BG4,
CLK2, TGBUF, BGBUF, MODE
VIN
14V TO
36V
MP
VOUT
10V/100A MAX
TYPICAL APPLICATION
FEATURES DESCRIPTION
4-Phase DC/DC Expander with
Internal Gate Drivers for Buck Converters
The LT
®
8550 is a multiphase expander for synchronous
buck DC/DC converters. It operates in tandem with any
buck DC/DC converter to increase the load current capa-
bility by adding additional phases, which are clocked out-
of-phase to reduce ripple current and filtering capacitance.
It easily adds phases without the need to route sensitive
feedback and control signals.
The LT8550 integrates gate drivers and can support up
to four buck phases per device. Multiple LT8550’s can
be used for up to 18 phases. It accurately monitors and
adjusts the current of each channel to achieve excellent
DC and transient current sharing.
The LT8550 operates over a fixed frequency from 100kHz
to 1MHz, or can be synchronized to an external clock.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 9077244.
10V/100A Step-Down Phase Expander System
n Expands Up to Four Phases per Chip
n Up to 80V Input or Output Voltage
n Cascade with Multiple Chips for Very High Current
Applications
n Supports Up to 18 Distinct Phases from 20° to 180°
n Phases Can Share Phase Angle
n Excellent DC and Transient Current Sharing
n Phase-Lockable Fixed Frequency 125kHz to 1MHz
n Supports Bidirectional Current Flow
n RSENSE or DCR Current Sensing
n Eliminates the Need to Route Sensitive Feedback and
Control Signals
n 52-Lead (7mm × 8mm) QFN Package
APPLICATIONS
n High Current Distributed Power Systems
n Telecom, Datacom, and Storage Systems
n Industrial and Automotive
LT8550
2
Rev. 0
For more information www.analog.com
ABSOLUTE MAXIMUM RATINGS
SW1/2/3/4 ...................................................80V (Note 5)
ISP1/2/3/4, ISN1/2/3/4, ISP, ISN,
VIN, REGIS, REGDRV Voltage (Note 2) ... –0.3V to 80V
SHDN Voltage ............................................ –0.3V to 70V
TGSL Voltage ................................................ –3V to 80V
TGSH Voltage ................................................ –3V to 86V
TG1/2/3/4, BST1/2/3/4, TGSR Voltage ...... –0.3V to 86V
BG1/2/3/4, RT/MS, SYNC, PHS1/2/3,
CLK1/2, REGSNS, IAMPP, ILIM, BGSH,
BGBUF, TGBUF, ENOUT, MODE, VCC,
REG, (BST-SW)1/2/3/4, (TG-SW)1/2/3/4,
(VIN-REGDRV), (TGSR-TGSL),
(TGSH-TGSL) Voltage .......................... –0.3V to 6.0V
IAMPN Voltage .......................................... –0.6V to 0.6V
(ISP-ISN)1/2/3/4, (ISP-ISN) Voltage ......... –0.3V to 0.3V
Operating Junction Temperature Range (Note 3)
LT8550E ............................................ –40°C to 125°C
LT8550I ............................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8550EUKG#PBF LT8550EUKG#TRPBF 8550 52-PIN (7mm × 8mm) Plastic QFN –40°C to 125°C
LT8550IUKG#PBF LT8550IUKG#TRPBF 8550 52-PIN (7mm × 8mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
1615 17 18 19
TOP VIEW
53
GND
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 125°C, θJA = 31°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
20 21 22 23 24 25 26
5152 50 49 48 47 46 45 44 43 42 41
33
34
35
36
37
38
39
40
8
7
6
5
4
3
2
1BG4
BG3
REG
SW3
TG3
BST3
BST2
TG2
SW2
BG2
BG1
BGBUF
TGBUF
BST1
REGSNS
ISN4
ISP4
ISN2
ISP2
ISN
ISP
IAMPP
IAMPN
SHDN
MODE
VCC
ENOUT
ILIM
BST4
TG4
SW4
VIN
REGDRV
REGIS
ISN3
ISP3
ISP1
ISN1
NC
PHS3
TG1
SW1
TGSR
TGSH
TGSL
CLK2
CLK1
BGSH
SYNC
PHS2
PHS1
RT/MS
32
31
30
29
28
27
9
10
11
12
13
14
PIN CONFIGURATION
LT8550
3
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage Range For Min Spec VCC, REG = 0V l3.6 80 V
VIN Quiescent Current REG = VCC = 5V, REGDRV REGIS Floating 800 µA
VIN Quiescent Current in Shutdown 2 µA
VCC Quiescent Current Not Switching 5 mA
VCC Undervoltage Lockout VCC Falling, REG = VCC l3.3 3.55 3.8 V
VCC Undervoltage Lockout Hysteresis REG = VCC 0.1 V
SHDN Input Voltage High SHDN Falling l1.05 1.15 1.25 V
SHDN Input Voltage High Hysteresis 60 mV
SHDN Input Voltage Low Device Disabled, Low Quiescent Current, VCC = 3V, REG = 3V l0.3 V
SHDN Pin Bias Current VSHDN = 3V
VSHDN = 12V
0
8.5
1
20
µA
µA
MODE Low Falling Threshold Slave LT8550 l 0.5 V
MODE High Rising Threshold Slave LT8550 l4.5 V
MODE Output Voltage Low Master LT8550, 200µA into MODE Pin 50 mV
MODE Output Voltage High Master LT8550, 20µA Out of MODE Pin 4.8 V
MODE Pin Impedance in Middle State Master LT8550 9 kΩ
ENOUT Output Voltage Low Master LT8550, 1mA into ENOUT Pin, VCC, REG in UVLO 60 mV
ENOUT Leakage Current ENOUT = 5V, REG, VCC = 3V 0.2 1 µA
ENOUT Rising Threshold 2.1 V
ENOUT Threshold Hysteresis 0.4 V
Current Sensing
Maximum Positive Current Sense Voltage,
(ISPn-ISNn)
ILIM = 0V, ISNn=12V, ISPn Rising
ILIM = REG, ISNn=12V, ISPn Rising
ILIM = Float, ISNn=12V, ISPn Rising
l
l
l
27
56
84.5
30
60
90
32.5
64
95.5
mV
mV
mV
Maximum Negative Current Sense Voltage,
(ISNn-ISPn)
ILIM = 0V, ISNn=12V, ISPn Falling
ILIM = REG, ISNn=12V, ISPn Falling
ILIM = Float, ISNn=12V, ISPn Falling
l
l
l
26.5
55.5
84
30
60
90
33
64.5
96
mV
mV
mV
ISP, ISN Common Mode Operating Voltage
Range
l0 80 V
ISPn, ISNn Common Mode Operating
Voltage Range
l0 80 V
ILIM High Rising Threshold l4.65 V
ILIM High Threshold Hysteresis 90 mV
ILIM Low Falling Threshold l0.3 V
ILIM Low Threshold Hysteresis 80 mV
ILIM Impedance at Floating 11 kΩ
IAMPP Output Voltage (ISP-ISN) = 30mV, ILIM = 0V, Master LT8550, ISN=12V
(ISP-ISN) = 0mV, ILIM = 0V, Master LT8550, ISN=12V
(ISP-ISN) = –30mV, ILIM = 0V, Master LT8550, ISN=12V
(ISP-ISN) = 60mV, ILIM = REG, Master LT8550, ISN=12V
(ISP-ISN) = 0mV, ILIM = REG, Master LT8550, ISN=12V
(ISP-ISN) = –60mV, ILIM = REG, Master LT8550, ISN=12V
(ISP-ISN) = 90mV, ILIM = Float, Master LT8550, ISN=12V
(ISP-ISN) = 0mV, ILIM = Float, Master LT8550, ISN=12V
(ISP-ISN) = –90mV, ILIM = Float, Master LT8550, ISN=12V
l
l
l
l
l
l
l
l
l
2.33
1.33
0.33
2.33
1.35
0.34
2.33
1.35
0.34
2.40
1.40
0.40
2.40
1.40
0.40
2.40
1.40
0.40
2.47
1.47
0.47
2.47
1.45
0.46
2.47
1.45
0.46
V
V
V
V
V
V
V
V
V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
LT8550
4
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
(ISPn-ISNn) Voltage In Regulation IAMPP = 2.20V, IAMPN = 0V, ILIM = 0V, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = 0V, ISNn = 12V
IAMPP = 2.20V, IAMPN = 0V, ILIM = REG, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = REG, ISNn = 12V
IAMPP = 2.20V, IAMPN = 0V, ILIM = Float, ISNn = 12V
IAMPP = 0.60V, IAMPN = 0V, ILIM = Float, ISNn = 12V
l
l
l
l
l
l
21.25
–26.75
45.0
–51.0
67.25
–76.75
26.75
–21.25
51.0
–45.0
76.75
–67.25
mV
mV
mV
mV
mV
mV
(ISP-ISN) to IAMPP Voltage Gain ILIM = 0V, Master LT8550, ISN = 0V
ILIM = REG, Master LT8550, ISN = 0V
ILIM = FLOAT, Master LT8550, ISN = 0V
33.3
16.7
11.1
IAMPP Sourcing Current Limit (ISP-ISN) = 0mV, Master LT8550 l250 µA
IAMPP Sinking Current Limit (ISP-ISN) = 0mV, Master LT8550 l60 µA
IAMPP Load Regulation ILOAD = –200µA to 50µA, Master LT8550 1 mV
IAMPP Pin Bias Current IAMPP = 1.2V, Slave LT8550
IAMPP = 2.4V, Slave LT8550
3
6
µA
µA
Mismatch Between (ISPn-ISNn) and Master
LT8550’s (ISP-ISN) in Regulation
ILIM = REG l–6
–4.75
6
4.75
%
%
Mismatch Between (ISPn-ISNn) and Master
LT8550’s (ISP-ISN) in Regulation
ILIM = FLOAT l–6
–5.5
6
5.5
%
%
Mismatch Between (ISPn-ISNn) and Master
LT8550’s (ISP-ISN) in Regulation
ILIM = 0V l–10
–8
10
8
%
%
Oscillator
CLK1 Frequency RT/MS = 24.3kΩ, Master LT8550
RT/MS = 100 kΩ, Master LT8550
RT/MS = 249kΩ, Master LT8550
l
l
l
900
236
90
1000
250
100
1100
264
110
kHz
kHz
kHz
Switching Frequency Range Free-Running
Synchronizing
l
l
100
125
1000
1000
kHz
kHz
SYNC High Level for Synchronization l1.2 V
SYNC Low Level for Synchronization l0.8 V
CLK1, CLK2 Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 7 ns
CLK1, CLK2 Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 5 ns
CLK2 Rising Threshold Slave LT8550 l4.0 V
CLK2 Falling Threshold Slave LT8550 l1.0 V
PHS1, PHS2 High Rising Threshold l4.65 V
PHS1, PHS2 High Threshold Hysteresis 80 mV
PHS1, PHS2 Low Falling Threshold l0.3 V
PHS1, PHS2 Low Threshold Hysteresis 80 mV
PHS1, PHS2 Impedance at Floating 11 kΩ
PHS3 Rising Threshold l4.65 V
PHS3 Threshold Hysteresis 80 mV
REG LDO
REG Voltage REGSNS = 5V, IAMPN = 0V, ILOAD = 45mA l4.9 5.1 5.3 V
REG LDO Current Limit VIN = 12V, REGSNS = 5V, REG, VCC = 4V
VIN = 24V, REGSNS = 5V, REG, VCC = 4V
250
145
mA
mA
REG LDO Gate Drive Clamp Voltage (VIN – REGDRV) Voltage, REG, VCC = 4.5V 5.3 V
REG Load Regulation ILOAD = 0 to 100mA, REGSNS = 5V, IAMPN = 0V 90 mV
REGSNS Pin Bias Current REGSNS = 5V 12 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
LT8550
5
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Drivers
TG1, TG2, TG3, TG4 Rise Time CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4) 30 ns
TG1, TG2, TG3, TG4 Fall Time CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4) 20 ns
BG1, BG2, BG3, BG4 Rise Time CLOAD = 3.3nF (Note 4) 50 ns
BG1, BG2, BG3, BG4 Fall Time CLOAD = 3.3nF (Note 4) 27 ns
Bottom & Top Gate Non-Overlap Time TG Falling to BG Rising, CLOAD = 3.3nF (Note 4)
BG Falling to TG Rising, CLOAD = 3.3nF (Note 4)
85
80
ns
ns
Bottom & Top Gate Minimum Off-Time CLOAD = 3.3nF (Note 4) 140 ns
Primary Gate Sensing
BGSH Rising Threshold l4.0 V
BGSH Falling Threshold l1.0 V
BGSH Threshold Hysteresis 1.4 V
BGSH to BGBUF Delay CLOAD = 220pF, Master LT8550 (Note 4) 45 ns
BGBUF Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 8 ns
BGBUF Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 6 ns
TGSH Rising Threshold TGSR = 5V, TGSL = 0V l4.0 V
TGSH Falling Threshold TGSR = 5V, TGSL = 0V l1.0 V
TGSH Threshold Hysteresis 1.4 V
TGSH to TGBUF Delay CLOAD = 220pF, Master LT8550 (Note 4) 45 ns
TGBUF Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 8 ns
TGBUF Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 6 ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating Condition for extended periods may affect device
reliability and lifetime.
Note 2: Do not apply a positive or negative voltage or current source
to REGDRV, BG1, BG2, BG3, BG4, TG1, TG2, TG3 and TG4, otherwise
permanent damage may occur.
Note 3: The LT8550E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8550I is guaranteed to meet performance specifications from –40°C to
125°C junction temperature.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: Negative voltages on SW1/2/3/4 pins are limited, in an application,
by the body diodes of the external NMOS devices, or the parallel Schottky
diodes when present. The SW1/2/3/4 pins are tolerant of these negative
voltages in excess of one diode drop below ground, guaranteed by design.
LT8550
6
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
REG LDO Load Regulation REG Voltage vs REGSNS Voltage REG LDO Current Limit
REG Quiescent Current vs
VIN Voltage, Not Switching
REG Quiescent Current vs
Temperature, Not Switching REG LDO Line Regulation
VCC Quiescent Current vs
VIN Voltage, Not Switching
VCC Quiescent Current vs
Temperature, Not Switching VCC UVLO Threshold
REG LDO LOAD CURRENT (mA)
0
45
90
135
180
225
4.8
4.9
5.0
5.1
5.2
5.3
REG VOLTAGE (V)
8550 G01
T = 25°C
REGSNS = 5V
IAMPN = 0V
VIN = 12V
REGSNS VOLTAGE (V)
3.5
4.5
5.5
4.0
4.3
4.6
4.9
5.2
5.5
REG VOLTAGE (V)
8550 G02
T = 25°C
IAMPN = 0.1V
IAMPN = 0V
IAMPN = –0.1V
T = 25°C
VIN VOLTAGE (V)
10
20
30
40
50
60
70
80
60
120
180
240
300
REG LDO CURRENT LIMIT (mA)
8550 G03
VIN VOLTAGE (V)
5
15
25
35
45
55
65
75
85
5.0
7.5
10.0
12.5
15.0
17.5
20.0
REG QUIESCENT CURRENT (µA)
8550 G04
T = 130°C
T = 25°C
T = –50°C
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
REG QUIESENCT CURRENT (µA)
8550 G05
VIN = 6V
VIN = 12V
VIN = 80V
LOAD = 0mA
T = 25°C
REGSNS–IAMPN = 5V
VIN VOLTAGE (V)
10
20
30
40
50
60
70
80
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
REG VOLTAGE (V)
8550 G06
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
3.0
3.2
3.4
3.6
3.8
4.0
VCC UVLO THRESHOLD (V)
8550 G09
T = 25°C
T = 150°C
T = –50°C
VIN VOLTAGE (V)
10
20
30
40
50
60
70
80
4.9
5.0
5.1
5.2
5.3
V
CC
QUIESCENT CURRENT (mA)
8550 G07
VIN = 6V
VIN = 12V
VIN = 80V
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.9
5.0
5.1
5.2
5.3
V
CC
QUIESCENT CURRENT (mA)
8550 G08
LT8550
7
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
SHDN Pin Threshold VIN UVLO Threshold
VIN Quiescent Current vs
VIN Voltage, Not Switching
VIN Quiescent Current vs
Temperature, Not Switching SHDN Pin Current vs Voltage
IAMPP-IAMPN Voltage vs
(ISP-ISN) Voltage
Maximum Positive Current Limit
vs Temperature
Maximum Negative Current Limit
vs Temperature PHS1 Pin Current
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
1.10
1.15
1.20
1.25
1.30
SHDN PIN THRESHOLD (V)
8550 G10
FALLING
RISING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
3.0
3.1
3.2
3.3
3.4
3.5
VIN UVLO THRESHOLD (V)
8550 G11
T = 130°C
T = 25°C
T = –50°C
VIN VOLTAGE (V)
15
25
35
45
55
65
75
85
4.8
4.9
5.0
5.1
5.2
5.3
5.4
5.5
5.6
VIN QUIESCENT CURRENT (mA)
8550 G12
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.7
4.9
5.1
5.3
5.5
5.7
VIN QUIESENCT CURRENT (mA)
8550 G13
VIN = 6V
VIN = 12V
VIN = 80V
SHDN PIN VOLTAGE (V)
10
20
30
40
50
60
70
10
15
20
25
30
SHDN PIN CURRENT (µA)
8550 G14
T = 150°C
T = 25°C
T = –50°C
T = 25°C
ISP–ISN VOLTAGE (mV)
–90
–60
–30
30
60
90
0.2
0.5
0.8
1.1
1.4
1.7
2.0
2.3
2.6
IAMPP–IAMPN VOLTAGE (V)
8550 G15
ILIM = FLOAT
ILIM = REG
ILIM = GND
ILIM = REG
ILIM = FLOAT
ILIM = GND
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
20
30
40
50
60
70
80
90
100
MAXIMUM POSITIVE CURRENT LIMIT (mV)
8550 G16
ILIM = FLOAT
ILIM = REG
ILIM = GND
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
–100
–90
–80
–70
–60
–50
–40
–30
–20
MAXIMUM NEGATIVE CURRENT LIMIT (mV)
8550 G17
T = 25°C
PHS1 PIN VOLTAGE (V)
–180
–120
–60
60
120
180
PHS1 PIN CURRENT (µA)
8550 G18
LT8550
8
Rev. 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
PHS1 High Threshold Voltage vs
Temperature
PHS1 Low Threshold Voltage vs
Temperature PHS2 Pin Current
PHS2 High Threshold Voltage vs
Temperature
PHS2 Low Threshold Voltage vs
Temperature PHS3 Pin Current
PHS3 Threshold Voltage vs
Temperature ILIM Pin Current vs Voltage
ILIM High Threshold Voltage vs
Temperature
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.25
4.30
4.35
4.40
4.45
4.50
PHS1 VOLTAGE (V)
8550 G19
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.4
0.5
0.6
0.7
0.8
PHS1 VOLTAGE (V)
8550 G20
T = 25°C
PHS2 PIN VOLTAGE (V)
–180
–120
–60
60
120
180
PHS2 PIN CURRENT (µA)
8550 G21
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.25
4.30
4.35
4.40
4.45
4.50
PHS2 VOLTAGE (V)
8550 G22
RISING
FALLING
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
0.4
0.5
0.6
0.7
0.8
PHS2 VOLTAGE (V)
8550 G23
T = 25°C
PHS3 PIN VOLTAGE (V)
10
15
20
25
30
35
40
PHS3 PIN CURRENT (µA)
8550 G24
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.25
4.30
4.35
4.40
4.45
4.50
PHS3 VOLTAGE (V)
8550 G25
ILIM VOLTAGE (V)
–180
–120
–60
60
120
180
ILIM PIN CURRENT (µA)
8550 G26
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
4.20
4.25
4.30
4.35
4.40
ILIM VOLTAGE (V)
8550 G27
LT8550
9
Rev. 0
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TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
ILIM Low Threshold Voltage vs
Temperature ENOUT Threshold Voltage TGSR-TGSL UVLO Threshold
Oscillator Frequency vs
Temperature BST-SW UVLO Threshold
Efficiency and Power Loss vs
Load Current — LT8550 + LT3763
Load Response from 0A to 80A —
LT3741 + LT8550
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
0.3
0.4
0.5
0.6
0.7
0.8
0.9
ILIM VOLTAGE (V)
8550 G28
RISING
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
ENOUT THRESHOLD VOLTAGE (V)
8550 G29
FALLING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
2.20
2.25
2.30
2.35
2.40
TGSR–TGSL UVLO THRESHOLD (V)
8550 G30
RT = 249K
RT = 100K
RT = 49.9K
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
100
200
300
400
500
600
OSCILLATOR FREQUENCY (kHz)
8550 G31
FALLING
RISING
TEMPERATURE (°C)
–50
–25
25
50
75
100
125
150
3.3
3.4
3.5
3.6
3.7
BST–SW UVLO THRESHOLD (V)
8550 G32
V
OUT
= 12V
EFFICIENCY
POWER LOSS
fs = 250kHz
24V
IN–W/O SHEDDING
24V
IN–W/ SHEDDING
56V
IN–W/O SHEDDING
56V
IN–W/ SHEDDING
LOAD CURRENT (A)
0.1
10
100
10
20
30
40
50
60
70
80
90
100
10
100
1k
EFFICIENCY (%)
POWER LOSS (W)
8550 G33
400µs/DIV
EXPANDER IL4
10A/DIV
EXPANDER IL3
10A/DIV
EXPANDER IL2
10A/DIV
PRIMARY IL
10A/DIV
8550 G34
fS = 350kHz
VIN = 24V
V
OUT
= 6V
LT8550
10
Rev. 0
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PIN FUNCTIONS
REG (Pin 3): Output of REG LDO. Power supply for gate
drivers. Decouple this pin to ground with a minimum
4.7µF low ESR ceramic capacitor. Connect this pin to the
external PMOS drain side.
BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1): Bottom Gate
Driver Output. These pins drive the gates of the bottom
N-channel MOSFETs. Voltage swing at these pins is from
ground to REG.
BGBUF (Pin 12): Logic Output Pin. This pin is pulled up
to REG when BGSH is at logic high, and it is pulled down
to ground when BGSH is at logic low. For a slave LT8550,
leave this pin floating. See the Applications Information
section for more information.
TGBUF (Pin 13): Logic Output Pin. For a master LT8550,
this pin is pulled up to REG voltage when (TGSH-TGSL)
is at logic high, and it is pulled down to ground when
(TGSH-TGSL) is at logic low. For a slave LT8550, leave
this pin floating. See the Applications Information section
for more information.
BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52): Boosted
Floating Driver Supply. The (+) terminal of the boost-strap
capacitor is connected to this pin. This pin swings from a
diode voltage drop below REG up to VIN + REG.
TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51): Top Gate Driver
Output. This is the output of a floating driver with a volt-
age swing equal to REG superimposed on the switch node
voltage.
SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50): Switch Node.
Voltage swing at these pins is from a diode voltage drop
below ground to VIN.
TGSR (Pin 17): The Rail of Primary Channel Top Gate
Sense Circuit. For a master LT8550, connect this pin to
the primary channel top gate driver’s boost node. This pin,
combined with TGSH, TGSL pins, is to sense the primary
channel top MOSFET’s state. For a slave LT8550, connect
this pin to REG.
TGSH (Pin 18): Input of Primary Channel Top Gate Sense
Circuit. For a master LT8550, connect this pin to the pri-
mary channel top MOSFET’s gate. This pin, combined
with TGSR, TGSL pins, is to sense the primary channel
top MOSFET’s state. For a slave LT8550, connect this pin
to the master LT8550’s TGBUF pin.
TGSL (Pin 19): Lower Rail of Primary Channel Top Gate
Sense Circuit. For a master LT8550, connect this pin to
the primary channel top MOSFET’s source. This pin, com-
bined with TGSR, TGSH pins, is to sense the primary
channel top MOSFET’s state. For a slave LT8550, connect
this pin to ground.
CLK1, CLK2 (Pins 21, 20): Clock Pin. These two pins
are used to synchronize the primary channel to all other
channels. See the Applications Information section for
more information.
BGSH (Pin 22): Logic Input of Primary Channel Bottom
Gate Sense Circuit. For a master LT8550, connect this
pin to the primary channel bottom MOSFET’s gate. This
pin is to sense the primary channel bottom MOSFET’s
state. For a slave LT8550, connect this pin to the master
LT8550’s BGBUF pin.
SYNC (Pin 23): To synchronize the switching frequency to
an outside clock, simply drive this pin with a clock. The
high voltage level of the clock must exceed 1.2V, and the
low level must be less than 0.8V. Drive this pin to less
than 0.8V to revert to the internal free-running clock. See
the Typical Applications section.
PHS1, PHS2 (Pins 25, 24): Phase Selection Pin. These
pins, combined with PHS3 and RT/MS, set the switch-
ing frequency and the phase of each channel. PHS1 and
PHS2 are three-level input pins, they can be floated, set
to REG or ground. When the PHS1/PHS2 is floating, add
a 1nF cap from PHS1/PHS2 to ground. See the Operation
section for more information.
RT/MS (Pin 26): Timing Resistor Pin and Master Slave
Selection Pin. This pin, combined with PHS1, PHS2 and
PHS3, sets the switching frequency and the phase of
each channel. Connecting a resistor to ground sets the
chip as master LT8550. Connecting this pin to the REG
pin sets the chip as slave LT8550. See the Applications
Information section for more information.
(QFN)
LT8550
11
Rev. 0
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PIN FUNCTIONS
ILIM (Pin 27): Maximum Current Sense Voltage
Programming Pin. This pin is used to set the maximum
sense voltage in the primary channel current sense ampli-
fier and expanded channel current sense amplifier. It is a
three level input pin. Connecting this pin to ground, REG
or leaving it floating sets the maximum current sense
voltage to 30mV, 60mV or 90mV, respectively. When the
ILIM is floating, add a 1nF cap from the ILIM to ground.
ENOUT (Pin 28): For a master LT8550, this pin is an open-
drain logic output pin. For a slave LT8550, it is an input
pin. See more details in ENOUT Connection Section.
V
CC
(Pin 29): Power supply for control circuits. Decouple
this pin to ground with a minimum 1µF low ESR ceramic
capacitor. VCC and REG need to be connected through a
1Ω resistor.
MODE (Pin 30): Stage Shedding Selection Pin. Connecting
this pin to GND disables stage shedding feature. See the
Operation section for more information.
SHDN (Pin 31): Shutdown Pin. This pin is used to enable/
disable the chip. Drive below 0.3V to disable the chip.
Drive above 1.2V (typical) to activate the chip. Do not
float this pin.
IAMPN (Pin 32): For a master LT8550, connect this pin
to local ground. For a slave LT8550, connect this pin
to the master LT8550’s IAMPN. See the Applications
Information section for more information.
IAMPP (Pin 33): For a master LT8550, this is an out-
put pin. It is the buffered signal of the Primary Channel
Current Sense Amplifier output. For a slave LT8550, this
is an input pin. When multiple LT8550s are used, connect
all IAMPP pins together. See the Applications Information
section for more information.
ISP (Pin 34): Primary Channel Current Sense Amplifier
Input. The (+) input to the current sense amplifier is nor-
mally connected to DCR sensing network or current sens-
ing resistor. This pin is only used for a master LT8550.
Ground this pin for a slave LT8550.
ISN (Pin 35): Primary Channel Current Sense Amplifier
Input. The (–) input to the current sense amplifier is
normally connected to DCR sensing networks or cur-
rent sensing resistors. This pin is only used for a master
LT8550. Ground this pin for a slave LT8550.
REGSNS (Pin 40): REG LDO Voltage Sense Pin. Connect
this pin to the primary channel gate driver power supply
pin.
PHS3 (Pin 41): Phase Select Pin. This pin, combined with
PHS1, PHS2 and RT/MS, set the switching frequency and
the phase of each channel. PHS3 connects to REG or
ground. See the Operation section for more information.
NC (Pin 42): No Connection. Leave this pin floating or
connect to any adjacent pin.
ISN1, ISN2, ISN3, ISN4 (Pins 43, 37, 46, 39): Expanded
Channel Current Sense Amplifier (–) Input. The (–) input
to the current sense amplifier is normally connected to
DCR sensing network or current sensing resistor.
ISP1, ISP2, ISP3, ISP4 (Pins 44, 36, 45, 38): Expanded
Channel Current Sense Amplifier (+) Input. The (+) input
to the current sense amplifier is normally connected to
DCR sensing network or current sensing resistor.
REGIS (Pin 47): REG LDO Current Sense Pin. Connect
this pin to the external PMOS source side.
REGDRV (Pin 48): Gate Driver Output for REG LDO.
Connect this pin to the external PMOS gate.
VIN (Pin 49): Input Supply Pin. Must be locally bypassed
to ground.
GND (Exposed Pad Pin 53/Pin 27): Ground. Tie directly
to local ground plane.
(QFN)
LT8550
12
Rev. 0
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BLOCK DIAGRAM
VIN REG
ILIM
VC1
VIN REG
ILIM
VC4
CHANNEL 2 AND 3
NOT SHOWN
V
BIAS
–
+
–
+
8550 BD
SHDN
ENOUT
VIN
REGIS
REGDRV ISP1
ISN1
REG
TIMING
CONTROL
1
CURRENT LIMIT
AND
FAULT CONTROL 1
EA1
IAMP_INT1
A1
–
+
–
+
REGSNS
IAMPN
STAGE
SHEDDING
CONTROL
START-UP CONTROL
UVLO_VIN
UVLO_VCC
OT
ENOUT
CONTROL
CURRENT
LIMIT
CONTROL
A6
REGS_INT
A5 (1×)
–
+
1.8V
–
+
A0
–
+
A7 (1×)
VOUT
–
+
–
+
BST4
TG4
SW4
BG4
BST1
TG1
SW1
BG1
ISP4
ISN4
REG
TIMING
CONTROL
4
CURRENT LIMIT
AND
FAULT CONTROL 4
EA4
IAMP_INT4
A4
VOUT
REG
MODE
VCC
ILIM
IAMPP
IAMPN
ISP
ISN
SYNC
PHS1
PHS2
PHS3
CLK1
CLK2
TGSR
TGSH
TGSL
BGSH
TGBUF
BGBUF
REG
PRIMARY
GATE
SENSING
OSCILLATOR
AND CLOCK
PROCESSING
RT/MS
1×
31
28
49
47
48 44
43
40
52
51
50
1
14
15
16
11
38
39
3
30
29
27
33
32
34
35
23
25
24
41
21
20
17
18
19
22
13
12
26
IAMP_INT
LT8550
13
Rev. 0
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OPERATION
Introduction
The LT8550 is a multiphase expander for synchronous
buck controllers. Each LT8550, which has 8 gate driv-
ers, can expand up to four phases. Multiple LT8550s can
also be used together in a system, and up to 18 different
phases can be supported. In addition, the part supports
more than one phase per phase angle.
The ADI proprietary control architecture allows the
LT8550 to cycle-by-cycle duplicate the operation of a buck
controller (named as Primary Controller). The LT8550
measures the primary controller’s inductor current as well
as primary controller’s gate driver operation timing, and at
the same time, accurately monitors and adjusts the cur-
rent of each expanded channel to achieve excellent DC and
transient current sharing. The current sharing accuracy
is ±6%, ±6% and ±10% over temperature when ILIM set
at REG, Float and GND, respectively.
In normal operation, the primary buck regulator’s switch
current is compared with the expanded channel’s switch
current by the EA (EA1/2/3/4 in the Block Diagram).
When the primary channel’s current increases, the VC
(VC1/2/3/4 in the Block Diagram) voltage also increases,
which in turn controls the expanded channel’s switches to
increase the current until the expanded channel’s current
matches the primary channel’s current.
System with Multiple LT8550s
One LT8550 can expand up to four channels. This config-
uration can provide enough power for most high current
applications. However, for even higher power applications,
the LT8550 can be configured for multi-chip operation.
When two or more LT8550s are used together in a system,
one LT8550 is the master and other LT8550s are slaves.
Connecting a resistor from the RT/MS pin to ground sets
the chip as the master and connecting the RT/MS pin to
REG sets the chip as a slave. When only one LT8550 is
used in a system, this LT8550 needs to be set as a master.
Stage Shedding Mode
The MODE pin is dedicated for the Stage Shedding fea-
ture. The MODE pin is an output pin for a master LT8550,
and it is an input pin for a slave LT8550.
For a master LT8550, when the MODE pin is floating, the
LT8550 operates in Stage Shedding mode at light loads.
In this case, when the (ISP-ISN) peak voltage is lower
than a certain value for some period of time, the part
turns off channels1 and 3 to increase overall efficiency.
After channel 1 and 3 are off, if the (ISP-ISN) peak volt-
age is still lower than a certain value for some period of
time, the part also turns off channel 4 and only leaves
channel2 running. For bidirectional applications, stage
shedding should be disabled when the current is regulated
in the reverse direction. Driving the MODE pin below 0.5V
disables the Stage Shedding feature.
In a multiple LT8550s system, all chips’ MODE pins need
to be connected together and left floating if the Stage
Shedding feature is desired. The master LT8550 senses
the (ISP-ISN) voltage to decide proper operation. The slave
LT8550s follows the master LT8550’s Stage Shedding
operation with some delay. Driving all chips’ MODE pins
below 0.5V disables the Stage Shedding feature.
Clock Scheme
This section discusses the LT8550 clock scheme for a
multiple LT8550 system. This clock scheme can easily
apply to a single LT8550 system by ignoring the slave
LT8550s.
A master LT8550 generates two clock signals: CLK1 and
CLK2. In a multiple LT8550 system, as shown in Figure1,
all LT8550s’ CLK2 pins need to be connected together.
The CLK1 signal is at the fundamental switching fre-
quency (Refer to Internal Oscillator and SYNC Pin and
Clock Synchronization sections for more information),
and it is used to synchronize the primary buck controller
and the slaves (in Figure1). Under normal operation, the
CLK2 frequency is at the CLK1 frequency times the total
distinct phase number (TDPN), as shown in Figure2. The
number shown above the CLK2 pulses in Figure2 is called
the phase angle number (PAN).
LT8550
14
Rev. 0
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OPERATION
The total distinct phase number is programmed through
the master LT8550’s PHS1, PHS2 and PHS3 pins, accord-
ing to Table1. There is a delay locked loop in the chip
which can force the primary controller’s (TG-SW) rising
edge to align with the pulse whose phase angle number
equals the TDPN (in Figure2).
Each expanded channel chooses one pulse from CLK2 in
one CLK1 clock cycle. The rising edge of this chosen pulse
aligns with the corresponding channel’s top gate turn on
edge with a very short delay. The master LT8550’s chan-
nel 1 to channel 4 always choose the pulses whose phase
angle number equals 1 to 4, respectively. Four channels
of a slave LT8550 choose pulses with four consecu-
tive phase angles. The phase angle number of the slave
LT8550’s channel 1 pulse is also programmed through
PHS1, PHS2 and PHS3 pins, according to Table1, and
the pulses of the slave LT8550’s channel 2, channel 3
and channel 4 have the next three phase angle number
in succession.
REGREG
• • •
8550 F01
MASTER
LT8550
SYNC
CLK1
CLK2
RT/MS
PRIMARY
CONTROLLER
SYNC
SLAVE
LT8550
SYNC
CLK1
CLK2
RT/MS
SLAVE
LT8550
SYNC
CLK1
CLK2
RT/MS
Figure1. Clock Configuration in a Multiple LT8550 System
Table2 shows the PHS1, PHS2 and PHS3 connections
for a two LT8550 system with a total of 9 phases, includ-
ing the primary controller’s phase, as an example. The
primary controller uses the CLK1 signal. The clocks used
by the eight expanded channels are shown in Figure3.
When the primary controller skips one or more pulses,
the expanded channels also skip the same number of
pulse(s). This function is realized by CLK2. As shown in
Figure4, when the primary controller skips one (TG-SW)
pulse, the CLK2 also skips a group of pulses with phase
number from 1 to TDPN.
Table1. Table for Programming Total Distinct Phase Number
(TDPN) and Phase Angle Number (PAN)
PHS3 PHS2 PHS1 TDPN for Master
PAN of Slave
Channel 1 Pulse
GND GND GND NA 1
GND GND REG 2 2
GND GND Floating 3 3
GND REG GND 4 4
GND REG REG 5 5
GND REG Floating 6 6
GND Floating GND 7 7
GND Floating REG 8 8
GND Floating Floating 9 9
REG GND GND 10 10
REG GND REG 11 11
REG GND Floating 12 12
REG REG GND 13 13
REG REG REG 14 14
REG REG Floating 15 15
REG Floating GND 16 16
REG Floating REG 17 17
REG Floating Floating 18 18
Table2. Design Example for a 9-Phase Application
PHS3 PHS2 PHS1
PAN for Channel
1, 2, 3 and 4
Master LT8550 GND Floating Floating 1,2,3,4
Slave LT8550 GND REG REG 5,6,7,8
LT8550
15
Rev. 0
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OPERATION
• • •
8550 F06
TDPN-1 TDPN TDPN-1 TDPN11 2 1 2
CLK2
CLK1
PRIMARY’S
(TG-SW)
8550 F05
CLOCK FOR SLAVE
CHANNEL 4
CLOCK FOR SLAVE
CHANNEL 3
CLOCK FOR SLAVE
CHANNEL2
CLOCK FOR SLAVE
CHANNEL 1
CLOCK FOR MASTER
CHANNEL 4
CLOCK FOR MASTER
CHANNEL 3
CLOCK FOR MASTER
CHANNEL 2
CLOCK FOR MASTER
CHANNEL 1
891234567891234567891234567
CLK2
CLK1
PRIMARY’S
(TG-SW)
• • • • • •
8550 F06
TDPN-1 TDPN 1 TDPN-1 TDPN 1 TDPN-1 TDPN 1
CLK2
CLK1
PRIMARY’S
(TG-SW)
Figure2. CLK1, CLK2 and Primary’s (TG-SW)
Figure3. Clock Waveforms for a Two LT8550 System
Figure4. CLK1, CLK2 and Primary’s (TG-SW) Waveforms for Pulse Skipping
LT8550
16
Rev. 0
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OPERATION
Primary Controller’s Switch State Detection
This section discusses a system with multiple LT8550s.
For a single LT8550 system, simply ignore the slave
LT8550s in this discussion.
The primary controller’s switch states are detected by
the master LT8550, and this information is used by both
master and slave LT8550s.
The primary controller’s top switch state is sensed by
the master LT8550’s TGSR, TGSH, and TGSL pins, as
shown in Figure5. This floating top gate logic signal is
converted to a ground based logic signal, and outputted
to the TGBUF pin. The master LT8550’s TGBUF is then
connected to the downstream slaves’ TGSH, as shown in
Figure5. The slave’s TGSR and TGSL are connected to the
REG and GND respectively. If the (TGSR-TGSL) voltage is
less than 2.3V (typical), the TGBUF pin will be forced to
ground for both of the master and slave LT8550. See the
Applications Information section for more information.
A similar method is used for the primary controller’s bot-
tom switch state detection, also shown in Figure5. Since
the primary BG is a ground based signal, only one pin
(BGSH) is needed for the primary’s BG detection.
Since the master LT8550 passes the primary’s switch
states to the slaves, this avoids routing the primary’s
noisy BST, TG, SW and BG signals around the board.
REGREG
• • •
8550 F07
MASTER
LT8550
TGBUF
BGBUF
TGSR
TGSH
TGSL
BGSH
RT/MS
PRIMARY
CONTROLLER
BST
TG
SW
BG
SLAVE
LT8550
TGBUF
BGBUF
TGSR
TGSH
TGSL
BGSH
RT/MS
SLAVE
LT8550
TGBUF
BGBUF
TGSR
TGSH
TGSL
BGSH
RT/MS
Figure5. Gate Sensing in a Multiple LT8550 System
Primary Controller’s Inductor Current Sensing
This section discusses a system with multiple LT8550s.
For a single LT8550 system, simply ignore the slave
LT8550s in this discussion.
The primary controller’s inductor current is detected by
the master LT8550, and this information is used by both
the master and slave LT8550s.
As shown in Figure6, the primary controller’s inductor
current is detected by the master LT8550’s ISP and ISN
pins. This signal is amplified, and then outputted to the
master LT8550’s IAMPP pin. For stability purposes, a cap
is required from the IAMPP to GND, and total capaci-
tance must be between 100pF and 470pF. For a slave
LT8550, the ISP and ISN pins are not used and should
be grounded, and the IAMPP is an input pin. To pass the
primary’s inductor current information from the master
LT8550 to the slave LT8550s, all LT8550s’ IAMPP and
IAMPN pins are connected together, respectively. Connect
the IAMPN pins to the master LT8550’s local ground.
The IAMPP and IAMPN are connected to the inputs of
a unity gain differential sense amplify (A7 in the Block
Diagram). See the Applications Information section for
more information.
The signal across the primary inductor current sense
resistor is only tens of mV. By passing the amplified cur-
rent signal from the master to the slaves, routing sensitive
small signals around the board is avoided.
REGREG • • •
RSENSE
8550 F07
MASTER
LT8550
IAMPP
IAMPN
ISN
ISP
RT/MS
SLAVE
LT8550
IAMPP
IAMPN
ISN
ISP
RT/MS
SLAVE
LT8550
IAMPP
IAMPN
ISN
ISP
RT/MS
Figure6. Primary Regulator’s Switch Current Sensing in Multiple
LT8550 System
LT8550
17
Rev. 0
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OPERATION
Current Sensing Gain, Limit and Fault
The gain of five current amplifiers (A0 to A4 in the Block
Diagram) has three gain levels which are set by the ILIM
pin. Connecting the ILIM pin to GND/REG/Floating sets
the gain to 33.3/16.7/11.1, respectively. The outputs of
these amplifiers are called IAMP_INT/IMAP_INTx (in the
Block Diagram). The relation between the IAMP_INT/
IAMP_INTx and the (ISP-ISN)/(ISPx-ISNx) are shown in
Figure7. There is a 1.4V offset. For expanded channels,
the IAMP_INTx’s value determines the current limit and
current fault as shown in Figure8.
When the IAMP_INTx reaches 2.4V but lower than 2.8V,
or if it drops below 0.4V, the corresponding channel
enters current limit. When the current limit condition is
detected, both corresponding channel’s BGx and TGx are
pulled low immediately. The channel resumes switching at
the next clock rising edge after the current limit condition
is removed. The corresponding (ISPx-ISNx) voltages at
current limit are indicated in Figure7.
When the IAMP_INTx reaches 2.8V, the corresponding
channel enters current fault. When the current fault con-
dition is detected, the corresponding channel enters into
a fault sequence which is described in more detail in the
Fault Sequence section.
Shutdown and Start-Up
Figure9 illustrates the start-up sequence for the LT8550.
The shutdown pin for the chip is SHDN. When it is driven
below 0.3V, the chip is disabled (chip off state) and qui-
escent current is minimal. Increasing the SHDN voltage
can increase quiescent current but will not enable the chip
until SHDN is driven above 1.15V (typical) after which the
REG LDO is enabled (switcher off state).
Starting up the switching regulator happens after VCC
has risen above 3.55V (typical) and the ENOUT has been
driven above 2.1V (typical). For a master LT8550, the
ENOUT is an open drain pin. When VCC is lower than
3.55V, the ENOUT is pulled to GND to disable switching.
For a slave LT8550, the ENOUT is always a high imped-
ance input pin.
Fault Sequence
The LT8550 activates a fault sequence (see Figure9)
when IAMP_INTx is higher than 2.8V, which is the fault
condition for a LT8550. The fault event is independent of
channels, which means that the fault condition occurring
in one channel won’t directly affect other channels. If one
of these conditions occurs for a certain channel, the cor-
responding channel’s gate driver outputs are pulled low. If
one of the LT8550’s channels enters latch off mode (see
Figure9), only restarting the whole chip will reactivate
the channel.
–90
2.4
1.4
0.4
60
8550 F07
9030–30–60
ILIM = FLOAT
GAIN = 11.1
ILIM = REG
GAIN = 16.7
IAMP_INT (V)
IAMP_INTx (V)
(ISP – ISN) (mV)
(ISPx – ISNx) (mV)
ILIM = GND, GAIN = 33.3
ILIM = REG, GAIN = 16.7
ILIM = FLOAT, GAIN = 11.1
Figure7. Current Sensing Amplifier Output Vs. Input
at Three Different Gains
CURRENT FAULT
CURRENT LIMIT
CURRENT LIMIT
NORMAL OPERATION
IAMP_INTx (V)
2.8
0.4
2.4
0
8550 F08
Figure8. IAMP_INTx Voltage for Current Limit and Current Fault
LT8550
18
Rev. 0
For more information www.analog.com
OPERATION
ENOUT > 2.1V (TYPICAL) AND VCC > 3.55V (TYPICAL)
SHDN > 1.15V (TYPICAL) AND VIN > 3.3V (TYPICAL) AND
TJUNCTION <165°C (TYPICAL) AND
(ENOUT <2.1V (TYPICAL) OR VCC < 3.55V (TYPICAL))
SHDN < 1.15V (TYPICAL) OR
VIN < 3.3V (TYPICAL) OR
TJUNCTION >165°C (TYPICAL)
YES
NO
YES
8550 F09
FAULT
FAULT
FAULT
SWITCHER OFF
• SWITCHER OFF
• REG LDO ON
CHIP OFF
• SWITCHER OFF
• REG LDO OFF
FAULT DETECTED
• SWITCHER DISABLED
• FAULT COUNTER +1
• WAITING FOR FAULT CONDITION CLEARED
NORMAL MODE
• NORMAL OPERATION
• RESET FAULT COUNTER
POST FAULT DELAY
• SWITCHER DISABLED
• WAITING FOR ABOUT 800 CLOCK CYCLES
PRE-NORMAL MODE
• NORMAL OPERATION FOR ABOUT 800
CLOCK CYCLES
LATCH OFF MODE
• SWITHER DISABLED
IS
FAULT COUNTER
LESS THAN 15?
Figure9. Start-Up and Fault Sequence
ENOUT Connection
For a master LT8550, this pin is an open-drain logic output
pin. The master LT8550’s ENOUT pin is pulled to ground
when it is not ready for switching. For a slave LT8550, this
pin is an input pin. For both master and slave LT8550s,
when the ENOUT pin is lower than 2.1V (typical), the gate
driver’s switching activity is disabled.
When a master LT8550 is not ready for switching, it is
desired to disable the primary controller and the slave
LT8550s’ switching activity. Figure 10 is one recom-
mended configuration.
REG
47pF
CONNECT TO
SYSTEM ENABLE SIGNAL
47k
8550 F10
PRIMARY
CONTROLLER
EN OR
SHND
MASTER
LT8550
ENOUT
SHDN
SLAVE
LT8550
ENOUT
SHDN
Figure10. Recommended ENOUT Connection
LT8550
19
Rev. 0
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APPLICATIONS INFORMATION
REG LDO and VCC Power
The REG LDO supplies the power for the gate drivers and
output stages of CLK1, CLK2, TGBUF and BGBUF. Once the
SHDN pin is higher than 1.15V, REG will be regulated to
4V (typical), (REGSNS–IAMPN) voltage, or 5.25V (typi-
cal) from V
IN
, depending on whether (REGSNS–IAMPN)
is lower than 4V, or higher than 4V but lower than 5.25V,
or higher than 5.25V respectively, as shown in Figure11.
The REG pin must be bypassed to power ground with an
X5R or X7R ceramic capacitor of at least 4.7μF placed
close to the REG pin.
Current Sensing section, both the master LT8550’s
IAMPN and the slave LT8550’s IAMPN are connected to
the master LT8550’s local ground. Since the master’s
local ground and the primary controller’s local ground
may have small voltage difference, this can introduce a
small error. To minimize this error, the master LT8550
should be placed close to the primary controller.
REG LDO Current Limit and External Power PMOS
Selection
Overcurrent protection circuitry limits the maximum cur-
rent drawn from the REG LDO. When the VCC voltage is
below 3.3V during start-up or an overload condition, the
typical current limit is about 110mA.
When the REG voltage is higher than 3.55V, the current
limit depends on the VIN voltage as shown in Figure13.
If the VIN voltage is lower than 13.6V or higher than 30V,
the current limit is about 220mA or 100mA respectively.
If the VIN voltage is between 13.6V and 30V, the current
limit is inversely proportional to the VIN voltage to limit the
maximum power dissipation in the external power PMOS.
The power dissipation in the external PMOS can be cal-
culated by:
P=(VBIAS–REG) • ILDO
10nF
8550 F12
PRIMARY
CONTROLLER
LT8550
IAMPN
REGSNS
INTVCC
VIN
REGIS
REGDRV
REG
VCC
10Ω
CLP
+
–
+–
CF
CL
REGS_INT
CURRENT
LIMIT
*VBIAS
A5
1x
A6
RF
MP
*LOWER VOLTAGE (VBIAS) CAN BE USED FOR VIN PIN TO REDUCE THERMAL
STRESS INSTEAD OF USING THE SUPPLY FOR THE POWER STAGE
Figure12. REG LDO Configuration
(REGSNS – IAMPN) VOLTAGE (V)
0
REG VOLTAGE (V)
5
4
5.25
054
8550 F11
Figure11. REG Voltage vs REGSNS Voltage
VCC is the power supply for most of the internal circuitry
and it’s connected to REG through an external filter (RF,
CF) to filter the switching noise in REG, as shown in
Figure12, the filter should be placed close to the VCC pin,
typical value of RF=1Ω,CF=1μF is recommended. The
internal UVLO comparator disables the LT8550's switch-
ing activity when VCC is lower than 3.55V (typical).
Primary INTVCC Sensing
The primary controller gate driver’s power supply is
INTVCC, as shown in Figure12.
The primary INTVCC voltage is filtered and then sensed
by the differential unity gain amplifier A5 in Figure12,
and buffered to REGS_INT as the reference voltage of
the REG LDO.
Notice that the (–) of A5 is connected to IAMPN. As has
been discussed in the Primary Controller’s Inductor
LT8550
20
Rev. 0
For more information www.analog.com
Where VBIAS (VIN pin voltage) is the chip power supply
for the LT8550, ILDO is the current drawn from the REG
LDO for a specific application.
Use the following formula to calculate the junction tem-
perature of the PMOS and compare the calculated value
of T
J
to the manufacturer’s data sheets to help choose the
appropriate PMOS that will not overheat.
TJ=TA+P•RTH(JA) (1)
Where:
TJ is the junction temperature of the PMOS
TA is the ambient air temperature
P is the power dissipation of the PMOS.
RTH(JA) is the MOSFET’s thermal resistance from the
junction to the ambient air. Refer to the manufactur-
er’s data sheets.
To reduce the power dissipation in the external PMOS,
it’s helpful to power up the chip with a lower voltage aux
power supply (VBIAS) instead of sharing the same power
supply with the power stage, especially in a high input
voltage application. Large enough copper area on the PC
board is needed for the PMOS to alleviate thermal stress.
To ensure the loop stability, it’s also recommended to
choose a PMOS with Qg<40nC.
VIN (V)
0
MAXIMUM CURRENT (mA)
100
220
013.6
8550 F13
30
CONSTANT
POWER
SET TO 100 mA
Figure13. REG LDO Current Limit vs VBIAS Voltage
APPLICATIONS INFORMATION
Operating Frequency Selection
The expander system (primary controller and LT8550s)
adopts a constant frequency ranging from 100kHz to
1MHz determined by the master LT8550. The primary
controller and slave LT8550s are synchronized to the
master LT8550 by connecting the master LT8550’s CLK1
pin to their SYNC pins as shown in Figure1. To minimize
noise, it is recommended to add an RC filter between
master CLK1 and each primary’s or slave’s SYNC pin.
This RC filter should be close to SYNC pins with typical
value of R=10Ω, C=220pF.
The frequency can be set either by the internal oscillator,
or can be synchronized to an external clock source. A
trade-off between efficiency and component size exists in
selecting the switching frequency. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires more inductance and/or capacitance
to maintain low output ripple voltage. The switching fre-
quency can be set by placing an appropriate resistor from
the RT/MS pin to ground and tying the SYNC pin low or
high. The frequency can also be synchronized to an exter-
nal clock source driven into the SYNC pin. The following
sections provide more details.
Internal Oscillator
The free-running switching frequency of the master
LT8550 can be set using the internal oscillator by tying
a resistor from RT/MS pin to ground while the SYNC pin
is driven low (<0.8V) or high (>1.2V). The oscillator fre-
quency is calculated using the following formula:
fOSC =
25,000
R
T
+0.15 kHz
(2)
Where fOSC is in kHz and RT is in kΩ. Conversely, RT (in
kΩ) be calculated from the desired frequency (in kHz)
using:
RT=
25,000
f
OSC
kΩ– 0.15kΩ
(3)
LT8550
21
Rev. 0
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SYNC Pin and Clock Synchronization
The LT8550 has a phase-locked loop (PLL) to synchro-
nize the internal oscillator to the external clock signal.
The PLL is an edge sensitive digital type that provides
zero degree phase shift between the external clock and
internal oscillators.
To synchronize to an external clock source properly, the
frequency of the external clock source must meet two
criteria listed below:
1. The PLL is guaranteed to work properly only when the
frequency of the external clock source ranges from
125kHz to 1MHz.
2. The external clock can be synchronized to only when
it’s faster than the free-running frequency set by the
RT resistor. If the external clock is lower than fOSC, as
set by RT, the internal oscillator will oscillate at fOSC.
Primary Controller Gate Sensing Filters and Dividers
As has been discussed in the Operation section, the
primary controller’s top and bottom switch states are
detected by the master LT8550 gate sensing pins (i.e.
TGSR, TGSH, TGSL and BGSH). This sensed top gate
signal and bottom gate signal are buffered to the master
LT8550’s TGBUF and BGBUF respectively.
Since the primary controller’s SW node moves fast, an
RC filter RF, CF and bypass capacitor CH must be used,
as shown in Figure14 to avoid falsely sensing the pri-
mary controller’s top MOSFET’s state. Optional Schottky
clamps close to the TGSL pin of the LT8550 are recom-
mended to prevent the TGSL pin from ringing below
ground or exceeding the pin’s absolute maximum rating
if long traces are used to sense the top gate. Optional
filters are also recommended for both of the primary con-
troller’s bottom gate sensing and the slave LT8550s’ gate
sensing pins, as shown in Figure14. The time constant
of these filters should be less than 30ns, typical values of
RF=20Ω, C=1nF are recommended.
The LT8550 is recommended to work with a primary
controller which has gate driver rail lower than 5.5V. If
the primary has higher than 5.5V gate driver rail, resis-
tor dividers are required as shown in Figure15. Use the
APPLICATIONS INFORMATION
following equations to design the adequate divider and
filter for the gate sensing or refer to Table3 for the rec-
ommended values:
RFC1C2
C1+C2 ≤30ns
CFR5 R6
R5 +R6 ≤30ns
R2
R1+R2 =R4
R3 +R4 =R6
R5 +R6 =5.5V
Primary's VINTVCC
R1C1=R2 C2
CFCH
RF
OPTIONAL
VIN
8550 F14
PRIMARY
CONTROLLER
BST
TG
SW
BG
MASTER
LT8550
TGSR
TGSH
TGSL
BGSH
TGBUF
BGBUF
SLAVE
LT8550
REG
TGSR
TGSH
TGSL
BGSH
Figure14. Gate Sensing Configuration with Filters
and Schottky Clamps on TGSL
R4
R2
CH
R1
C2
C1
CF
R6
R5
R3
RF
OPTIONAL
8550 F15
PRIMARY
CONTROLLER
SW
BST
TG
BG
MASTER
LT8550
TGSL
TGSR
TGSH
BGSH
Figure15. Gate Sensing Configuration when Primary
Gate Driver Rail is Higher than 5.5V
LT8550
22
Rev. 0
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Table3. Recommended Values for Gate Sensing Filters
Primary’s
INTVCC
Voltage (V)
R1=R3=R5
(kΩ)
R2=R4=R6
(kΩ)
C1
(nF)
C2
(nF)
RF
(Ω)
6.0 4.7 47 10 1.0 22
6.5 10 33 3.3 1.0 27
7.0 10 22 2.2 1.0 30
7.5 10 15 1.0 0.68 47
8.0 10 15 1.0 0.68 47
9.0 10 13 1.0 0.68 47
9.5 9.1 13 1.0 0.68 47
10 10 10 1.0 1.0 43
In addition, R1–R6 should be in the range of kΩ or higher
to reduce the quiescent current. And, in order to sense the
primary top gate state correctly during the SW node tran-
sition, the C1 and C2 capacitance within 1nF to 100nF and
CH>4.7nF are recommended. These dividers and filters
should be close to the master LT8550 in the PCB layout.
Power Stage Components Selection Guideline
The power stage components include the input and output
capacitor, inductor, power N-channel MOSFETs and the
optional Schottky diode. Each LT8550’s expanded chan-
nel always adopts the exact same power stage compo-
nents as the primary controller. The following sections
offer a brief guideline for the power device selection. Refer
to the primary controller’s data sheet for more detailed
information.
Inductor Selection
For high efficiency, choose an inductor with low core loss,
such as ferrite. Also the inductor should have low DC
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
The inductor selection is interrelated with maximum aver-
age load current and inductor current ripple, which means
the inductor must have a rating greater than its peak oper-
ating current to prevent saturation and the inductance
must be large enough to decrease the current ripple so
that the maximum average current can be fed to the load
due to the limited peak inductor current.
APPLICATIONS INFORMATION
Power MOSFET, Schottky Diode(optional) Selection
and Efficiency Considerations.
Critical parameters for power MOSFET selection include
the on-resistance (RDS(ON)), Miller capacitance (CMILLER),
BVDSS (i.e. drain-source breakdown voltage) and maxi-
mum output current, all those parameters can be found
on the manufacture’s data sheet. The gate drive voltage
is set by the REG LDO (5V, typical value), consequently
logic level (5V) MOSFET must be used for the LT8550.
It’s very important to consider power dissipation when
selecting the power MOSFETs. The most efficient cir-
cuit will use MOSFETs that dissipate the least amount of
power. Power dissipation must be limited to avoid over-
heating that might damage the device. When the LT8550
operates in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Sync Switch Duty Cycle =VIN – VOUT
V
IN
The power dissipation of the main switch and the synchro-
nous switch at the maximum output current are given by:
PMAIN =VOUT
VIN
IMAX21+ δ
( )
RDS(ON)
+VIN2IMAX
2
⎛
⎝
⎜⎞
⎠
⎟RDR
( )
CMILLER
( )
•1
VREG – VTH(MIN)
+1
VTH(MIN)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎢ ⎥
⎥• fOSC
PSYNC =
V
IN
– V
OUT
V
IN
IMAX21+ δ
( )
RDS(ON)
Where δ is the temperature dependency of RDS(ON), RDR
is effective gate driver resistance at the MOSFET’s Miller
threshold voltage, V
TH(MIN)
is the typical MOSFET mini-
mum threshold voltage and fOSC is the switching frequency.
Both MOSFETs have I2R losses while the main switch
equation includes an additional term for transition
LT8550
23
Rev. 0
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losses, which dominates the power losses at high input
voltages. For VIN<20V, the high current efficiency gen-
erally improves with larger MOSFETs, while for VIN>20V
the transition losses rapidly increase to the point that
the use of a higher RDS(ON) device with lower Miller
capacitance provides higher efficiency. The synchronous
MOSFET losses are greatest at highest input voltage when
the duty cycle of the main switch is lowest. In this case,
it’s helpful to use two or more MOSFETs in parallel to
reduce the power dissipation on each device.
Based on the power dissipation, the MOSFET junction
temperature can be obtained using the formula (1) in
the REG LDO Current Limit and External Power PMOS
Selection section to pick an adequate MOSFET that will
not overheat.
An optional Schottky diode in parallel with the bottom
switch conducts during the dead time between the conduc-
tion of the main switch and the synchronous switch. This
prevents the body diode of the synchronous switch from
turning on, storing charge and requiring a reverse recovery
period that could cost as much as 3% in lower efficiency at
high VIN. Although improving the efficiency, the Schottky
diode also exhibits much higher reverse leakage current
than the silicon diode particularly at high temperature, the
combination of high reverse voltage and current can lead to
self-heating of the diode. Choose a package with lower ther-
mal resistance (θJA) to minimize self-heating of the diode.
CIN Capacitance
In continuous mode, the source current of the top
N-channel MOSFET is a square wave of duty cycle VOUT/
V
IN
. To prevent large voltage transients, a low ESR (equiv-
alent series resistance) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
CIN Required IRMS ≅
I
MAX
V
IN
VOUT
( )
VIN – VOUT
( )
⎡
⎣⎤
⎦
1/2
This formula has a maximum at VIN=2VOUT, where
IRMS=IO(MAX)/2. This simple worst-case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours of
APPLICATIONS INFORMATION
life, this makes it advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be used in parallel to
meet requirement. Typically multiple X5R or X7R ceramic
capacitors are put in parallel with either conductive-polymer
or aluminum-electrolytic types of bulk capacitors. Because
of its low ESR, the ceramic capacitors will take most of the
RMS ripple current. Vendors do not consistently specify the
ripple current rating for ceramics, but ceramics could also
fail due to excessive ripple current, consult the manufac-
turer if there is any question.
COUT Capacitance
The output capacitors need to have very low ESR to
reduce output voltage ripple. Multiple capacitors placed
in parallel may be needed to meet the ESR and RMS cur-
rent handling requirements. Dry tantalum, special poly-
mer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-driven
applications. Typically, once the ESR requirement for COUT
has met, the RMS current rating far exceeds the require-
ment. A minimum of 20μF/A of load capacitor is recom-
mended in most designs.
Topside MOSFET Driver Supply (CBX, DBX)
An external bootstrap capacitor, CBX, supplies the gate
driver voltage for the top switch. This capacitor is con-
nected between BSTx and SWx and is charged through
Schottky diode DBX from REG when the SWx pin is low.
When the top switch turns on, the SWx rises to power
VIN and the BSTx rises to VIN+REG. The boost capacitor
needs to store about 100 times the gate charge required
by the top switch. In most applications, a 0.1μF to 0.47μF,
X5R or X7R dielectric capacitor is adequate. The bypass
capacitance from REG to GND should be at least ten times
the bootstrap capacitor value. In addition, the reverse
breakdown of the Schottky diode must greater than the
maximum power VIN voltage.
LT8550
24
Rev. 0
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Inductor Current Sensing
The LT8550 can be configured to sense the inductor cur-
rent through either low value series current sensing resis-
tor (R
SENSE
) or inductor DC resistance (DCR). The choice
between the two current sensing schemes is largely a
design trade-off between cost, accuracy and power con-
sumption. DCR is becoming popular since it saves expen-
sive current sensing resistors and is more power efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller.
The ISPx/ISNx (i.e. ISP, ISP1/2/3/4, ISN, ISN1/2/3/4)
pins are the inputs to the current sense amplifiers. The
common mode input voltage range of the current sense
amplifier is from 0V to 80V. The current sense resistor
is normally placed at the output of the LT8550 in series
with the inductor.
Each ISNx pin draws 0µA to 100μA during normal oper-
ation. The ISPx pin current is less than 1µA. The high
impedance ISPx input to the current amplifier allows
accurate DCR current sensing.
Low Value Resistor Current Sensing: A typical RSENSE
inductor current sensing is shown in Figure16a. The
filter components (RF, CF) need to be placed near the
LT8550. RF values greater than 100Ω should be avoided
as this may increase offset voltage. The filter time con-
stant (RF•CF) should be no more than 30nS. The positive
and negative sense traces need to be routed as a differ-
ential pair close together and Kelvin (4-wire) connected
underneath the sense resistor as shown in Figure17.
RSENSE is chosen based on the maximum output current.
Given the maximum output current, IOUT(MAX), maximum
sense voltage, VSENSE(MAX), and maximum inductor ripple
current, ∆IL(MAX), the value of the RSENSE can be chosen
from the following formula if allowing a margin of 20%
for variations in the external component values:
RSENSE =0.8 • VSENSE MAX
( )
IOUT MAX
( )
+∆IL MAX
( )
/ 2
APPLICATIONS INFORMATION
TO SENSE FILTER
NEXT TO ISPx/ISNx
INDUCTOR OR RSENSE
VOUT
8550 F17
Figure17. Sense Lines Placement for DCR Sensing
or Resistor Sensing
DCR Inductor Current Sensing: For applications requir-
ing the highest possible efficiency, the LT8550 is capable
of sensing the voltage drop across the inductor DCR, as
shown in Figure16b. The DCR of the inductor represents
the small amount of DC winding resistance, which can be
less than 1mΩ for today’s low value, high current induc-
tors. In high current applications requiring such an induc-
tor, conduction loss through a sense resistor would cost
several points of efficiency compared to DCR sensing.
CF
RF
FILTER COMPONENTS
CLOSE TO THE ISPx/ISNx PINS
LRSENSE VOUT
TG
SW
BG
KELVIN SENSE
8550 F16a
ISPx
ISNx
MASTER
LT8550
a)
R2
R1
C
R2 AND C CLOSE TO THE ISPx/ISNx PINS
R1 CLOSE TO THE SW NODE
OPTIONAL
L DCR VOUT
TG
SW
BG
KELVIN SENSE
8550 F16b
ISPx
ISNx
MASTER
LT8550
b)
Figure16. Inductor Current Sense Filter
LT8550
25
Rev. 0
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The inductor DCR is sensed by connecting an RC filter
across the inductor. This filter typically consists of one
or two resistors (R1 and R2) and one capacitor (C). If
the external (R1||R2)•C time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across C will be:
VSENSE =IL• DCR
R2
R1+R2
Therefore, R2 may be used to scale the voltage across the
sense terminals when the DCR is greater than the target
sense resistance. With the ability to program the current
limit through ILIM pin, R2 may be optional. C is usually
selected in the range of 0.01μF to 0.47μF. This forces
R1||R2 to be around the kΩ range.
For DCR current sensing, the sense lines should also
run close together to a Kelvin connection underneath the
inductor as shown in Figure17. To prevent noise from
coupling into the sensitive small-signal nodes, resistor
R1 should be placed close to the inductor, while R2 and
C are placed close to the LT8550 as shown in Figure16b.
Thermal Shutdown
If the die junction temperature reaches approximately
165°C, the LT8550 will go into thermal shutdown. All the
power switches will be turned off. For a master LT8550,
the ENOUT pin will be pulled down to ground so that it
will shut down all the switching activity of the system. The
LT8550 will be re-enabled when the die temperature has
dropped by about 5°C (nominal).
Efficiency Considerations
The percent efficiency of LT8550 is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would lead to
the most improvement. Percentage efficiency can be
expressed as:
%Efficiency=100%–(L1+L2+L3+…)
Where L1, L2, etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
APPLICATIONS INFORMATION
the circuit produce power losses, several sources usually
account for most of the losses in LT8550 circuits:
1. I2R losses. I2R losses arise from the DC resistance
of the MOSFETs, inductor and current sense resistor.
It is the majority of power losses under high output
current conditions. In continuous mode, the aver-
age output current flows through the inductor and
RSENSE, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same R
DS(ON)
, then the resistance of one MOSFET can
simply be summed with the inductor’s DCR, RSENSE
and the board traces to obtain I2R losses.
2. Transition loss. This loss mostly arises from the brief
amount of time the top MOSFET spends in the satura-
tion (Miller) region during the switching node transi-
tions. It depends on the input voltage, load current,
driver strength and MOSFET capacitance. The transi-
tion can be significant at high input voltages or high
switching frequency.
3. REG current. This is the sum of MOSFETs driver
and REG control currents. The MOSFET driver cur-
rent results from switching the gate capacitance of
the power MOSFETs. Each time a MOSFET gate is
switched from low to high then to low again, a packet
of charge dQ moves from REG to ground. The result-
ing dQ/dt is a current out of REG that is typically much
larger than the control circuit current. In continuous
mode, IGATECHG=f•[QT+QB], where QT and QB are
the gate charges of the top and bottom MOSFETs.
As mentioned in the REG LDO and VCC Power Section,
powering the REG LDO with a lower power supply
voltage will not only improve efficiency, especially for
high input voltage application, but also alleviate the
thermal stress for the LDO’s P-channel MOSFET.
4. CIN loss. The input capacitor filters large square-wave
input currents drawn by the LT8550 into an averaged
DC current from the supply. The capacitor itself has
zero average DC current, but there is an AC current
flowing through it. Therefore, the input capacitor must
have a very low ESR to minimize the RMS current loss
due to ESR. It must also have sufficient capacitance
to filter out the AC component of the input current to
LT8550
26
Rev. 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure18. Recommended PC Board Design for a 9-Phase System
8550 F18
MN
MN
MN
MN
MN MN
MN MN
MN
MN
MN
MN
MN MN
MN
MN
PRIMARY
CONTROLLER
COUT
RSENSE
L
P
V
IN
GND
CIN
CH
V
OUT
CH1
CH2
CIN1
CIN2
L1
R
SENSE1
L2
RSENSE2
COUT1
COUT2
MASTER
LT8550
FIRST SLAVE
LT8550
CH5
CH6
CIN5
CIN6
CH3
CH4
CIN3
CIN4
RSENSE3
R
SENSE4
COUT3
COUT4
GNDGND
GND
GND
COUT5
COUT6
RSENSE5
R
SENSE6
L5
L3
L
4
L6
MN
MN
L7
L8
CH7
CH8
CIN7
CIN8
COUT7
COUT8
R
SENSE7
RSENSE8
MORE SLAVE LT8550s
CONNECTED VIA
prevent additional RMS losses in upstream cabling,
fuses or battery. The LT8550’s multi-phase architec-
ture can help reduce the ESR losses.
5. Body diode conduction loss. During the dead time,
the loss in the bottom MOSFET is IL•VF, where VF
is around 0.7V. At higher switching frequencies, the
dead time becomes a higher percentage of the switch-
ing cycle period and causes the efficiency to drop.
6. The VIN current is the DC supply current which flows
into the device from the VIN pin directly, and it is spec-
ified in the Electrical Characteristic table. VIN current
typically results in a small (<0.1%) loss.
Other hidden losses, such as copper trace, fuse and bat-
tery resistance, etc. can account for additional efficiency
degradation. It’s important to take them into consideration
during the system design phase.
LT8550
27
Rev. 0
For more information www.analog.com
Circuit Board Layout Checklist
One recommended PC board design for a 9 phase sys-
tem, primary controller and two LT8550s, is shown in
Figure18, the design can be expanded to more phases/
channels if needed. Use the following general checklist
to ensure the proper operation of the multiphase system:
• A multilayer PC board with dedicated ground planes
is generally preferred to reduce noise coupling and
improve heat sinking. The ground plane should be
immediately next to the routing layer for the compo-
nents (i.e. MOSFETs, inductors, sense resistors, input
and output capacitors etc.
• Keep small signal ground (SGND) and power ground
(PGND) separate. Only one connection point between
the SGND and PGND is required. It’s desirable to
return the SGND to a clean point on the PGND plane.
Do not return the small signal components grounds
to SGND through PGND. All power train components
should be referenced to PGND. Use immediate vias
to connect the power components to PGND. Several
vias are needed for each power component.
• Place power components, such as CIN, COUT, inductor
and MOSFET, in one compact area. Use wide but the
shortest possible traces for high current paths (e.g. VIN,
VOUT, PGND etc.) in this area to minimize copper loss.
• The BSTx/SWx nodes’ voltage swings with a high
dV/dt rate. These nodes are rich in high frequency
noise components, and they are strong sources of
EMI noise. To minimize the coupling between these
nodes and other noise-sensitive traces, the copper
area should be minimized. However, on the other
hand, to conduct high inductor current and provide
a heat sink to the power MOSFET, the SWx nodes
APPLICATIONS INFORMATION
PCB area cannot be too small. It’s usually preferred
to have a ground copper area placed underneath the
SWx nodes to provide additionalshielding.
In addition to BSTx/SWx, the TGx and BGx are also high
dV/dt signals, which must be routed away from the
noise-sensitive traces. It is also highly recommended
to use short and wide traces to route gate driver sig-
nals in order to minimize the impedance in gate driver
paths. The TGx and SWx should be routed together
with minimum loop area to minimize the inductance
and high dV/dt noise. Likewise, the BGx should be
routed close to a PGND trace, as shown in Figure19.
Try to route TGx, SWx, BGx traces on one layer only.
LT8550 BSTX
TGx
SWx
REG
BGx
+
–
+
–
REG
PGND PGND PLANE
MTOP
MBOT
VIN
8550 F19
Figure19. Gate Driver Routing Example
• Keep the high di/dt loop, which consists of the top
MOSFET, bottom MOSFET, and the ceramic capacitor
C
H
as shown in Figure20, as short as possible to
minimize the pulsating loop inductance and absorb
switchingnoise.
• The decoupling capacitors for REG, V
CC
, V
IN
and the
current sense, etc. should be placed close to their pins,
use PGND for the REG decoupling capacitor and SGND
for VIN and VCC decoupling capacitors. To minimize
the connection impedance, it’s desired to connect the
Figure20. Minimize the High di/dt Loop Area in PCB Layout
8550 F20
VIN
L
SW
L
MTOP
MBOT
CHSW
CIN
+
VIN
+
–
M
TOP
M
BOT
CH
PGND
PGND
MINIMIZE THIS
LOOP AREA
0.1µF TO 10µF X5R/X7R
CERAMIC CAPACITOR
a) High di/dt Loop b) Recommended Layout Example
LT8550
28
Rev. 0
For more information www.analog.com
decoupling capacitors directly to the pins without using
any via.
• Of all the small signal traces, current sensing traces
are most sensitive to noise. The current sensing
traces should be routed differentially with minimum
spacing to minimize the chance of picking-up noise,
as shown in Figure21. In addition, the filter resistors
and capacitors for current sensing traces should be
placed as close to the ISPx/ISNx pins as possible. If
the DCR sensing is used with an R/C network, the
APPLICATIONS INFORMATION
DCR sensing resistor R1 should be close to the induc-
tor, while R2 and C should be close to the IC.
Place the vias that connect the ISPx/ISNx lines directly
at the terminals of the current sensing resistors or the
inductors as shown in Figure21.
• When routing the interface signals between a mas-
ter LT8550, primary controller, and/or slave LT8550,
keep the small-signal lines far from the noisy lines
and shield these lines with a ground plane. A recom-
mended line arrangement is shown in Figure22.
Figure21. Current Sensing PCB Design
Figure22. Recommended Signal Lines Arrangement for PCB
8550 F21
VOUT
L
a) Resistor Sensing b) Inductor DCR Sensing
ISPx
ISNx
LT8550
C
DIRECT TRACE CONNECTION
DO NOT USE VIA
THIS VIA SHOULD NOT
TOUCH ANY OTHER
INTERNAL VOUT
COPPER PLANE
DIFFERENTIAL TRACE
VOUT
L
ISPx
ISNx
LT8550
R2
R1
C
DIRECT TRACE CONNECTION
DO NOT USE VIA
THIS VIA SHOULD NOT
TOUCH ANY OTHER
INTERNAL VOUT
COPPER PLANE
DIFFERENTIAL TRACE
SW
R
ALL LINES ARE SHIELDED
BY THE GROUND PLANE
ROUTE IN DIFFERENTIAL PAIR ROUTE IN DIFFERENTIAL PAIR
ALL LINES ARE SHIELDED
BY THE GROUND PLANE
GROUND PLANE GROUND PLANE
BST
TG
SW
BG
SYNC
SENSE+
SENSE–
INTVCC
RUN/ENABLE
PRIMARY
CONTROLLER
TGSR
TGSH
TGSL
BGSH
CLK1
ISP
ISN
REGSNS
ENOUT
MASTER
LT8550
INTERFACE
TGBUF
BGBUF
CLK2
CLK1
MODE
IAMPP
IAMPN
REGSNS
ENOUT
MASTER
LT8550
TGSH
BGSH
CLK2
SYNC
MODE
IAMPP
IAMPN
REGSNS
ENOUT
SLAVE
LT8550
INTERFACE
8550 F22
LT8550
29
Rev. 0
For more information www.analog.com
TYPICAL APPLICATIONS
Five Phase 6V/100A Step-Down Expander
VIN
REG
VIN
REG
VIN
REG
VIN
REG
VIN
REG
33nF
20Ω
8550 TA02
ISP
ISN
TG1
BST1
SW1
BG1
ISP1
ISN1
10Ω
1nF
+
CIN2
100µF
x2
CIN3
10µF
x4
CIN4
100µF
x2
CIN5
10µF
x4
CIN6
100µF
x2
CIN7
10µF
x4
CIN8
100µF
x2
CIN9
10µF
x4
COUT2
10µF
x2
COUT3
150µF
x3
COUT4
10µF
x2
COUT5
150µF
x3
COUT6
10µF
x2
COUT7
150µF
x3
COUT8
10µF
x2
COUT9
150µF
x3
10Ω
10Ω
33nF
220pF
62k
10Ω
0.22µF
1nF
SENSEN
SENSEP
HG
CBOOT
SW
LG
+
CIN0
100µF
x2
CIN1
10µF
x4
COUT0
10µF
x2
COUT1
150µF
x3
0.22µF
ENOUT CLK1 REGSNS TGSR TGSH TGSLBGSHVIN
SHDN
REGIS
REGDRV
CTRL1
VREF
CTRL2
VC
RT SS EN/UVLO SYNC VCC_INT GND
FB
VIN
200k 47k
10Ω
10nF 1nF
22µF 1nF
L1, 1.3µH 2mΩ
L0, 1.3µH 2mΩ
40.2k
10k100k
45.3k
10k
2.2µF
4.7nF
4.7µF
137k
1µF
680k
LT8550
LT3741
24k
4.7µF
1Ω
L0–L4: WURTH ELEKTRONIK 7443551130
M1–M10: INFINEON BSC093N04LSG
CIN0, CIN2, CIN4, CIN6, CIN8: PANASONIC EEHZAH101P
CIN1, CIN3, CIN5, CIN7, CIN9: TDK C3225X7R1H106M250AC
COUT0, COUT2, COUT4, COUT6, COUT8: PANASONIC 16TQC150MYF
COUT1, COUT3, COUT5, COUT7, COUT9: TDK C3216X7R1V106K160AC
VIN
12V TO 36V
M1
M2
M3
+
10Ω
0.22µF
1nF
L2, 1.3µH 2mΩ
M5
+
10Ω
0.22µF
1nF
L3, 1.3µH 2mΩ
M7
+
10Ω
0.22µF
1nF
L4, 1.3µH 2mΩ
M9
M4
M6
M8
M10
VOUT
6V/100A MAX
10µF
MP
TG2
BST2
SW2
BG2
ISP2
ISN2
TG3
BST3
SW3
BG3
ISP3
ISN3
TG3
BST4
SW4
BG4
ISP4
ISN4
REG
ILIM
PHS1
PHS2
PHS3
VCC
SYNC
RT/MS
IAMPP
IAMPN
CLK2
TGBUF
BGBUF
MODE
GND
REG
LT8550
30
Rev. 0
For more information www.analog.com
VIN
REG
VIN
REG
VIN
REG
INTVCC
VIN
REG
REG
REG
100k
330kHz
8550 TA03a
ISP
ISN
TG1
BST1
SW1
BG1
ISP1
ISN1
10Ω
1nF
+
+
10Ω
10Ω
1nF
10Ω
0.22µF
1nF
SENSE–
SENSE+
TG
BOOST
SW
BG
CIN0
22µF
×2
CIN1
150µF
CIN2
22µF
×2
CIN3
150µF
+
+
C
OUT1
330µF
x2
COUT0
22µF
x2
C
OUT3
330µF
x2
COUT2
47µF
x2
0.22µF
ENOUT CLK1 REGSNS TGSR TGSL TGSHVIN
SHDN
FREQ/PLLFILTER
ILIM
VIN
ITH
TK/SS RUN
MODE/
PLLIN INTVCC GND
FB
47k
0.1µF
330pF
22µF
L1 1.3µH
L0 1.3µH RS0
2mΩ
RS1
2mΩ
154k
48.7k
15k
2.2nF
4.7µF
10µF 1µF 1Ω
33k
BGSH
LT8550
LTC3851A-1
CH2 AND CH3
NOT SHOWN
12k
VIN
4.5V TO
32V
M0
M2
M1
×2
M3
×2
TG4
BST4
SW4
BG4
ISP4
ISN4
+
+
10Ω
0.22µF
1nF
CIN4
22µF
×2
CIN5
150µF
C
OUT5
330µF
x2
COUT4
22µF
x2
L4, 1.3µH RS4
2mΩ
M4
M5
×2
1nF
1k
10nF
4.7µF
MP
1nF33nF
20Ω
470pF
L1–L4: WURTH ELEKTRONIK 7443556130
M1–M6: INFINEON BSC093N04LSG
CIN0, CIN2, CIN4: TDK C4532X7R1E226M250KC
CIN1, CIN3, CIN5: PANASONIC EEUFC1V151
COUT0, COUT2, COUT4: TDK C3216JB1E476M160AC
COUT1, COUT3, COUT5: PANASONIC EEUFM1E331
R
S0
–R
S4
: PANASONIC ERJMP3PF2MOU
VOUT
3.3V/75A MAX
ILIM
PHS1
PHS2
PHS3
RT/MS
SYNC
MODE
TGBUF
BGBUF
CLK2
IAMPP
IAMPN
GND
REGIS
REGDRV
REG
VCC
REG
TYPICAL APPLICATIONS
Five Phase 3.3V/75A Step-Down Expander System
Start-Up Waveform with 10A Load
Transient Response with
20A to 70A Output Load Step
10ms/DIV
VOUT
2V/DIV
IL4
5A/DIV
IL2
5A/DIV
IL0
5A/DIV
8550 TA03b
400µs/DIV
IL4
10A/DIV
IL3
10A/DIV
IL2
10A/DIV
IL0
10A/DIV
8550 TA03c
LT8550
31
Rev. 0
For more information www.analog.com
TYPICAL APPLICATIONS
Five Phase 12V/70A Step-Down Expander System
VIN
REG
VIN
REG
VIN
REG
VIN
14V TO 56V
REG
REG
REG
124k
250kHz
10nF 1nF
10nF
INTVCC
D4
D1
LT8550
8550 TA04a
ISP
ISN
TG1
BST1
SW1
BG1
ISP1
ISN1
10Ω
1nF
+
10Ω
10Ω
100k
100k
100k
33nF
10Ω
0.22µF
1nF
SENSE–
SENSE+
ISMON
IVINMON
TG
BOOST
SW
BG
PWM_OUT
PWM
FAULT
FBIN
VREF
CIN0, CIN1
15µF
×2
CIN10
4.7µF
CIN2, CIN3
15µF
×2
CIN11
4.7µF
+
COUT5,6
150µF
x2
COUT0
22µF
COUT7,8
150µF
x2
VOUT
12V
70A MAX
COUT1
22µF
47pF
0.22µF
ENOUT CLK1 REGSNS TGSR TGSL TGSH BGSH
VIN
SHDN
SS EN/UVLO SYNC INTVCC GND
FB
47k 47k
IN4448HWT
10nF 22µF
L1 6.8µH
L0 6.8µH RS0
2.5mΩ
RS1
2.5mΩ
107k
909Ω
12.1k
10k
4.7nF 210k
2.2µF
10µF 2.2µF 1Ω
118k
LT3763
CH2 AND CH3
NOT SHOWN
13k
VIN 11.5V
M0, M1
M4, M5
M6, M7
M18, M19
M2,
M3
M6,
M7
TG4
BST4
SW4
BG4
ISP4
ISN4
+
10Ω
0.22µF
1nF
CIN8, CIN9
15µF
×2
CIN14
4.7µF
COUT13,14
150µF
x2
COUT4
22µF
L4 6.8µH RS4
2.5mΩ
M16,
M17
M18,
M19
2.2µF
1µF
MP
1nF
10nF
20Ω
100pF
L0–L4: COILCRAFT SER2915L-682KL
M0–M19: INFINEON BSC100N06LS3
MP: ZETEX ZXMP10A18G
CIN0–CIN9: MURATA KRM55WR72A156MH01K
CIN10–CIN14: MURATA GRJ32DC72A475KE11L
COUT0–COUT4: MURATA GRM32ER71C226MEA8L
COUT5–COUT14: PANASONIC 16SVP150M
RS0–RS4: PANASONIC ERJMP4PF2M5U
D0–D4: BAT46WJ
15k
150k
IVINN
IVINP
VIN
VC
470k
NTC
T
10Ω 10Ω
ILIM
PHS1
PHS2
PHS3
RT/MS
SYNC
MODE
TGBUF
BGBUF
CLK2
IAMPP
IAMPN
GND
REGIS
REGDRV
REG
VCC
REG
CTRL1
CTRL2
RT
D0
VIN
LT8550
32
Rev. 0
For more information www.analog.com
TYPICAL APPLICATIONS
Ten Phase Bidirectional Expander System Direction Change from Buck
to Boost (15A per Phase)
50ms/DIV
IL4
20A/DIV
IL3
20A/DIV
IL1
20A/DIV
BUCK
8550 TA04c
BUCK BOOST
VHIGH2
VHIGH
PGATE
POWER STAGE 1
REG
0Ω
VHIGH2
MP
REG
REG
REG
REG2
VHIGH4 POWER STAGE 1
PGATE
VHIGH4
MP
REG2
VHIGH
1µF COUT0
10µF
COUT4
100µF
COUT5
100µF
ISP
ISN
BST1
TG1
SW1
BG1
ISP1
ISN1
10Ω
1nF
2.2µF
×2
CIN1
33µF
1µF COUT2
10µF
COUT6
100µF
1µF COUT1
10µF
100pF
10Ω
0.22µF
1nF
CIN4
100µF
TG2
SW2
BG2
1nF
47k
ENOUT CLK1REGSNS TGSL TGSR TGSH BGSH
VIN
SHDN
REGIS
REGDRV
REG
VCC
ILIM
PHS1
PHS2
PHS3
SYNC
RT/MS
IAMPP
IAMPN
CLK2
RUN SYNC SGND PGND
VFBHIGH
47k 4.7k 4.7k
47k
4.7k
10nF
22Ω
10Ω
1nF
47k
4.7k
L3, 10µH 1mΩ
1mΩ
4.7µF
10µF
169k
LT8550
LTC3871-1
PINS FOR
POWER
STAGE2,3,4
10k
1Ω
4.7µF
205k
VHIGH
26V TO 58V
37.5A AT 48V
10nF
47k
0.33µF
499Ω
0.22µF
BST2 DRVCC
M4 ×2
M3 ×2 L2, 10µH
7.15k
2.2µF
×4
CIN0
33µF
×2
CIN3
100µF
×2
1µF
TG1
SW1
BG1
VFB
LOW
1mΩ
10k
0.33µF
499Ω
0.22µF
BST1 DRVCC
M2
×2
M1
×2 L1 10µH
7.15k
SNS2
SNSD2
EXTVCC
SNS1
SNSD1
TGBUF BGBUF MODE GND
PGATE
PGATE
VHIGH
V
HIGH1
5Ω
M9 ×2
215k
10k
603k
10k
OVHIGH
UVHIGH
ITHHIGH
ITHLOW
102k
10k
OVLOW
4.7µF
4.7µF
0.1µF
0.1µF
47pF
4.53k
10nF
3.01k
100pF
V5
DRVSET
10pF 35.7k IMON
FREQ
VLOW
SNSA2
SNSA1
392k 10k
M10 ×2
M5 ×2
M6 ×2
M12 ×2
M7 ×2
M8 ×2
DRVCC
SS
SETCUR
BUCK
SETCUR
BUCK
8550 TA05a
ISP
ISN
BST1
TG1
SW1
BG1
ISP1
ISN1
2.2µF
×2
CIN2
33µF
1µF COUT3
10µF
COUT7
100µF
100pF
10Ω
0.22µF
1nF
CIN5
100µF
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
ENOUT CLK1REGSNS TGSL TGSR TGSH BGSH
VIN
SHDN
REGIS
REGDRV
REG
VCC
ILIM
PHS1
PHS2
PHS3
SYNC
RT/MS
IAMPP
IAMPN
CLK2
L4, 10µH 1mΩ
4.7µF
10µF
169k
LT8550
PINS FOR
POWER
STAGE2,3,4
10k
1Ω
4.7µF
1nF
10Ω
VHIGH
TGBUF BGBUF
REG2
REG
REG2
REG2
V
HIGH
VLOW
12V
150A
90.9k
VHIGH5
PGATE
VHIGH
M13 ×2
VHIGH4
VHIGH5
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
VHIGH3
PGATE
VHIGH
M11 ×2
VHIGH3
VHIGH2
MODE GND
L1–L4: WURTH ELEKTRONIK 7443641000
M1–M8: VISHAY SQJA84EP
M9–M13: VISHAY SUD50P08
MP: ON FDMS86263P
CIN0–CIN2: PANASONIC EEE-FK1K330P
CIN3–CIN5: SUN 100CE100KXT
COUT0–COUT3:
MURATA GRM31CR71E106KA12L
COUT4–COUT7: PANASONIC EEHZA1E101XP
RS0–RS4: VISHAY WSL20101L000FEA18
LT8550
33
Rev. 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
7.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
0.40 ±0.10
5251
1
2
BOTTOM VIEW—EXPOSED PAD
TOP VIEW
SIDE VIEW
6.50 REF
(2 SIDES)
8.00 ±0.10
(2 SIDES)
5.50 REF
(2 SIDES)
0.75 ±0.05
0.75 ±0.05
R = 0.115
TYP
R = 0.10
TYP 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
6.45 ±0.10
5.41 ±0.10
0.00 – 0.05
(UKG52) QFN REV Ø 0306
5.50 REF
(2 SIDES)
5.41 ±0.05
6.45 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
6.10 ±0.05
7.50 ±0.05
6.50 REF
(2 SIDES) 7.10 ±0.05 8.50 ±0.05
0.25 ±0.05
0.50 BSC
PACKAGE OUTLINE
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
LT8550
34
Rev. 0
For more information www.analog.com
ANALOG DEVICES, INC. 2019
04/19
www.analog.com
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Five Phase 5V/100A Buck Phase Expander System
VIN
REG
10nF
1nF
VIN POWER STAGE 1
MP
REG
10Ω
10Ω
33nF
SENSE–
SENSE+
HG
CBOOT
SW
LG
100µF
×2
10µF
×4
+
+
150µF
×3
10µF
×2
VOUT
5V/100A
220nF
ENOUT CLK1 REGSNS TGSR TGSH BGSH TGSL
SS EN/UVLO SYNC VCC_INT GND
FB
47k
22µF
L0 1.3µH 2.5mΩ
38.3k
12.1k
10k
4.7nF
200k
LT3741 M1
M2
2.2µF
100k
VC
RHOT
45.3k
RNTC
470k
1Ω
CTRL1
VREF
CTRL2
VIN
RT
D0
ISP
ISN
10Ω
1nF
470pF
10Ω
220nF
1nF
POWER STAGE 2
POWER STAGE 3
POWER STAGE 4
VIN
L1
1.3µH 2.5mΩ
1µF
4.7µF
LT8550
PINS FOR
POWER
STAGE2,3,4
24.3k
62k
109k
1Ω
4.7µF
VIN
10V TO
36V
M3
M4
8550 TA06
100µF
×2
10µF
×4
+
150µF
×3
10µF
×2
+
REG
1µF
L0, L1: WURTH ELEKTRONIK 7443551300
M1–M4: INFINEON BSC093N04LSG
ISP1
ISN1
BST1
SW1
BG1
TG1
VCC
SYNC
PHS3
RT/MS
IAMPP
IAMPN
BGBUF
TGBUF
CLK2
GND
SHDN
REGIS
REGDRV
REG
PHS1
PHS2
ILIM