$= XILINX December 10, 1997(Version 1.1) XC1701L (3.3Vv), XC1701 (5.0V) and XC17512L (3.3v) Serial Configuration PROMs Features * On-chip address counter, incremented by each rising edge on the clock input + Simple interface to the FPGA; requires only one user VO pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Supports XC4000EX/XL fast configuration mode (15.0 MHz) Low-power CMOS Floating Gate process Available in 5 V and 3.3 V versions Available in compact plastic packages: 8-pin PDIP, 20-pin SOIC, and 20-pin PLCC. Programming support by leading programmer manufacturers. * Design support using the Xilinx Alliance and Foundation series software packages. Veco Vpp GND CE RESET/ OE or QE/ RESET Description The XC1701L, XC1701 and XC17512L serial configuration PROMs (SCPs) provide an easy-to-use, cost-effective method for storing Xilinx FPGA configuration bitstreams. When the FPGA is in master serial mode, it generates a configuration ciock that drives the SCP. A short access time after the rising clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock puises to complete the configuration. Once configured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the GE input of the following device. The clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foun- dation series development system compiles the FPGA design file into a standard Hex format, which is then trans- ferred to the programmer. CEO Address Counter CLK DATA X3185 Figure 1: Simplified Block Diagram (does not show programming circuit) December 10, 1997(Version 1.1) 5-1XC4701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs Pin Description DATA Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is heid at zero, and the DATA output is 3-stated. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer inter- face. This input pin is easily inverted using the Xilinx HW- 130 Programmer. Third-party programmers have different methods to invert this pin. CE When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-lec standby mode. CEO Chip-Enable output, to be connected to the CE input of the next SCP in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other worcis: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. Vpp Programming voltage. No overshoot above the specified max vaitage is permitted on this pin. For normal read oper- ation, this pin must be connected to Voc. Failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. Do not leave VPP floating! Vec and GND Positive supply and ground pins. Serial PROM Pinouts : | g.Pin | 7 oe DATA t t 2 CLK 2 [ 3 | 4 RESET/OE (OE/RESET) 3 as | 6 Ce 4 10 8 iGNO ~ ~ 5 11 10 CEO 6 13 14 Vep 7 18 17 [Voc _ 8 28 2 Capacity Device Configuration Bits XC1701L 1,048,576 xC1701 1,048,576 : (XC17842L 524,288 | Number of Configuration Bits, Including Header for all Xilinx FPGAs and Compatible SCP Type | Device Contiguration Bits SPROM | XC4010XL 283,424 XC17512L XC4013XL 393,623 XC17512L 1 XC4020E 329,312 xC1701. XC4020XL 521,880 XC17512L XC4025E 422,176 XC1701 [ XC4028XL 668,184 XC1701L XC4028EX 668,184 XC1701~ XCa0a6EX | S*iaS2W~SC<CS~SKINC* XG4036XL 832,528 XCiI701L_ XC4044XL 1,014,928 XCI701L | ~~ X%C4052XL 1,215,368 XC1701L + L. XC17256L XC4062XL 1,433,864 XC1701L + Po _ XC17512L | _ XC4085XL 1,924,992 2xXCi70iL | 5-2 December 10, 1997(Version 1.1)Controlling Serial PROMs Most connections between the FPGA device and the Serial PROM are simple and self-explanatory. * The DATA output(s) of the of the Serial PROM(s) drives the DIN input of the lead FPGA device. * The master FPGA CCLK output drives the CLK input(s) of the Serial PROM(s). * The CEO output of a Serial PROM drives the CE input of the next Serial PROM in a daisy chain (if any). The RESET/OE input of all Serial PROMs is best driven by the INIT output of the XC3000 or XC4000 tead FPGA device. This connection assures that the Serial PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a Veg glitch. Other methods such as driving RESET/OE from CDC or system reset ~ assume that the Serial PROM internal power-on-reset is always in step with the FPGAs internal power-on-reset, which may not be a safe assumption. * The CE input of the lead (or only) Serial PROM is driven by the DONE/PRGM or DONE output of the lead FPGA device, provided that DONE/PRGM is not permanently grounded. Otherwise, CDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanenily tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. FPGA Master Serial Mode Summary The V/O and logic functions of the Logic Cell Array and their associated interconnections are established by a configu- ration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA automatically loads the configuration program from an external memory. The Serial Configuration PROM has been designed for compatibility with the Master Serial Mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial Mode whenever ail three of the FPGA mode- select pins are Low (M0=0, M1=0, M2=0). Data is read from the Serial Configuration PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during con- figuration. Master Serial Mode provides a simple configuration inter- face. Only a serial data line and two contro! lines are required to configure an FPGA. Data from the Serial Con- figuration PROM is read sequentially, accessed via the $< XILINX internal address and bit counters which are incremented on every valid rising edge of CCLK. if the user-programmable, duai-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The XC3000 and XC4000 families take care of this automatically with an on- chip default pull-up resistor. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a Serial Configuration PROM, the GE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the D/P fine is pulled Low and configuration begins at the last vaiue of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the Serial PROM does not reset its address counter, since it never saw a High level on its OE input. The new configura- tion, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK puises, up to 16 million (24) and D/P goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Serial Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cas- caded SCPs provide additional memory. After the last bit from the first SCP is read, the next clack signal to the SCP asserts its CEO output Low and disables its DATA line. The second SCP recognizes the Low level on its CE input and enabies its DATA output. See Figure 2. After configuration is complete, the address counters of all cascaded SCPs are reset if the FPGA RESET pin goes Low, assuming the SCP reset polarity option has been inverted. To reprogram the FPGA with another program, the D/P line goes Low and configuration begins where the address counters had stopped. in this case, avoid contention between DATA and the configured I/O use of DIN. December 10, 1997(Version 1.1) 5-3XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMS * lf Readback is Activated, a . Pal Vee 3.3-kQ Resistor is + | |] 4 Required in MO M1 PWRDWN Series With M1 During Configuration 7 ( dour the 3.3 kQ M2 Pull-Down 1 M2 OPTIONAL Resistor Overcomes the Daisy-chained Internal Pull-Up, HDe FPGAs with but it Allows M2 to d LDC - Different be User /0. General- Configurations Purpose < 0o INIT UserVO | ___| Pins . 3] | Other s| | VO Pins OPTIONAL FPGA y __ Slave FPGAs with Identical Configurations Vee RESETo| RESET | peewee nee nee 5 Voc pp i i DIN DATA , DATA i CCLK CLK L__.icik Cascaded | _ ScP i Serial | D/P |} cE CEObp<! CE Memory | init OE/RESET | OB/RESET | Looe and (Low Resets the Address Pointer) CCLK (OUTPUT) P\ Sf \ on KX y em x X X sot Figure 2: Master Serial Mode. The one-time-programmabie Serial Configuration PROM supports automatic loading of configuration programs. Multiple devices can be cascaded to support additional FPGA. An early D/P inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. 5-4 December 10, 1997(Version 1.1)Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high imped- ance state regardless of the state of the OE input. Table 1: Truth Table for XC1700 Control Inputs $= XILINX Programming The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Control inputs Outputs Internal Address RESET CE DATA CEO lee tnactive Low if address < TC: increment active High active if address > TC: dont change 3-state Low reduced Active Low Held reset 3-state High active Inactive High Not changing 3-state High standby Active High Held reset 3-state High standby Notes: |. The XC1700 RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC+1 = address 0. IMPORTANT: Always tie the Vpp pin to Vcc in your application. Never leave Vpp floating. December 10, 1997(Version 1.1) 5-5XC17011. (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs XC1701 Absolute Maximum Ratings Symbol Description Units Veco Supply valtage relative to GND -0.5 to +7.0 Vv Vpp Supply voltage relative to GND -0.5 to +12.5 Vv VIN Input voltage relative to GND -0.5 to Veco +0.5 Vv Vrs Voltage applied to 3-state output -0.5 to Voc +0.5 V Tste@ Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol Description Min Max Units Voc Commercial Supply voltage relative to GND 0C to +70C junction 4.75 5.25 Vv Industrial Supply voitage relative to GND -40C to +85C junction 4.50 5.50 Vv Military Supply voitage relative to GND -55C to +125C case 4.50 5.50 Vv DC Characteristics Over Operating Condition Symbol! Description Min Max Units Vin High-level input voltage 2.0 Veco Vv Vit Low-level input voltage 0 0.8 Vv Vox High-level output voltage (igy = -4 mA) Commercial 3.86 Vv Voi Low-level output voltage (lo, = +4 MA) 0.32 V Vou High-level output voltage (Io4 = -4 MA) industrial 3.76 Vv Voi Low-level output voltage (ig, = +4 MA) 0.37 Vv leca Supply current, active mode 10.0 mA lees Supply current, standby mode 50.0 HA i Input or output leakage current -10.0 10.0 pA Note: During normal read operation Vpp must be connected to Voc December 10, 1997(Version 1.1)$= XILINX XC1701L/XC17512L Absolute Maximum Ratings Symbol Description Units Veco Supply voltage relative to GND -0.5 to +6.0 Vv Vep Supply voltage relative to GND -0.5 to +12.5 Vv VIN Input voltage with respect to GND -0.5 to Vee +0.5 Vv Vrs Voltage applied to 3-state output -0.5 to Veg +0.5 V Tsta Storage temperature (ambient) -65 to +150 C Tso Maximum soldering temperature (10 $ @ 1/16 in.) +260 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliabitity. Operating Conditions Symbol Description Min Max Units Voc Commercial Supply voitage relative to GND 0C to +70C junction 3.0 3.6 Vv DC Characteristics Over Operating Condition Symbol Description Min Max Units Vin High-ievel input voltage 2.0 Voc v Vit Low-level input voltage 0 0.8 Vv Vou High-jevel output voltage (Igy = -4 MA) 2.4 V Vor Low-level output voltage (lq_ = +4 mA) 0.4 Vv loca Supply current, active mode 5.0 mA lecs Supply current, standby mode 50.0 HA IL Input or output leakage current -16.0 10.0 pA Note: During normal read operation Vpp must be connected to Voc, December 10, 1997(Version 1.1) 5-7XCI7O1L (3.3V}, XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs AC Characteristics Over Operating Condition ce \ h+ @ Tsce > RESET/OE K L at (41) THoe F ie Onc Tove CLK @ / @ | , - - @ | Teac fe | Tow e- * or CE o_O x KY ~ i @Ton X2634 XC1701L. Description C1701 XC17512L. Min Max Min Max to Data 30 to 45 60 to 45 60 or to 50 50 1 2 3 4 5 6 7 8 wo to guarantee 10 to (to guarantee proper 11 counters are Notes: 1. AC test load = 50 pF 2. Float delays are measured with minimum tester ac load and maximum dc toad. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V;, = 0.0 V and Viq = 3.0 V. 5-8 December 10, 1997(Version 1.1)$< XILINX AC Characteristics Over Operating Condition (continued) RESET/OE fo \_ CLK / (\ | G2) Teor 4 : DATA Last Bit First Bit Xt, et (Toc > CEO ' G4) Toce +! XC1701L Symbol Description xe1701 %C17512L Units Min Max Min Max 12. |Tepr CLK to Data Float Delay? 50 50 ns 13 [Tock CLK to CEO Delay 30 30 ns 14 |Toce CE to CEO Delay 35 35 ns 15 [Toor RESET/OE to CEO Delay 30 30 ns Notes: 1. AC test load = 50 pF 2. Float delays are rneasured with minimum tester ac load and maximum de load. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with V\_ = 0.0 V and Vj, = 3.0 V. December 10, 1997(Version 1.1) 5-9XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMS Ordering Information XC1701L - PC20 C Device Number -_______ Operating Range/Processing XC1701L = Commercial (0 to +70C) XC1701 r = Industrial (40 to +85C XC17512L Package Type PDS = 8-Pin Plastic DIP $020 = 20-Pin Plastic Smaii-Outline Package PC20 = 20-Pin Plastic Leaded Chip Carrier Marking Information Due to the smail size of the serial PROM package, the complete ordering part number cannot be marked on the package. The XC prefix is deletec! and the package code is simplified. Device marking is as follows. 1701L P Cc = Device Number ~ | Operating Range/Processing XC1701L = Commercial (0 to +70C) XC1701 Package Type r = Industriat (~40 to +85C) xC17512L 8-Pin Plastic DIP J 20-Pin Plastic Smail-Outline Package 20-Pin Plastic Leaded Chip Carrier 5-10 December 10, 1997(Version 1.1)