MS1003 PLESSEY Semiconductors MS1003 910 ELEMENT CCD ANALOGUE STORE The Plessey MS1003 is a clock controlled analogue shift register for applications including time delay, v Ww compression/expansion and temporary storage of analogue whe ref] voo or digital signals. Information is transferred through the nc(]2 18] Voo device by two externally supplied clocks; the timing between wes aD] vo the clocks is not critical. A soft line clamp facility is available so that the input can be referenced to a desired voltage level. vs wsioo3 sp Ne internal thermal compensation circuits correct for any driftin Vow [Is Pac CCD bias over a wide range of temperature. The device is available in two grades as follows: ve Os wfnc re 003-4 selected for analogue storage with interrupted oc? 0101 clocks. MS1003-3 selected for delay line operation with vss Qe spor DC16 continuous clocks. FEATURES Fig.1 Pin connections - top view HH Typically 5MHz Video Bandwidth With A Clock Frequency of 14.3MHz " quency PIN NAMES HM 15V Supply Operation Hi einternal Thermal Compensation To Correct For Ves | Substrate Bias Any Drifts in CCD Input Bias Vi Analogue input @ Soft Line Clamp Facility Veret Clamp Reference Bias Vic Thermal Compensation Bias APPLICATIONS bc Clamp Pulse Hi sElectrically Variable Analogue Delay Voo | Drain Supply W@ Line Store: Full NTSC TV Line Can Be Stored Vo Analogue Output With A Clock Frequency (14.3MHz) Of Four NC | Not Connected Times The Colour Subcarrier Frequency v1 Clock 1 @ Time Base Correction be Clock 2 Time Compression/Expansion Vss_| Ground Voo Vop 2 16 15 9 come Oo 9 EE 4 ! | | | GENERATORS | | oo 7 | | | | CLAMP + BUFFER + | Yew aot] INPUT BIAS INPUT SHIET ABGISTER ouffur sauets [on wide | ] | | | | | INPUT CLOCK OUTPUT CLOCK | GENERATOR GENERATOR | | TC | | {er | | Lp SS 6 o- 4 Veo n vee Fig.2 Block diagram 87MS1003 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated): Vers = 4V, Oc = Mc, Voo = 15V, Ves -5V, OL = O0.8V, OH 12.5V, f = 13.3MHz, fsig = 1kHz, T = 25C Characteristic Symbol Min. We. Max. Units Notes Supply current top 12 16 mA | O1 = OHo2 = OL Substrate current les 10 20 uA Gain G -2 0 +2 dB } Vin = 100mV pk/pk Differential gain AG 3 % Vin = 1V pk/pk Bandwidth BW 45 5 MHz | Vin = 1V pk/pk Random noise RN 0.8 mV | Bandwidth = 4.5MHz Spatial noise (1) SN 25 mV | Hold time = 1ms %:1 = O.,62 = 6H Rate of output signal offset (1) RSO 3 mV/ms| 61 = O12 = On Output droop rate (1) VAT 4 8 V/s | O1 = O.2 = OH Signal input leakage ha 0.1 nA Signal input capacitance Cn 4 7 pF Output resistance Ro 0.4 1 kQ Clock capacitance Phase/phase 1/2 Co! 75 100 pF Phase/gnd Co 60 80 pF | bd: and 2 Clamp capacitance Coc 2 7 pF T = +70C Spatial noise (1) SN 50 mV | Hold time = 1ms 1 = 1,02 = on Rate of output signal offset (1) RSO 70 mV/ms}] Pi = @Ld2 = OH Output droop rate (1) Vo/T 200 WS [1 = O12 = oH Signal! input leakage tin 100 nA NOTE (1) applies to MS1002-1 only RECOMMENDED OPERATING CONDITIONS Condition Symbol! Value Units Notes Min. Max Supply voltage - positive Voo 14.5 155 Vv Substrate bias supply Ves 4 -4 Vv Clock low oe -1 0.8 V | All clock inputs Clock high Ou 125 Voo V_] All clock inputs Clamp low Por -1 08 Vv Clamp high cH 11.0 Vop Vv Input bias range Veias 3.5 45 Vs | Vin = 100mV pk/pk Clock frequency fb - 25 MHz Output load Resistance Ri 10 - kQ Capacitance Ch - 15 pF Ambient operating temperature T 0 70 C ABSOLUTE MAXIMUM RATINGS Storage temperature Ambient operating temperature 65C to +100C oOC to +70C Max.positive supply voltage (Vpo) +19V Min.negative supply voltage (Vse) -6V Max.voltage on any pin (except Vop , Vas) Vop Min.voltage on any pin (except Von , Vee) Vee -0.3V All voltages with respect to Vss (Ground) 88PRECAUTIONS This device has limited immunity to static electricity when handled. The conductive foam or plastic carrier provided should be retained until the device is incorporated in its circuit. Any handling of the device without its plastic carrier should be minimised. Care should be taken to avoid any static discharges occurring in the circuit before completion and soldering should be carried out with an earthed bit. Care should also be taken to avoid voltage transients in the supply leads. These can occur when the supplies are switched on or off. The track length from the clock drivers to the CCD store should be minimised to prevent overshoots on the clock waveforms. It is permissible to allow these overshoots to exceed the minimum and maximum clock voltage specifications by up to 2V for not longer than 10ns duration per clock transition. GENERAL OPERATION The circuit operates as a sampled shift register under the control of the external clocks 1 and 2, Analogue input signals are sampled on the falling edge of the $: clock and are subsequently stored and shifted through the device to appear at the output after 909 complete clock cycles (see timing diagram in Fig.3 for exact delay information). Each output sample is presented on the falling edge of 1 and exists for an entire clock period. The output waveform consists of the delayed and/or stored analogue information plus components of the inverse 1 clock due to breakthrough from internal sample and hoid circuits. Connections for two- phase operation are shown in Fig.4. If the soft line clamp facility is not desired, it may be disabled by connecting dc to Vss. In this case, to maintain correct input biassing, the wiper MS$1003 of Rv should be connected to pin 4 instead, via a resistor, as shown in Fig.5. The device exhibits signal inversion. Delay mode Incoming signals are applied to the terminal Vi via a coupling capacitor (Fig.4). It is necessary for the user to ensure that the incoming analogue signal contains no frequency components in excess of fo + 2 in order to avoid spurious components, due to aliassing, appearing at the output. The output waveform is available directly from the device, or may be taken via a suitable buffer circuit if a lower output impedance is required. Analogue information appears at the output terminat delayed in time by 910 clock cycles. The frequency response characteristics of the device are related to the clock frequency, f as shown in Fig.6. The clock frequency is variable over a wide range. At high frequencies ( > 25MHz) the bandwidth of the device becomes limited owing to the decreasing efficiency of the charge coupled shift register. At low frequencies (< 100kHz) the signal range is diminished because of the generation of thermal charge in the shift register; hence the minimum clock frequency is related to the maximum operating temperature (the 100kHz figure corresponding to 70C operation). The device should be located away from circuit components which dissipate power and should be provided with the coolest ambient offered by the system. Heat dissipation from the analogue store itself may be assisted by soldering uncommitted pins to an earth plane. At low frequencies the effects of thermally generated currents can be minimised by using clocks having a short 1 on-duration (ta = 100ns). This approach also simplifies the filtering of clock noise from the output. A 100nF decoupling capacitor on pin 6 may be necessary in some applications. 2 o1 Ds D1 Dz v VS \ Mean uncascaded delay 909.5 7 as I\ AY IN SAMPLE & HOLD CLOCK BREAKTHROUGH Delay of N cascaded lines = 909.57 + (N - 1)9107 t = 9097 t = 9107 [| ts h Oo | tr D2 Ds VALID Crossover points of clocks nominally 50 %; exact timing relationship is non-critical providing: Minimum time, t2, when 1 is low and $2 is high, and Minimum time, t4 when $1 is high and 2 is low = 15ns Minimum ty, ta =10ns Maximum ti, ts = 100ns Fig.3 Timing diagram 89MS1003 Time compression/expansion Compression or expansion of analogue signals in the time domain may be achieved by loading and unloading the shift register at different frequencies. The tow frequency limit for this mode of operation is dictated by the rate of average signal offset (RSO) as this will reduce the maximum output signal amplitude. Analogue storage When the shift register has been loaded with analogue signals, the clocks may be interrupted to achieve temporary storage of the information. The samples are retrieved when the clocks are subsequently re-started. The clocks must be stopped in the state @:1 = 1 in order to minimise degradation of the signal due to thermal leakage currents. The maximum hold time is determined by the spatial noise parameter (SN). Spatial noise magnitude is a function of stop clock period and of operating temperature as shown in Fig.7. MS1003-1 devices are tested in the stopped clock mode and spatial noise parameters guaranteed for this type of operation. Component values Co Output Capacitor, 1.0uF Ci Input Capacitor, 0.1yF Ri Input Resistor, 47kQ Rv Variable Resistor, 200kQ Ri Fixed Resistor, 820kQ Re Load Resistor, 10kQ (including measuring Cu Load Capacitor, 15pF kit impedance) Co Decoupling Capacitors, 10nF Voo MS1003 co 15 Co pas 131 4 t ourPuT ql H ij Ri Fig.4 Circuit connections (utilising line clamp) MS1003 13[] Cp 8 ra Go ouTPUT wt} JI 28 t co ef Ae Loao of Test 10[ - #4 s[}- %2 Fig.5 Circuit connections (line clamp disabled) 90SIGNAL BANDWIDTH (BW) MHz 0 5 10 15 20 25 30 35 CLOCK FREQUENCY, fp MHz Fig.6 Typical bandwidth AMBIENT TEMPERATURE TC 1000 7 C Ea. e A 4 z Lo > = ) JY = w y 3 3 2 f z / < 10 7 v4 7 4 7 / | 7 7 / 7 7 Y 7 7 f 7 7 at Z Z Z 0.01 01 1 10 100 CLOCK HOLD TIME, ms Fig.7 Typical output spatial noise as a function of clock hold time and operating temperature MS1003 91