 
  
DAC8822
FEATURES DESCRIPTION
APPLICATIONS
I A
OUT
AGNDA
R A
1
R A
1
DACA
I B
OUT
AGNDB
DACB
DACA
Register
DACB
Register
DGND
D0
D15
WR
A0
A1
RS
LDAC
RSTSEL
VDD R A
COM V A
REF
R A
OFS R A
FB
R A
FB
R A
OFS
R B
1R B
2R B
OFS R B
FB
R B
FB
R B
OFS
V B
REF
R B
COM
R B
1
InputA
Register
Parallel
Bus
Interface
Control
Logic
InputB
Register
R A
2
Power-On
Reset
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
16-Bit, Dual, Parallel Input, MultiplyingDigital-to-Analog Converter
• ± 0.5LSB DNL
The DAC8822 dual, multiplying digital-to-analogconverter (DAC) is designed to operate from a single• ± 1LSB INL
2.7V to 5.5V supply.•Low Noise: 12nV/ √Hz
The applied external reference input voltage V
REF•Low Power Operation:
determines the full-scale output current. An internalI
DD
= 1 µA per Channel at 2.7V
feedback resistor (R
FB
) provides temperature•2mA Full-Scale Current, with V
REF
= 10V
tracking for the full-scale output when combined with•Settling Time: 0.5 µs
an external, current-to-voltage (I/V) precisionamplifier.•16-Bit Monotonic
•4-Quadrant Multiplying Reference Inputs
A RSTSEL pin allows system reset assertion ( RS) toforce all registers to zero code when RSTSEL = '0',•Reference Bandwidth: 10MHz
or to midscale code when RSTSEL = '1'. Additionally,•Reference Input: ±18V
an internal power-on reset forces all registers to zero•Reference Dynamics: –105 THD
or midscale code at power-up, depending on thestate of the RSTSEL pin.•Midscale or Zero Scale Reset•Analog Power Supply: +2.7V to +5.5V
A parallel interface offers high-speedcommunications. The DAC8822 is packaged in a•TSSOP-38 Package
space-saving TSSOP-38 package and has an•Industry-Standard Pin Configuration
industry-standard pinout. The device is specified•Pin-Compatible with the 14-Bit DAC8805
from –40 °C to +125 °C.•Temperature Range: –40 °C to +125 °C
For a 14-bit, pin-compatible version, see theDAC8805 .
•Automatic Test Equipment•Instrumentation
•Digitally Controlled Calibration•Industrial Control PLCs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
RELATIVE DIFFERENTIAL SPECIFIEDACCURACY NONLINEARITY PACKAGE-LEAD TEMPERATURE PACKAGEPRODUCT (LSB) (LSB) (DESIGNATOR) RANGE MARKING
TSSOP-38DAC8822QB ±2±1 –40 °C to +125 °C DAC8822(DBT)
TSSOP-38DAC8822QC ±1±1 –40 °C to +125 °C DAC8822(DBT)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
over operating free-air temperature range (unless otherwise noted)
(1)
DAC8822 UNIT
V
DD
to GND –0.3 to +7 VDigital input voltage to GND –0.3 to +V
DD
+ 0.3 VV (I
OUT
) to GND –0.3 to +V
DD
+ 0.3 VREF, R
OFS
, R
FB
, R
1
, R
COM
to AGND, DGND ±25 VOperating temperature range –40 to +125 °CStorage temperature range –65 to +150 °CJunction temperature range (T
J
max) +150 °CPower dissipation (T
J
max – T
A
) / R
θJA
WThermal impedance, R
θJA
53 °C/WHuman Body Model (HBM) 4000 VESD rating
Charged Device Model (CDM) 500 V
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
2
Submit Documentation Feedback
www.ti.com
ELECTRICAL CHARACTERISTICS
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
All specifications at T
A
= –40 °C to +125°C, V
DD
= +2.7V to +5.5V, I
OUT
= virtual GND, GND = 0V, and V
REF
= 10V, unless otherwise noted.
DAC8822
PARAMETER CONDITIONS MIN TYP MAX UNITS
STATIC PERFORMANCE
Resolution 16 Bits
DAC8822QB ±2 LSBRelative accuracy INL
DAC8822QC ±1 LSB
Differential nonlinearity DNL ±0.5 ±1 LSB
Output leakage current Data = 0000h, T
A
= +25 °C 10 nA
Output leakage current Data = 0000h, Full temperature range 20 nA
Unipolar, data = FFFFh ±1±4 mVFull-scale gain error
Bipolar, data = FFFFh ±1±4 mV
Full-scale temperature coefficient ±1±2 ppm/ °C
T
A
= +25 °C±1±3 mVBipolar zero error
Full temperature range ±1±3 mV
Power-supply rejection ratio PSRR V
DD
= 5V ±10% ±0.2 ±1.0 LSB/V
OUTPUT CHARACTERISTICS
(1)
Output current 2 mA
Output capacitance Code dependent 50 pF
REFERENCE INPUT
Reference voltage range V
REF
–18 18 V
Input resistance (unipolar) R
REF
4 5 6 k Ω
Input capacitance 5 pF
R
1
, R
2
4 5 6 k Ω
Feedback and offset resistance R
OFS
, R
FB
8 10 12 k Ω
LOGIC INPUTS AND OUTPUT
(1)
V
IL
V
DD
= +2.7V 0.6 VInput low voltage
V
IL
V
DD
= +5V 0.8 V
V
IH
V
DD
= +2.7V 2.1 VInput high voltage
V
IH
V
DD
= +5V 2.4 V
Input leakage current I
IL
0.001 1 µA
Input capacitance C
IL
8 pF
POWER REQUIREMENTS
Supply voltage V
DD
2.7 5.5 V
Normal operation, logic inputs = 0V 3 6 µA
Supply current I
DD
V
DD
= +4.5V to +5.5V, V
IH
= V
DD
and V
IL
= GND 3 6 µA
V
DD
= +2.7V to +3.6V, V
IH
= V
DD
and V
IL
= GND 1 3 µA
AC CHARACTERISTICS
(1) (2)
To 0.0015% of full-scale,Output current settling time t
S
0.5 µsdata = 0000h to FFFFh to 0000h
Reference multiplying BW BW – 3dB V
REF
= 5V
PP
, data = FFFFh, 2-quadrant mode 10 MHz
V
REF
= 0V to 10V,DAC glitch impulse 5 nV–sdata = 7FFFh to 8000h to 7FFFh
Data = 0000h, V
REF
= 100kHz, ±10V
PP
,Feedthrough error V
OUT
/V
REF
–70 dB2-quadrant mode
Crosstalk error V
OUT
A/V
REF
B Data = 0000h, V
REF
B = 100mV
RMS
, f = 100kHz –100 dB
LDAC = logic low, V
REF
= –10V to + 10VDigital feedthrough 1 nV–sAny code change
Total harmonic distortion THD V
REF
= 6V
RMS
, data = FFFFh, f = 1kHz –105 dB
Output noise density e
N
f = 1kHz, BW = 1Hz, 2-quadrant mode 12 nV/ √Hz
(1) Specified by design and characterization; not production tested.(2) All ac characteristic tests are performed in a closed-loop system using a THS4011 I-to-V converter amplifier.
3Submit Documentation Feedback
www.ti.com
PIN ASSIGNMENTS
D1
D0
ROFSA
RFBA
R A
1
RCOMA
VREFA
IOUTA
AGNDA
DGND
AGNDB
I B
OUT
V B
REF
R B
COM
R B
1
R B
FB
R B
OFS
WR
A0
D2
D3
D4
D5
D6
D7
D8
D9
D10
VDD
D11
D12
D13
D14
D15
RS
RSTSEL
LDAC
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DAC8822
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
DBT PACKAGE
TSSOP-38
(TOP VIEW)
4
Submit Documentation Feedback
www.ti.com
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
PIN ASSIGNMENTS (continued)Table 1. TERMINAL FUNCTIONS
PIN # NAME DESCRIPTION
1, 2, 24-28,
D0-D15 Digital Input Data Bits D0 to D15. Signal level must be ≤V
DD
+0.3V. D15 is MSB.30-38
Bipolar Offset Resistor A. Accepts up to ±18V.3 R
OFS
A In 2-quadrant mode, R
OFS
A ties to R
FB
A.In 4-quadrant mode, R
OFS
A ties to R
1
A and the external reference.4 R
FB
A Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion.4-Quadrant Resistor.5 R
1
A In 2-quadrant mode, R
1
A shorts to the V
REF
A pin.In 4-quadrant mode, R
1
A ties to R
OFS
A and the reference input.Center Tap Point of the Two 4-Quadrant Resistors, R
1
A and R
2
A.6 R
COM
A In 2-quadrant mode, R
COM
A shorts to the V
REF
pin.In 4-quadrant mode, R
COM
A ties to the inverting node of the reference amplifier.DAC A Reference Input in 2-Quadrant Mode, R
2
Terminal in 4-Quadrant Mode.7 V
REF
A In 2-quadrant mode, V
REF
A is the reference input with constant input resistance versus code.In 4-quadrant mode, V
REF
A is driven by the external reference amplifier.DAC A Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage8 I
OUT
A
output.9 AGNDA DAC A Analog Ground.10 DGND Digital Ground.11 AGNDB DAC B Analog Ground.DAC B Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage12 I
OUT
B
output.
DAC B Reference Input in 2-Quadrant Mode, R
2
Terminal in 4-Quadrant Mode.13 V
REF
B In 2-quadrant mode, V
REF
B is the reference input with constant input resistance versus code.In 4-quadrant mode, V
REF
B is driven by the external reference amplifier.Center Tap Point of the Two 4-Quadrant Resistors, R
1
B and R
2
B.14 R
COM
B In 2-quadrant mode, R
COM
B shorts to the V
REF
pin.In 4-quadrant mode, R
COM
B ties to the inverting node of the reference amplifier.4-Quadrant Resistor.15 R
1
B In 2-quadrant mode, R
1
B shorts to the V
REF
B pin.In 4-quadrant mode, R
1
B ties to R
OFS
B and the reference input.16 R
FB
B Internal Matching Feedback Resistor B. Connects to external op amp for I-V conversion.Bipolar Offset Resistor B. Accepts up to ±18V.17 R
OFS
B In 2-quadrant mode, R
OFS
B ties to R
FB
B.In 4-quadrant mode, R
OFS
B ties to R
1
B and the external reference.Write Control Digital Input In, Active Low. WR enables input registers.18 WR
Signal level must be ≤V
DD
+ 0.3V.19 A0 Address 0. Signal level must be ≤V
DD
+ 0.3V.20 A1 Address 1. Signal level must be ≤V
DD
+ 0.3V.Digital Input Load DAC Control. Signal level must be ≤V
DD
+ 0.3V. See the Function of Control Inputs21 LDAC
table for details.Power-On Reset State.RSTSEL = 0 corresponds to zero-scale reset.22 RSTSEL
RSTSEL = 1 corresponds to midscale reset.The signal level must be ≤V
DD
+ 0.3V.Reset. Active low resets both input and DAC registers.23 RS Resets to zero-scale if RSTSEL= 0, and to midscale if RSTSEL = 1.Signal level must be equal to or less than VDD + 0.3 V.29 V
DD
Positive Power Supply Input. The specified range of operation is 2.7V to 5.5V.
5Submit Documentation Feedback
www.ti.com
TIMING AND FUNCTIONAL INFORMATION
tWR
tDS tDH
tLWD
tLDAC tRST
WR
DATA
tAS tAH
A0/1
LDAC
RS
TIMING CHARACTERISTICS
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
Figure 1. Timing Diagram
All specifications at T
A
= –40 °C to +125°C, I
OUT
= virtual GND, GND = 0V, and V
REF
= 10V, unless otherwise noted
DAC8822
PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
= +5.0V 10 nsData to WR setup time t
DS
V
DD
= +2.7V 10 ns
V
DD
= +5.0V 10 nsA0/1 to WR setup time t
AS
V
DD
= +2.7V 10 ns
V
DD
= +5.0V 0 nsData to WR hold time t
DH
V
DD
= +2.7V 0 ns
V
DD
= +5.0V 0 nsA0/1 to WR hold time t
AH
V
DD
= +2.7V 0 ns
V
DD
= +5.0V 10 nsWR pulse width t
WR
V
DD
= +2.7V 10 ns
V
DD
= +5.0V 10 nsLDAC pulse width t
LDAC
V
DD
= +2.7V 10 ns
V
DD
= +5.0V 10 nsRS pulse width t
RST
V
DD
= +2.7V 10 ns
V
DD
= +5.0V 0 nsWR to LDAC delay time t
LWD
V
DD
= +2.7V 0 ns
6
Submit Documentation Feedback
www.ti.com
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
Table 2. Address Decoder PinsA1 A0 OUTPUT UPDATE
0 0 DAC A
0 1 None
1 0 DAC A and DAC B
1 1 DAC B
Table 3. Function of Control InputsCONTROL INPUTS
RS WR LDAC REGISTER OPERATION
Asynchronous operation. Reset the input and DAC register to '0' when the RSTSEL pin is tied to DGND, and to0 X X
midscale when RSTSEL is tied to V
DD
.
1 0 0 Load the input register with all 16 data bits.
1 1 1 Load the DAC register with the contents of the input register.
1 0 1 The input and DAC register are transparent.
LDAC and WR are tied together and programmed as a pulse. The 16 data bits are loaded into the input register on1
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
1 1 0 No register operation.
7Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +5V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T =+25 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA=+125°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
TA=+125°C
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 2. Figure 3.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 4. Figure 5.
LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 6. Figure 7.
8
Submit Documentation Feedback
www.ti.com
Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
T =+25 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T =+25 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
T 40- °
A= C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
T =+125 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
TA=+125°C
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS: V
DD
= +5V (continued)
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 8. Figure 9.
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 10. Figure 11.
DIFFERENTIAL LINEARITY ERROR DIFFERENTIAL LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 12. Figure 13.
9Submit Documentation Feedback
www.ti.com
Time(0.2 s/div)m
OutputVoltage(50mV/div)
V =+10V
REF
LDACPulse
Code:7FFFhto8000h
Time(0.2 s/div)m
OutputVoltage(50mV/div)
V =+10V
REF
LDACPulse
Code:8000hto7FFFh
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS: V
DD
= +5V (continued)
MIDSCALE DAC GLITCH MIDSCALE DAC GLITCH
Figure 14. Figure 15.
FULL-SCALE ERROR BIPOLAR-ZERO ERRORvs TEMPERATURE vs TEMPERATURE
Figure 16. Figure 17.
10
Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +2.7V
Channel A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
T =+125 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
TA=+125°C
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 18. Figure 19.
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 20. Figure 21.
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 22. Figure 23.
11Submit Documentation Feedback
www.ti.com
Channel B
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA=+25°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T =+25 C°
A
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA= 40- °C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
T = 40- °
AC
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
INL(LSB)
Code
TA=+125°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0 8192 16384 24576 32768 40960 49152 57344 65535
DNL(LSB)
Code
TA=+125°C
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS: V
DD
= +2.7V (continued)
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 24. Figure 25.
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 26. Figure 27.
LINEARITY ERROR LINEARITY ERRORvs DIGITAL INPUT CODE vs DIGITAL INPUT CODE
Figure 28. Figure 29.
12
Submit Documentation Feedback
www.ti.com
Time(0.2 s/div)m
OutputVoltage(50mV/div)
V =+10V
REF
LDACPulse
Code:7FFFhto8000h
Time(0.2 s/div)m
OutputVoltage(50mV/div)
V =+10V
REF
LDACPulse
Code:8000hto7FFFh
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS: V
DD
= +2.7V (continued)
MIDSCALE DAC GLITCH MIDSCALE DAC GLITCH
Figure 30. Figure 31.
FULL-SCALE ERROR BIPOLAR-ZERO ERRORvs TEMPERATURE vs TEMPERATURE
Figure 32. Figure 33.
13Submit Documentation Feedback
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +2.7V and +5V
180
160
140
120
100
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SupplyCurrent,IDD (mA)
LogicInputVoltage(V)
V =+5.0V
DD
V =+2.7V
DD
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
0xFFFF
0x8000
0x4000
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
10 100 1k 10k 100k 1M 10M 100M
Attenuation(dB)
Bandwidth(Hz)
0x0000
0x0001
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
0xFFFF
0xC000
0xA000
0x9000
0x8800
0x8400
0x8200
0x8100
0x8080
0x8040
0x8020
0x8010
0x8008
0x8004
0x8002
0x8001
0x8000
10 100 1k 10k 100k 1M 10M 100M
Attenuation(dB)
Bandwidth(Hz)
CodesfromMidscale
toPositiveFull-Scale
DAC0Voutput
limitedbybipolar
zeroerrorto
–96dBtypical
(–76dBmax).
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
-96
-102
-108
-114
0x0000
0x4000
0x6000
0x7000
0x7800
0x7C00
0x7E00
0x7F00
0x7F80
0x7FC0
0x7FE0
0x7FF0
0x7FF8
0x7FFC
0x7FFE
0x7FFF
0x8000
10 100 1k 10k 100k 1M 10M 100M
Attenuation(dB)
Bandwidth(Hz)
CodesfromNegative
Full-ScaletoMidscale
DAC0Voutput
limitedbybipolar
zeroerrorto
–96dBtypical
(–76dBmax).
Time(0.5 s/div)m
OutputVoltage(5V/div)
TriggerPulse
UnipolarMode
VoltageOutputSettling
6
5
4
3
2
1
0
-50 -30 -10 1301109070503010
SupplyCurrent,IDD (mA)
Temperature( C)°
V =5.0V
DD
V =2.7V
DD
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
SUPPLY CURRENT REFERENCE MULTIPLYING BANDWIDTHvs LOGIC INPUT VOLTAGE UNIPOLAR MODE
Figure 34. Figure 35.
REFERENCE MULTIPLYING BANDWIDTH REFERENCE MULTIPLYING BANDWIDTHBIPOLAR MODE BIPOLAR MODE
Figure 36. Figure 37.
SUPPLY CURRENT vs TEMPERATURE DAC SETTLING TIME
Figure 38. Figure 39.
14
Submit Documentation Feedback
www.ti.com
THEORY OF OPERATION
RRR
IOUT
GND
VREF
2R 2R2R 2R 2R 2R2R 2R2R 2R 2R 2R RFB
VOUT AńB+ *VREF D
65536
(1)
V+
V-
DAC8822 IOUTA/B
VDD
VREF
OPA277 VOUT
U2
VDD ROFS RFB
U1
GND
+15V
-15V
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
The DAC8822 is a multiplying, dual-channel, current output, 16-bit DAC. The architecture, illustrated inFigure 40 , is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the ladder is eitherswitched to GND or to the I
OUT
terminal. The I
OUT
terminal of the DAC is held at a virtual GND potential by theuse of an external I/V converter op amp. The R-2R ladder is connected to an external reference input (V
REF
) thatdetermines the DAC full-scale output current. The R-2R ladder presents a code-independent load impedance tothe external reference of 5k Ω ± 25%. The external reference voltage can vary in a range of –18V to +18V, thusproviding bipolar I
OUT
current operation. By using an external I/V converter op amp and the R
FB
resistor in theDAC8822, an output voltage range of –V
REF
to +V
REF
can be generated.
Figure 40. Equivalent R-2R DAC Circuit
The DAC output voltage is determined by V
REF
and the digital data (D) according to Equation 1 :
Each DAC code determines the 2R-leg switch position to either GND or I
OUT
. The external I/V converter op ampnoise gain will also change because the DAC output impedance (as seen looking into the I
OUT
terminal) changesversus code. Because of this change in noise gain, the external I/V converter op amp must have a sufficientlylow offset voltage such that the amplifier offset is not modulated by the DAC I
OUT
terminal impedance change.External op amps with large offset voltages can produce INL errors in the transfer function of the DAC8822because of offset modulation versus DAC code. For best linearity performance of the DAC8822, an op amp(such as the OPA277 ) is recommended, as shown in Figure 41 . This circuit allows V
REF
to swing from –10V to+10V.
Figure 41. Voltage Output Configuration
15Submit Documentation Feedback
www.ti.com
APPLICATION INFORMATION
DIGITAL INTERFACE
STABILITY CIRCUIT
C1
DAC8822
VREF
U2
VDD ROFS RFB
U1
VDD
GND
VREF
OPA277 VOUT
IOUTA/B
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
The parallel bus interface of the DAC8822 is comprised of a 16-bit data bus D0—D15, address lines A0 and A1,and a WR control signal. Timing and control functionality are shown in Figure 1 , and described in Table 2 andTable 3 . The address lines must be set up and stable before the WR signal goes low, to prevent loadingimproper data to an undesired input register.
Both channels of the DAC8822 can be simultaneously updated by control of the LDAC signal, as shown inFigure 1 . Reset control ( RS) and reset select control (RSTSEL) signals are provided to allow user reset ability toeither zero scale or midscale codes of both the input and DAC registers.
For a current-to-voltage (I/V) design, as shown in Figure 42 , the DAC8822 current output (I
OUT
) and theconnection with the inverting node of the op amp should be as short as possible and laid out according tocorrect printed circuit board (PCB) layout design. For each code change, there is an output step function. If thegain bandwidth product (GBP) of the op amp is limited and parasitic capacitance is excessive at the invertingnode, then gain peaking is possible. Therefore, a compensation capacitor C
1
(4pF to 20pF, typ) can be added tothe design for circuit stability, as shown in Figure 42 .
Figure 42. Gain Peaking Prevention Circuit with Compensation Capacitor
16
Submit Documentation Feedback
www.ti.com
BIPOLAR OUTPUT CIRCUIT
VOUT +ǒD
32768*1Ǔ VREF
(2)
D0
R1A
R1A R2A
D15 Parallel
Bus
Interface
InputA
Register
DACA
Register
DACA
Control
Logic
RS
RSTSEL
RCOMAV A
REF ROFSA
ROFSA RFBA
RFBA
VDD
IOUTA
AGNDA
DAC8822
OPA2277
U1
OPA2277 VOUT
C1
U2
VREF
DGND
WR
A0
A1
LDAC
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)
The DAC8822, as a 4-quadrant multiplying DAC, can be used to generate a bipolar output. The polarity of thefull-scale output (I
OUT
) is the inverse of the input reference voltage at V
REF
.
Using a dual op amp, such as the OPA2277 , full 4-quadrant operation can be achieved with minimalcomponents. Figure 43 demonstrates a ±10V
OUT
circuit with a fixed +10V reference. The output voltage isshown in Equation 2 :
Figure 43. Bipolar Output Circuit for Channel A
17Submit Documentation Feedback
www.ti.com
PROGRAMMABLE CURRENT SOURCE CIRCUIT
ILAńB+(R2)R3)ńR1
R3 VREF D
65536
(3)
ZO+R1ȀR3(R1)R2)
R1(R2Ȁ)R3Ȁ)*R1Ȁ(R2)R3)
(4)
R ´
150kW
1
R
150kW
1
U3
DAC8822
R
15kW
2
R
50W
3
R
50
´
W
3
IL
LOAD
VREF
R
15k
´
W
2
C
10pF
1
C
10pF
2
U2
VDD ROFS RFB
U1
VDD
GND
VREF
OPA2277
VOUT
IOUTA/B
OPA2277
CROSS-REFERENCE
DAC8822
SBAS390A – DECEMBER 2006 – REVISED MARCH 2007
APPLICATION INFORMATION (continued)
The DAC8822 can be integrated into the circuit in Figure 44 to implement an improved Howland current pumpfor precise V/I conversions. Bidirectional current flow and high-voltage compliance are two features of the circuit.With a matched resistor network, the load current of the circuit is shown by Equation 3 :
The value of R
3
in the previous equation can be reduced to increase the output current drive of U3. U3 can drive±20mA in both directions with voltage compliance limited up to 15V by the U3 voltage supply. Elimination of thecircuit compensation capacitor (C
1
) in the circuit is not suggested as a result of the change in the outputimpedance (Z
O
), according to Equation 4 :
As shown in Equation 4 , Z
O
with matched resistors is infinite and the circuit is optimum for use as a currentsource. However, if unmatched resistors are used, Z
O
is positive or negative with negative output impedancebeing a potential cause of oscillation. Therefore, by incorporating C
1
into the circuit, possible oscillation problemsare eliminated. The value of C
1
can be determined for critical applications; for most applications, however, avalue of several pF is suggested.
Figure 44. Programmable Bidirectional Current Source Circuit
The DAC8822 has an industry-standard pinout. Table 4 provides the cross-reference information.
Table 4. Cross-Reference
SPECIFIED CROSS-INL DNL TEMPERATURE PACKAGE PACKAGE REFERENCEPRODUCT BIT (LSB) (LSB) RANGE DESCRIPTION OPTION PART
DAC8822QB 16 2 1 –40 °C to +125 °C TSSOP-38 DBT AD5547BDAC8822QC 16 1 1 –40 °C to +125 °C TSSOP-38 DBT N/A
18
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC8822QBDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QBDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QBDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QBDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QCDBT ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QCDBTG4 ACTIVE TSSOP DBT 38 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QCDBTR ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
DAC8822QCDBTRG4 ACTIVE TSSOP DBT 38 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC8822QBDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
DAC8822QCDBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC8822QBDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
DAC8822QCDBTR TSSOP DBT 38 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated