A4402KLPTR-T - Allegro Microsystems

Description

The A4402 is a dual-output regulator, combining in a single

package a constant on-time buck regulator and a linear regulator

(LDO)—each with adjustable output voltages. It is ideal for

applications that require two regulated voltages, such as in

microcontroller- or DSP-based applications requiring core

and I/O voltage rails.

The buck regulator output supplies the adjustable linear

regulator to reduce power dissipation and increase overall

efficiency. The switching regulator is capable of operating

above 2 MHz, allowing the use of small low value inductors

and capacitors while avoiding sensitive EMI frequency bands

such as AM radio in automotive applications.

Protection features include undervoltage lockout and thermal

shutdown. In case of a shorted load, each regulator features

overcurrent protection.

The device has an integrated power-on reset with adjustable

delay to monitor LDO output voltage and provide a signal that

can be used to reset a DSP or microcontroller. It also includes

a watchdog circuit.

The A4402 is provided in a 16-pin TSSOP, with exposed pad

for enhanced thermal dissipation. It is lead (Pb) free, with

100% matte tin leadframe plating.

4402-DS, Rev. 7

Features and Benefits

▪ 2 MHz switching frequency

▪ Adjustable soft start timer

▪ Watchdog input

▪ Power-on reset output

▪ Adjustable buck and linear regulators

▪ Enable input

▪ 6 to 50 V supply voltage range

▪ Overcurrent protection

▪ Undervoltage lockout (UVLO)

▪ Thermal shutdown protection

Constant On-Time Buck Converter

With Integrated Linear Regulator

Package: 16-pin TSSOP with exposed

thermal pad (suffix LP)

Typical Application

Not to scale

A4402

ENB VO2

NPOR

GND

1F

3.3 V

250 mA

VO2

33 H

VIN1

FB1

10 F

VBAT

FB2

VIN2

POR

CPOR

TSET

CTSET

0.1 F

ISEN

VLIN

VSW

Switching Regulator Output

Linear Regulator Output

A 4402

TON

0.01 F

RSENSE .7 F

Rton

750 k

k

WDI

0.33 F

0.15 F

k

31.6

k

9.76

5.62

k

4.7 k

BOOT

AUTOMOTIVE (“K” VERSION)

• Power steering control units

• Transmission control units

• Lighting control units

• Infotainment

• Cluster

• Centerstack

• Other body control

COMMERCIAL (“E” VERSION)

• Photo and inkjet printers

• Industrial controls

• Distributed power systems

• Networking applications

• Point-of-sale

• Security systems

Applications:

Efficiency vs. Output Current

0 200 800600400 1000 1200

OUT

(mA)

Efficiency %

VOUT (V)

3.3

Data is for reference only. Efficiency data from circuit shown in left panel.

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit

VIN1 Pin VIN1 –0.3 to 50 V

VIN2 Pin VIN2 –0.3 to 7 V

LX Pin VLX –1 to 50 V

ISEN Pin VISEN –0.5 to 1 V

ENB Pin VENB –0.3 to 7 V

VO2 Pin VO2 –0.3 to 7 V

WDI Pin VWDI –0.3 to 6 V

TON Pin VTON –0.3 to 7 V

FB1 and FB2 Pins VFBx –0.3 to 7 V

NPOR VNPOR –0.3 to 6.5 V

TSET Pin VTSET –0.3 to 7 V

POR Pin VPOR –0.3 to 6 V

BOOT Pin VBOOT VLX to VIN1+ 7 V

Ambient Operating Temperature TA

Range E –40 to 85 °C

Range K –40 to 150 °C

Junction Temperature TJ(max) 150 °C

Storage Temperature Range Tstg –40 to 150 °C

Selection Guide

Part Number Ambient Operating

Temperature, TA Packing Package

A4402ELPTR-T –40°C to 85°C 4000 pieces per 13-in. reel 16-pin TSSOP with exposed thermal pad

A4402KLPTR-T –40°C to 150°C

Thermal Characteristics

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 34 ºC/W

*Additional thermal information available on the Allegro website.

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Block Diagram

ENB

VO2

NPOR

VFB2

Internal

Regulator

VIN1

ENB 1

3.3 V

250 mA

VO2

FAULT

TSD

VIN2

33 H

FB1

BOOT

Switch PWM

Control

Switch

Disable

Boot

Charge

VBAT

FB2

VIN2

POR

CPOR

Soft Start

Ramp Generator

Watchdog Timer

TSET

CTSET

VREF

VSW

VLIN

0.1

ISEN

VSW

TON

VREG

0.01

4.7

VIN1

Rton

750 k

k

4.7 k

k

WDI

0.15 F

F

0.33

5.62

RSENSE

31.6

9.76

GND

F

FF

F

Pin-out Diagram

Terminal List Table

Number Name Function

1 TON On time setting terminal

2 GND Ground

3 FB2 Feedback for VLIN

4 VIN2 Input voltage 2

5 VO2 Regulator 2 output

6 WDI Watchdog input

7 TSET Soft start and watchdog timing capacitor terminal

8 NPOR Fault output

9 FB1 Feedback for VSW

10 POR POR delay

11 ISEN Current sense, limit setting for switching regulator, connect to GND

through series resistor

12 BOOT Boot node for LX

13 LX Switching regulator output

14 GND Ground

15 VIN1 Input voltage 1

16 ENB Enable input

– PAD Exposed thermal pad

TON

GND

FB2

VIN2

VO2

WDI

TSET

NPOR

ENB

VIN1

GND

BOOT

ISEN

POR

FB1

PAD

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Continued on the next page…

ELECTRICAL CHARACTERISTICS1 valid for Temperature Range E version at TJ = 25°C and for Temperature Range K

version at TJ = –40°C to 150°C, VIN1 = 6 to 50 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Supply Quiescent Current IIN(Q) ENB = 5 V, IOUT = ISW+ILIN = 0 mA, 13.5 V < VIN1 < 50 V – 10 – mA

ENB = 0 V, 13.5 V< VIN1 < 18 V, IOUT = ISW+ ILIN = 0 mA – – 1 A

ENB Logic Input Voltage VENB VENB rising 2.0 2.28 2.56 V

ENB Hysteresis VENBHYS – 100 – mV

ENB Logic Input Current2IENB High input level, VENB = 3 V – – 100 A

Low input level, VENB < 0.4 V –2 – 2 A

Linear Regulator

Feedback Voltage VFB2 1 mA < IO2 < 250 mA, 3.3 V < VIN2 < 5 V 1.156 1.180 1.204 V

VO2 Undervoltage Lockout

Threshold VO2UVLO V

O2 rising based on FB voltage 0.896 0.944 0.990 V

VO2 Undervoltage Lockout

Hysteresis VO2UVHYS 30 50 70 mV

Feedback Input Bias Current2IFB2 –100 100 400 nA

Current Limit IO2 250 – 350 mA

Switching Regulator

Feedback Voltage VFB1 I

OUT = ISW+ ILIN = 1 mA to 1.0 A, 8 V < VIN1 < 18 V 1.139 1.180 1.221 V

Feedback Input Bias Current IFB1 V

IN1 = 6 V –400 –100 100 nA

Switcher On Time ton

VIN1 = 19.25 V, Rton = 750 k 450 640 830 ns

VIN1 = 13.5 V, Rton = 750 k165 230 300 ns

VIN1 = 8 V, Rton = 750 k1050 1480 1925 ns

ton Low Voltage Threshold VPL VIN1 rising 8.1 9 9.9 V

ton High Voltage Threshold VPH VIN1 rising 15.75 17.5 19.25 V

Changeover Hysteresis VHYS – 250 – mV

Minimum On-time tonmin 80 – – ns

Minimum Off-time toffmin 130 – – ns

Buck Switch On-Resistance RDS(on) TJ = 25°C, ILOAD = 1 A – 400 – m

TJ = 125°C, ILOAD = 1 A – 650 – m

ISEN Voltage VISEN – –200 – mV

Valley Current Limit Threshold Ilim RSENSE = 0.27  – 740 – mA

6 V < VIN1 < 8 V – – 550 mA

Protection Circuitry

NPOR Output Voltage VNPOR I

NPOR = 1 mA – – 400 mV

NPOR Leakage Current INPOR V

NPOR = 5.5 V – – 1.5 A

NPOR Reset VNPORRESET 20 k pullup connected to VOUT2 – – 0.7 V

Thermal Shutdown Threshold TJTSD T

J rising – 170 – ºC

Thermal Shutdown Hysteresis TJTSDHYS – 15 – ºC

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 (continued) valid for Temperature Range E version at TJ = 25°C and for Temperature

Range K version at TJ = –40°C to 150°C, VIN1 = 6 to 50 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Timing Circuitry

TSET Current, Watchdog Mode ITSETWDI NPOR = high 7 10 14 A

TSET Valley Voltage, Watchdog Mode VTRIP – 1.2 – V

TSET Reset Voltage, Watchdog Mode VRESET – 0.48 – V

WDI Frequency fWDI – – 100 kHz

WDI Duty Cycle DCWDI 10 – 90 %

WDI Logic Input VWDI(0) VIN2 ×

0.55 – – V

WDI Logic Input Current2IWDI VWDI = 0 to 5 V –20 < 1.0 20 A

WDI Input Hysteresis VWDIHYS – 300 – mV

TSET Current, Soft Start Mode ITSETSS NPOR = low 14 20 26 A

POR Current IPOR 3.92 5.60 7.28 A

1Temperature Range E version tested at TJ = 25°C with performance from –40°C to 85°C guaranteed by design and characterization.

2For input and output current specifications, negative current is defined as coming out of (sourcing) the specified pin.

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

VIN1

ENB

VSW

VO2

NPOR

UVLO Rising

tpor

tss

UVLO Falling

6 V

18 V

VSW

VO2

NPOR

tpor

tss

VPOR

VCTSET

UVLO Rising

tpor

UVLO Rising

tpor

tss

Power-Up and Power-Down Timing Diagrams

Using ENB

Using VIN1

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Watchdog Timing Diagram

ENB

UVLO Rising

Vreset

Vtrip

VSW

NPOR

tpor

tss

WDI

VO2

VTSET

twait

tpor

twait

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Functional Description

Basic Operation The A4402 contains a fixed on-time, adjust-

able voltage buck switching regulator with valley sensing current

mode control, and an adjustable linear regulator designed to run

off the buck regulator output. The constant on-time converter

maintains a constant output frequency because the on-time is

inversely proportional to the supply voltage. As the input voltage

decreases, the on-time is increased, maintaining a relatively con-

stant period. Valley mode current control allows the converter to

achieve very short on-times because current is measured during

the off-time.

The device is enabled via the ENB input. When the ENB pin

is pulled high, the converter starts-up under the control of an

adjustable soft start routine whose ramp time is controlled by an

external capacitor.

Under light load conditions, the switch enters pulse-skipping

mode to ensure regulation is maintained. This effectively changes

the switcher frequency. The frequency also is affected when the

switcher is operating in discontinuous mode. In order to maintain

a wide input voltage range, the switcher period is extended when

either the minimum off-time at low VIN1

, is reached or the mini-

mum on-time at high VIN1

Switcher Overcurrent Protection The converter utilizes

pulse-by-pulse valley current limiting, which operates when the

current through the sense resistor rises to VISEN

. During an over-

load condition, the switch is turned on for a period determined

by the constant on-time circuitry. The switch off-time is extended

until the current decays to the current limit value set by the

selection of the sense resistor, at which point the switch turns on

again. Because no slope compensation is required in this control

scheme, the current limit is maintained at a reasonably constant

level across the input voltage range.

Figure 1 illustrates how the current is limited during an overload

condition. The current decay (period with switch off) is propor-

tional to the output voltage. As the overload is increased, the out-

put voltage tends to decrease and the switching period increases.

VIN1 and VIN2 VIN1 is a high voltage input, designed to with-

stand 50 V. Bulk capacitance of at least 10 μF should be used to

decouple input supply VIN1. The VIN2 input is used to supply

the linear regulator and should be connected directly to the output

of the switching regulator when the target for the VSW voltage is

between 3 and 5.5 V. For voltages outside of that range, the bias

supply for the IC is taken from VIN1 directly and affects overall

efficiency.

For applications where the switcher voltage is greater than 5 V, a

second supply between 3 and 5.5 V can be used to supply VIN2

bias current and the linear regulator. Note that the current into the

VIN2 supply must supply both the idd bias current and any cur-

rent load on the linear regulator.

Output Voltage Selection The output voltage on each of the

two regulators is set by a voltage divider off the regulator output,

as follows:

VSW VFB1













R1 + R2

VLIN VFB2













R3 + R4

(1)

(2)

In order to maintain accuracy on the regulators the equivalent

impedance on the FB node (R1 parallel with R2) should be

approximately 10 kΩ.

Current Limit level

Inductor current operating at maximum load

Maximum load

Constant On -Time

CurrentCurrent

Time

Constant period

Current Limit level

Inductor current operating in a “soft ” overload

Overload

Time

Extended period

Figure 1. Current limiting during overload

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

FB Both output regulators use a resistive feedback network to set

the output voltage. To prevent introducing noise into the FB net-

work it is important to keep the total impedance of the FB nodes

low enough to prevent noise injection. For commercial applica-

tions it is recommended that the impedances on the FB nodes are

less than 50 kΩ. For automotive applications it is recommended

that the total impedance of the FB nodes is less than 25 kΩ.

TSET The TSET pin serves a dual function by controlling the

timing for both the soft start ramp and the WDI input. The current

sourced from the TSET pin is dependant on the state of NPOR.

There are two formulas for calculating the time constants. CTSET

must be selected so that both the WDI frequency and soft start

requirements are met. The formulas for calculating WDI and soft

start timing are:

tWDI 7.2 × 9.6

104 × CTSET , and

(3)

tSS 6.0 × 6.0

104 × CTSET ,

(4)

where CTSET is the value of the capacitor and the results,

tx, are in s.

Watchdog The WDI input is used to monitor the state of a DSP

or microcontroller. A constant current is driven into the capacitor

on TSET, causing the voltage on the TSET pin to ramp upward

until, at each rising edge on the WDI input, the ramp is pulled

down to VRESET. If no edge is seen on the WDI pin before the

ramp reaches VTRIP , the NPOR pin is pulled low.

The watchdog timer is not activated until the WDI input sees one

rising edge. If the watchdog timer is not going to be used, the

WDI pin should be pulled to ground with a 4.7 kΩ resistor.

Soft Start During soft start, an internal ramp generator and the

external capacitor on TSET are used to ramp the output voltage

in a controlled fashion. This reduces the demand on the exter-

nal power supply by limiting the current that charges the output

capacitor and any DC load at startup. Either of the following

conditions are required to trigger a soft start:

• ENB pin input rising edge

• Reset of a TSD event

When a soft start event occurs, VO2 is held in the off state until

the soft start ramp timer expires. Then the regulator will power

up normally. Refer to timing diagrams for details.

BOOT A bootstrap capacitor is used to provide adequate charge

to the NMOS switch. The boot capacitor is referenced to LX

and supplies the gate drive with a voltage larger than the supply

voltage. The size of the capacitor must be 0.01 μF, X7R type, and

rated for at least 25 V.

TON A resistor from the TON input to VIN1 sets the on-time of

the converter for a given input voltage. The formula to calculate

the on-time, tON (ns), is:

tON 3.12–12 + 60

10–9

VIN1

RTON

(5)

When the supply voltage is between 9 and 17.5 V, the switcher

period remains constant, at a level based on the selected value

of Rton . At voltages lower than 9 V and higher than 17.5 V, the

period is reduced by a factor of 3.5.

If a constant period is desired over varying input voltages, it is

important to select an on-time that under worst case conditions

will not exceed the minimum off-time or minimum on-time of the

converter. For reasonable input voltage ranges, the period of the

converter can be held constant, resulting in a constant operating

frequency over the input supply range.

More information on how to choose Rton can be found in the

Application Information section.

ISEN The sense input is used to sense the current in the diode

during the off-time cycle. The value for RSENSE is obtained by the

formula:

RSENSE = VISEN / IVALLEY , (6)

where IVALLEY is the lowest current measured through the induc-

tor during the off-time cycle.

It is recommended that the current sense resistor be sized so that,

at peak output current, the voltage on ISEN does not exceed

–0.5 V. Because the diode current is measured when the inductor

current is at the valley, the average output current is greater than

the IVALLEY value. The value for IVALLEY should be:

IVALLEY = IOUT(av) – 0.5 IRIPPLE + K , (7)

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

where:

IOUT(av) is the average of both output currents,

IRIPPLE is the inductor ripple current, and

K is a guardband margin. The peak current in the switch is then:

IPEAK = IVALLEY + IRIPPLE . (8)

The valley current must be calculated so that, at the worst-case

ripple, the converter can still supply the required current to the

load. Further information on how to calculate the ripple current is

included in the Application Information section.

ENB An active high input enables the device. When set low, the

device enters sleep mode; all internal circuitry is disabled, and the

part draws a maximum of 1 μA.

Thermal Shutdown When the device junction temperature, TJ

is sensed to be at TJTSD, a thermal shutdown circuit disables the

regulator output, protecting the A4402 from damage.

Power-on Reset Delay The POR function monitors the VFB2

voltage and provides a signal that can be used to reset a DSP or

microcontroller. A POR event is triggered by either of the

following conditions:

• VFB2 falls below its UVLO threshold. This occurs if the current

limit on either regulator is exceeded, or if the switcher voltage

falls due to TSD.

• After a rising edge on the WDI input, the voltage on TSET

reaches VTRIP.

An open drain output, through the NPOR pin, is provided to

signal a POR event to the DSP or microcontroller. The reset

occurs after an adjustable delay, tPOR, set by an external capacitor

connected to the POR pin. The value of tPOR is calculated using

the following formula:

tPOR = 214 × 103 × CPOR , (9)

where CPOR is the value of the POR capacitor in μF, and tPOR is

the POR time in seconds.

Shutdown The buck regulator will shutdown if one of the fol-

lowing conditions is present:

• TSD

• ENB falling edge

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Switcher On-Time and Switching Frequency In order for

the switcher to maintain regulation, the energy that is transferred

to the inductor during the on-time must be transferred to the out-

put capacitor during the off-time. This relationship must be main-

tained for stable operation and governs the fundamental operation

of a switching regulator. Each component along the current path

changes the voltage across the inductor and therefore the energy

that is transferred during each cycle. Summing the voltage from

VIN to VOUT during each cycle gives a relationship of the voltage

across the inductor during the on-time and during the off-time.

These terms are represented as VON and VOFF

Given a target operating frequency, represent tON as:

tON = T × D (10)

where T equals 1 / fSW , and D is the duty cycle.

Duty cycle can be represented as the voltage across the inductor

during the off-time, divided by the total voltage of the off-time

and on-time:

D = VOFF / (VOFF + VON ) (11)

Next, determine the voltage drops during the on cycle and the

off cycle. Figure 2 shows the current path during the on-time and

off-time.

Creating voltage summation during each cycle will give equa-

tions to represent VON and VOFF

VON = VIN – VOUT – (IOUT × RL ) – (RDS × IOUT

) (12)

VOFF = VOUT + (IOUT × RL ) + Vf + (RS × IOUT

) (13)

Now substituting VON and VOFF into equation 11 gives a com-

plete formula for duty cycle as it relates to the voltage across the

inductor:

VOUT × (IOUT× RL ) + Vf + ( RS× IOUT)

VOUT + (IOUT× RL ) + Vf + ( RS× IOUT) +

VIN – VOUT – (IOUT× RL ) – ( RDS+ IOUT)

(14)

The effects of the voltage drop across the inductor resistance and

trace resistance do have an effect on the switching frequency.

However, the frequency variation due to these factors is small

and is covered in the variation of the switcher period, TSW , which

is ±25% of the target. Removing these current-dependent terms

simplifies the equation:

VOUT + Vf + ( RS× IOUT)

VOUT + Vf + ( RS× IOUT) +

VIN – VOUT – ( RDS× IOUT)

(15)

Further simplification and grouping of terms yields:

VOUT + Vf + ( RS× IOUT)

VIN + Vf + ( RS× IOUT) – ( RDS× IOUT)

(16)

Substitute this simplified expression for duty cycle back into

equation 10. The following formula results in the on-time, given

a target switching frequency:

tON =

VOUT + Vf + ( RS× IOUT)

VIN + Vf + ( RS× IOUT) – ( RDS× IOUT)

fSW

(17)

The formulas above describe how tON changes based on input and

load conditions. Because load changes are minimal, and the out-

put voltage is fixed, the dominant factor that effects on-time is the

input voltage. The converter is able to maintain a constant period

over a varying supply voltage because the on-time is proportional

to the input voltage. The current into the TON terminal is derived

from a resistor tied to VIN1, which sets the on-time proportional

to the supply voltage. Selecting the resistor value, based on the

tON calculated above, is done using the following formula:

RTON =

3.12 × 10

–12

(tON – 60 × 10

–9

)× VIN

(18)

After the resistor is selected and a suitable tON is found, it must

be demonstrated that tON does not, under worst-case conditions,

Application Information

VIN1

Control Logic

OUT

On Cycle

Off Cycle

Vsw

VRL

VRS VRL

Figure 2. Current limiting during overload

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

exceed the minimum on-time or minimum off-time of the con-

verter. The minimum on-time occurs at maximum input voltage

and minimum load. The maximum off-time occurs at minimum

supply voltage and maximum load. For supply voltages below

9.5 V and above 17 V, refer to the Low Voltage Operation section.

Low and High Voltage Operation The converter can run at

very low input voltages. With a 5 V output, the minimum input

supply can be as low as 6 V. When operating at high frequencies,

the on-time of the converter must be very short because the avail-

able period is short. At high input voltages the converter must

maintain very short on-times, while at low input voltages the con-

verter must maintain long off-times. Rather than limit the supply

voltage range, the converter solves this problem by automatically

increasing the period by a factor of 3.5. With the period extended,

the converter will not violate the minimum on-time or off-time.

If the input voltage is between 9.5 V and 17 V, the converter will

maintain a constant period. When calculating worst-case on-times

and off-times, make sure to use the multiplier if the supply volt-

age is between those values.

When operating at voltages below 8 V, additional care must be

taken when selecting the inductor and diode. At low voltages

the maximum current may be limited due to the IR drops in the

current path. When selecting external components for low voltage

operation, the IR drops must be considered when determining

on-time, so the complete formula should be used to make sure the

converter does not violate the timing specification.

Inductor Selection Choosing the right inductor is critical to

the correct operation of the switcher. The converter is capable of

running at frequencies above 2 MHz. This makes it possible to

use small inductor values, which reduces cost and board area.

The inductor value is what determines the ripple current. It is

important to size the inductor so that under worst-case conditions

IVALLEY equals IAV minus half the ripple current plus reasonable

margin. If the ripple current is too large, the converter will be

current limited. Typically peak-to-peak ripple current should be

limited to 20% to 25% of the maximum average load current.

Worst-case ripple current occurs at maximum supply voltage.

After calculating the duty cycle, DC, for this condition, the ripple

current can be calculated. First to calculate DC:

DC =.

VIN1(max) + Vf + (VSENSE× IPEAK )

VSW+ Vf + (VSENSE× IPEAK )

(19)

Using the duty cycle, a ripple current can be calculated using the

following formula:

LDC

IRIPPLE

VIN1 – VOUT fSW(min)

××

(20)

where IRIPPLE is 25% of the maximum load current, and fSW(min)

is the minimum switching frequency (nominal frequency minus

25%). For the example used above, a 1 A converter with a supply

voltage of 13.5 V was the design objective. The supply voltage

can vary by ±10%. The output voltage is 5 V, Vf is 0.5 V, VSENSE

is 0.15, and the desired frequency is 2.0 MHz. The duty cycle

is calculated to be 36.45%. The worst-case frequency is 2 MHz

minus 20% or 1.6 MHz. Using these numbers in the above

formula shows that the minimum inductance for this converter is

9.6 μH.

Output Capacitor The converter is designed to operate with

a low-value ceramic output capacitor. When choosing a ceramic

capacitor, make sure the rated voltage is at least 3 times the

maximum output voltage of the converter. This is because the

capacitance of a ceramic decreases as they operate closer to their

rated voltage. It is recommended that the output be decoupled

with a 10 μF, X7R ceramic capacitor. Larger capacitance may be

required on the outputs if load surges dramatically influence the

output voltage.

Output ripple is determined by the output capacitance and the

effects of ESR and ESL can be ignored assuming recommended

layout techniques are followed. The output voltage ripple is

approximated by:

IRIPPLE

VRIPPLE 4 × fSW × COUT

(21)

Input Capacitor The value of the input capacitance affects

the amount of current ripple on the input. This current ripple is

usually the source of supply side EMI. The amount of interfer-

ence depends on the impedance from the input capacitor and

the bulk capacitance located on the supply bus. Adding a small

value, 0.1 μF , ceramic capacitor as close to the input supply pin

as possible can reduce EMI effects. The small capacitor will help

reduce high frequency transient currents on the supply line. If

further filtering is needed it, is recommended that two ceramic

capacitors be used in parallel to further reduce emissions.

Rectification Diode The diode conducts the current during the

off-cycle. A Schottky diode is needed to minimize the forward

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

drop and switching losses. In order to size the diode correctly, it

is necessary to find the average diode conduction current using

the formula below:

ID(av) ILOAD × (1 – DC(min))

(22)

where DC (min) is defined as:

DC (min) =,

VSW+Vf

VIN1+Vf

(23)

where VIN1 is the maximum input voltage and Vf is the maximum

forward voltage of the diode.

Average power dissipation in the diode is:

PD(diode) ILOAD(av) × DC(min) × Vf

(24)

The power dissipation in the sense resistor must also be consid-

ered using I2R and the minimum duty cycle.

PCB Layout The board layout has a large impact on the per-

formance of the device. It is important to isolate high current

ground returns, to minimize ground bounce that could produce

reference errors in the device. The method used to isolate power

ground from noise sensitive circuitry is to use a star ground. This

approach makes sure the high current components such as the

input capacitor, output capacitor, and diode have very low imped-

ance paths to each other. Figure 3 illustrates the technique.

The ground from each of the components should be very close to

each other and be connected on the same surface as the com-

ponents. Internal ground planes should not be used for the star

ground connection, as vias add impedance to the current path.

In order to further reduce noise effects on the PCB, noise sensi-

tive traces should not be connected to internal ground planes.

The feedback network from the switcher output should have an

independent ground trace that goes directly to the exposed pad

underneath the device. The exposed pad should be connected to

internal ground planes and to any exposed copper used for heat

dissipation. If the grounds from the device are also connected

directly to the exposed pad the ground reference from the feed-

back network will be less susceptible to noise injection or ground

bounce.

To reduce radiated emissions from the high frequency switching

nodes it is important to have an internal ground plane directly

under the LX node. The plane should not be broken directly

under the node as the lowest impedance path back to the star

ground would be directly under the signal trace. If another trace

does break the return path, the energy will have to find another

path, which is through radiated emissions.

Figure 3. Star Ground Connection

Star Ground

A4402

Current path

(off-cycle)

Current path (on-cycle)

RSENSE

VIN1

RLOAD

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PAD

A4402

C1 C8

TON

GND

FB2

VIN2

VO2

WDI

TSET

NPOR

ENB

VIN1

GND

BOOT

ISEN

POR

FB1

IN1

LIN

R7 R1

PCB Layout Diagram

PCB

Thermal Vias

Trace (2 oz.)

Signal (1 oz.)

Ground (1 oz.)

Thermal (2 oz.)

A4402 Solder

R5 GND

VIN2

C1 C8

VSW

VLIN

VIN1

GND GND

GND

Star Ground

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Pin Circuit Diagrams

Power Terminals

GND GND

54 V

GND GND

7 V

VIN1

GND

54 V

VIN1

TON

GND

VIN2

FB1

FB2

WDI

TSET

NPOR

POR

ISEN

ENB

Logic Terminals

VIN1

BOOT

GND

10 V

VIN2

VO2

GND

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

SEATING

PLANE

C0.10

16X

6.10

0.65

0.45

1.70

3.00

5.00 ±0.10

3.00

1.20 MAX

0.15 MAX

0.65

0.25

(1.00)

4.40 ±0.10 6.40 ±0.20 0.60 ±0.15

4° ±4

0.25 +0.05

–0.06

0.15 +0.05

–0.06

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

All dimensions nominal, not for tooling use

(reference JEDEC MO-153 ABT)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

Exposed thermal pad (bottom surface)

Package LP, 16-Pin TSSOP

with Exposed Thermal Pad

Constant On-Time Buck Converter

With Integrated Linear Regulator

A4402

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Revision History

Revision Revision Date Description of Revision

Rev. 7 April 10, 2012 Miscellaneous minor edits