1. General description
The 74HC166; 74HCT166 is an 8-bit serial or parallel-in/serial-out shift register. The
device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial
output (Q7). When th e parallel ena ble input (PE) is LOW, the dat a from D0 to D7 is load ed
into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When
PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of
CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH
transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes which
enable the use of current limiting resistors to interface input s to voltages in excess of V CC.
2. Features and benefits
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standard no. 7A
Input levels:
For 74HC166: CMOS level
For 74HCT166: TTL level
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Rev. 3 — 11 September 2013 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC166N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT166N
74HC166D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HCT166D
74HC166DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width
5.3 mm SOT338-1
74HCT166DB
74HC166PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body
width 4.4 mm SOT403-1
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 2 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
4. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
aaa-008816
Q7 13
115
67
D0
PE DS
CP CE
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
10
11
12
14
9MR
aaa-008817
6
7
15
2,1D
2,1D
≥1
SRG8
R
M2
C1/2
9
1
2
3
4
5
10
11
12
14 13
2,1D
Fig 3. Functional di agram
aaa-008818
8-BIT PARALLEL/SERIAL-IN/
SERIAL-OUT SHIFT REGISTER
DS
9
1
6
15
2
Q7
D0
13
3
D1
4
D2
5
D3
10
D4
11
D5
12
D6
14
D7
MR
CP
CE
PE
7
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74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 3 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 4. Logic diag ram
aaa-008819
MR
S
CP
D0 D1 D2 D3 D4 D5 D6 D7
Q7
RRD
FF
1
S
CP
RRD
FF
2
S
CP
RRD
FF
3
S
CP
RRD
FF
4
S
CP
RRD
FF
5
S
CP
RRD
FF
6
S
CP
RRD
FF
7
S
CP
RRD
FF
8
CE
CP
DS
PE
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 4 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configu ration (DIP16, SO16 and (T)SSOP16)
74HC166
74HCT166
DS V
CC
D0 PE
D1 D7
D2 Q7
D3 D6
CE D5
CP D4
GND MR
aaa-008815
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
DS 1 serial data input
D0 to D7 2, 3, 4, 5, 10, 11, 12, 14 parallel data inputs
CE 6 clock enable input (active LOW)
CP 7 clock input (LOW-to-HIGH edge-triggered)
GND 8 ground (0 V)
MR 9 asynchronous master reset (active LOW)
Q7 13 serial output from the last stage
PE 15 parallel enable input (active LOW)
VCC 16 positive supply voltage
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 5 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Table 3. Function table[1]
Operating modes Inputs Qn registers Output
PE CE CP DS D0 to D7 Q0 Q1 to Q6 Q7
parallel load I I X I L L to L L
IIX h H H to H H
serial shift h I l X L q0 to q5 q6
hI h X H q0 to q5 q6
hold “do nothing”XHXXXq0q1 to q6q7
Fig 6. Typical clear, shift, load, inhibit, and shift sequences
H
L
H
L
H
L
H
H
load aaa-008820clear
CP
MR
DS
shift/
load
D0
D1
D2
D3
D4
D5
D6
D7
Q7
CE
mode
control
inputs
parallel
inputs
output
inhibit
serial shiftserial shift
HH LHHH
LL
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 6 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
7. Limiting values
[1] The input and output voltage ratings may be e xceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 C.
[3] Ptot derates linearly with 8 mW/K above 70 C.
[4] Ptot derates linearly with 5.5 mW/K above 60 C.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput current 0.5 V < VO< VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
DIP16 package [2] - 750 mW
SO16 package [3] - 500 mW
(T)SSOP16 package [4] - 500 mW
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 7 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC166 74HCT166 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 - +125 40 - +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC166
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 8 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
CIinput
capacitance -3.5- - - - -pF
74HCT166
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 5.2 mA; VCC = 4.5 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =4.5V --0.1 - 1-1A
ICC supply current VI = VCC or GND; IO=0A;
VCC =4.5V - - 8.0 - 80 - 160 A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs - 35 126 - 157.5 - 171.5 A
CP and CE inputs - 80 288 - 360 - 392 A
MR input - 40 144 - 180 - 196 A
PE input - 60 216 - 270 - 294 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 9 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC166
tpd propagation
delay CP to Q7; see Figure 7 [1]
VCC = 2.0 V - 50 150 - 190 - 225 ns
VCC = 4.5 V - 18 30 - 38 - 45 ns
VCC = 5.0 V; CL=15pF - 15 - - - - - ns
VCC = 6.0 V - 14 26 - 33 - 38 ns
MR to Q7; see Figure 8
VCC = 2.0 V - 47 160 - 200 - 240 ns
VCC = 4.5 V - 17 32 - 40 - 48 ns
VCC = 5.0 V; CL=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 27 - 34 - 41 ns
tttransition
time output; see Figure 7 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
MR input LOW; see Figure 8
VCC = 2.0 V 100 25 - 125 - 150 - ns
VCC = 4.5 V 20 9 - 25 - 30 - ns
VCC = 6.0 V 17 7 - 21 - 26 - ns
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 0 19 - 0 - 0 - ns
VCC = 4.5 V 0 7- 0 - 0 -ns
VCC = 6.0 V 0 6- 0 - 0 -ns
tsu set-up time Dn, CE to CP; see Figure 9
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
PE to CP; see Figure 9
VCC = 2.0 V 100 33 - 125 - 150 - ns
VCC = 4.5 V 20 12 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 10 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
thhold time Dn, CE to CP; see Figure 9
VCC = 2.0 V 2 8- 2 - 2 -ns
VCC = 4.5 V 2 3- 2 - 2 -ns
VCC = 6.0 V 2 2- 2 - 2 -ns
PE to CP; see Figure 9
VCC = 2.0 V 0 28 - 0 - 0 - ns
VCC = 4.5 V 0 10 - 0 - 0 - ns
VCC = 6.0 V 0 8- 0 - 0 - ns
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 6 19 - 4.8 - 4 - MHz
VCC = 4.5 V 30 57 - 24 - 20 - MHz
VCC = 5.0 V; CL=15pF - 63 - - - - - MHz
VCC = 6.0 V 35 68 - 28 - 24 - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -41- - - - - pF
74HCT166
tpd propagation
delay CP to Q7; see Figure 7 [1]
VCC = 4.5 V - 23 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 20 - - - - - ns
MR to Q7; see Figure 8
VCC = 4.5 V - 22 40 - 50 - 60 ns
VCC = 5.0 V; CL=15pF - 19 - - - - - ns
tttransition
time output; see Figure 7 [2]
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width CP input HIGH or LOW;
see Figure 7
VCC = 4.5 V 20 9 - 25 - 30 - ns
MR input LOW; see Figure 8
VCC = 4.5 V 25 11 - 31 - 38 - ns
trec recovery time MR to CP; see Figure 8
VCC = 4.5 V 0 7- 0 - 0 -ns
tsu set-up time Dn, CE to CP; see Figure 9
VCC = 4.5 V 16 8 - 20 - 24 - ns
PE to CP; see Figure 9
VCC = 4.5 V 30 15 - 38 - 45 - ns
thhold time Dn, CE to CP; see Figure 9
VCC = 4.5 V 0 3- 0 - 0 -ns
PE to CP; see Figure 9
VCC = 4.5 V 0 13 - 0 - 0 - ns
Table 7. Dynamic characteristics …continu ed
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 11 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11. Waveforms
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 25 45 - 20 - 17 - MHz
VCC = 5.0 V; CL=15pF - 50 - - - - - MHz
CPD power
dissipation
capacitance
per package;
VI=GNDtoV
CC
[3] -41- - - - - pF
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); tr = tf = 6 ns: CL = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock (CP) to output (Q7) propagation delays, pulse width, output transition times and maximum
frequency
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 12 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Master reset (MR) pulse width, MR to output (Q7) propagation delay and MR to clock (CP) recovery time.
aaa-008822
Q7 output
V
M
t
PHL
V
M
MR input V
M
t
W
V
I
GND
t
rec
V
I
V
OH
V
OL
GND
CP input
The shaded areas indicate when the input is permitted to change for predictable output performance
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW
Fig 9. Set-up an d hold times
aaa-008823
VM
VI
GND
VI
GND
VI
GND
VI
GND
VI
GND
VM
see note (1)
CE input
PE input
Dn input VM
VM
DS input
stable
VM
CP input
condition: MR = HIGH
stable
th
th
th
tsu tsu tsu
th
th
tsu
th
tsu
thtW
tsu
tsu
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 13 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Table 8. Measurement points
Type Input Output
VIVMVM
74HC166 VCC 0.5VCC 0.5VCC
74HCT166 3 V 1.3 V 1.3 V
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 10. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test da ta
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC166 VCC 6ns 15pF, 50 pF 1kopen
74HCT166 3V 6ns 15pF, 50 pF 1kopen
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 14 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
12. Package outline
Fig 11. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 15 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 12. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
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Product data sheet Rev. 3 — 11 September 2013 16 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 13. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 17 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Fig 14. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 18 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
13. Abbreviations
14. Revision history
Table 10. Abbr eviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT166_3 20130911 Product data sheet - 74HC_HCT166_CNV_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Family data added, see Section 9 “S tatic characteristics”
74HC_HCT166_CNV_2 December 1990 Product specification - -
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 19 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict wit h the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the applica tion or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT166 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 11 September 2013 20 of 21
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automo tive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting fr om customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specificat ions.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC166; 74HCT166
8-bit parallel-in/serial out shift register
© NXP B.V. 2013. All r ights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2013
Document identifier: 74HC_HCT166
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17 Contact information. . . . . . . . . . . . . . . . . . . . . 20
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21