©2001 Fairchild Semiconductor Corporation
November 2001
Rev. B, November 2001
IRFP240B
IRFP240B
200V N-Ch annel MOSFET
General Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary,
planar, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switching DC/DC converters,
switch mode power supplies, DC-AC converters for
uninterrupted power supply and motor control.
Features
20A, 200V, RDS(on) = 0.18 @VGS = 10 V
Low gate charge ( typical 45 nC)
Low Crss ( typical 45 pF)
Fast switching
100% avalanche tested
Improved dv/dt capability
Absolute Maxim um Ratings TC = 25°C unless otherwise noted
Thermal Char acteristics
Symbol Parameter IRFP240B Units
VDSS Drain-Source Voltage 200 V
IDDrain Current - Continuous (TC = 25°C) 20 A
- Continuous (TC = 100°C) 12.7 A
IDM Drain Current - Pulsed (Note 1) 80 A
VGSS Gate-Source Voltage ± 30 V
EAS Single Pulsed Avalanche Energy (Note 2) 250 mJ
IAR Avalanche Current (Note 1) 20 A
EAR Repetitive Avalanche Energy (Note 1) 18 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns
PDPower Dissipation (TC = 25°C) 180 W
- Derate above 25°C 1.45 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,
1/8" from case for 5 seconds 300 °C
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 0.69 °C/W
RθCS Thermal Resistance, Case-to-Sink 0.24 -- °C/W
RθJA Thermal Resistance, Junction-to-Ambient -- 40 °C/W
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D
G
TO-3P
IRFP Series
GSD
Rev. B, November 2001
IRFP240B
(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
©2001 Fairchild Semiconductor Corporation
Electrical Characteristics TC = 25°C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 0.94mH, IAS = 20A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C
3. ISD 18A, di/dt 300A/µs, VDD BVDSS, Starting TJ = 25°C
4. Pulse Test : Pulse width 300µs, Duty cycle 2%
5. Essentially independent of operating temperature
Symbol Parame ter Test Condit i ons Min Typ Max Units
Off Characteristics
BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, I D = 250 µA200 -- -- V
BVDSS
/ TJ
Breakdown Vo ltage Temperature
Coefficient ID = 250 µA, Referenced to 25°C -- 0.2 -- V/°C
IDSS Zero Gate Voltage Drain Current VDS = 200 V, VGS = 0 V -- -- 10 µA
VDS = 160 V, TC = 125°C -- -- 100 µA
IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA
On Characteri st ics
VGS(th) Gate Threshold Volt age VDS = VGS, ID = 250 µA2.0 -- 4.0 V
RDS(on) Static Drain-Source
On-Resistance VGS = 10 V , ID = 10 A -- 0.145 0.18
gFS Forward Transconductance VDS = 40 V, ID = 10 A -- 13.5 -- S
Dynamic Characteristics
Ciss Input Capacitance VDS = 25 V, VGS = 0 V,
f = 1.0 MHz
-- 1300 1700 pF
Coss Output Capacitance -- 175 230 pF
Crss Reverse Transfer Capacit ance -- 45 60 pF
Switching Characteristics
td(on) Turn-On Delay Time VDD = 100 V, ID = 18 A,
RG = 25
-- 20 50 ns
trTurn-On Rise Time -- 145 300 ns
td(off) Turn-Off De l a y Time -- 14 5 300 ns
tfTurn -Off Fa ll Time -- 110 23 0 n s
QgTotal Gate Ch arge VDS = 160 V, ID = 18 A,
VGS = 10 V
-- 45 58 nC
Qgs Gate-Source Charge -- 6.5 -- nC
Qgd Gate-Drain Charge -- 22 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
ISMaximum Continuous Drain-Source Diode Forward Current -- -- 20 A
ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 80 A
VSD Drain-Source Diode Forward V oltage VGS = 0 V, IS = 20 A -- -- 1.5 V
trr Reverse Recovery Time VGS = 0 V, I S = 18 A,
dIF / dt = 100 A/µs
-- 195 -- ns
Qrr Reverse Recovery Charge -- 1.47 -- µC
Rev. B, November 2001©2001 Fairchild Semiconductor Corporation
IRFP240B
10-1 100101
10-1
100
101
V GS
Top : 1 5 .0 V
1 0 .0 V
8 .0 V
7 .0 V
6 .5 V
6 .0 V
5 .5 V
Bottom : 5.0 V
$ No te s :
1. 250 %s P ulse Test
2. TC = 25&
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
0 102030405060
0.0
0.2
0.4
0.6
0.8
1.0
VGS = 20V
VGS = 10V
$ No te : TJ = 25&
RDS(ON) ['],
Drain-Source On-Resistance
ID, Drain Current [A]
246810
10-1
100
101
150oC
25oC
-55oC$ Notes :
1. VDS = 40V
2. 2 50%s Pulse Test
ID, Drain Current [A]
VGS, Gate-Source Voltage [V]
0 5 10 15 20 25 30 35 40 45 50
0
2
4
6
8
10
12
VDS = 100V
VDS = 40V
VDS = 160V
$ Note : ID = 18 A
VGS, Gate-Source Voltage [V]
QG, To ta l Gate C h ar ge [n C]
10-1 100101
0
500
1000
1500
2000
2500
3000
3500
Coss
Ciss = Cgs + Cgd (C ds = shorted)
Coss = Cds + Cgd
Crss = Cgd
$ No te s :
1. VGS = 0 V
2. f = 1 MH z
Crss
Ciss
Capacitance [pF]
VDS, Drain-Source Voltage [V]
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10-1
100
101
150&
$ No te s :
1. VGS = 0V
2. 2 50%s P u lse Te st
25&
IDR, Reverse Drain Current [A]
VSD, Source-Drain voltage [V]
Typical Characteristics
Figure 5. Capacitanc e C haracteri st i cs Figure 6. Gate Char ge Character is tics
Figure 3. On-Resistanc e Variation vs
Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage
Variation with Sour ce Cur r ent
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Charact er ist ic s
©2001 Fairchild Semiconductor Corporation Rev. B, November 2001
IRFP240B
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
$ Notes :
1 . Z(JC(t) = 0 .69 &/W Ma x .
2 . Du ty F a c tor, D = t1/t2
3 . TJM - TC = PDM * Z(JC(t)
s in g le p u ls e
D=0.5
0.02
0.2
0.05
0.1
0.01
Z(JC
(t), T he r ma l Re s po n s e
t1, S quare Wave Pulse Duration [sec]
25 50 75 100 125 150
0
4
8
12
16
20
ID, Drain Current [A]
TC, Case Temperature [&
]
100101102
10-1
100
101
102
DC
10 ms
1 ms
100 µs
Operation in This Area
is Limited by R DS(on)
$ No te s :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
ID, Drain Current [A]
VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
$
N o te s :
1 . V GS = 10 V
2 . ID = 9.0 A
RDS(ON) , (Normalized)
Drain-Source On-Resistance
TJ, Junction Tem perature [oC]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
$
N o te s :
1 . V GS = 0 V
2 . ID = 250 %A
BV DSS , (Norm alized)
Drain-Source Breakdown Voltage
TJ, Junction Tem perature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs Case Temperature
Figu re 7. Breakdown Volta g e Variat i o n
vs Temperature Figure 8. On-Resistance Variation
vs Temperature
Figure 11. Tr ansient Thermal Res pons e Cur ve
t1
PDM
t2
Rev. B, November 2001©2001 Fairchild Semiconductor Corporation
IRFP240B
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K)
200nF
12V
Same Type
as DUT
Charge
VGS
10V Qg
Qgs Qgd
3mA
VGS
DUT
VDS
300nF
50K)
200nF
12V
Same Type
as DUT
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
VGS
VDS
10%
90%
td(on) tr
ton toff
td(off) tf
VDD
10V
VDS RL
DUT
RG
VGS
EAS =LI
AS2
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
L
ID
t p
EAS =LI
AS2
----
2
1
EAS =LI
AS2
----
2
1
----
2
1--------------------
BVDSS -V
DD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
10V DUT
RG
LL
ID
ID
t p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
©2001 Fairchild Semiconductor Corporation Rev. B, November 2001
IRFP240B
Peak Diode Recover y dv/dt Test Circ ui t & Waveform s
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
L
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
DUT
VDS
+
_
Driver
RGSame Typ e
as DUT
VGS dv/dt controlled by RG
•I
SD con trolled by pulse per iod
VDD
LL
ISD
10V
VGS
( Driver )
ISD
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
VSD
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
D = Gate Pulse Width
Gate Pu lse P eri od
--------------------------
Rev. B, November 2001©2001 Fairchild Semiconductor Corporation
IRFP240B
Package Dimensions
15.60 ±0.20 4.80 ±0.20
13.60 ±0.20
9.60 ±0.20
2.00 ±0.20
3.00 ±0.20
1.00 ±0.20 1.40 ±0.20
ø3.20 ±0.10
3.80 ±0.20
13.90 ±0.20
3.50 ±0.20
16.50 ±0.30
12.76 ±0.20
19.90 ±0.20
23.40 ±0.20
18.70 ±0.20
1.50 +0.15
–0.05
0.60 +0.15
–0.05
5.45TYP
[5.45 ±0.30]5.45TYP
[5.45 ±0.30]
TO-3P
Dimensions in Millimeters
©2001 Fairchild Semiconductor Corporation
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY A NY LICENSE UNDER ITS PATENT RIGHTS, N OR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devic es or syst em s
which, (a) ar e intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconduct or reserv es the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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