HSP43220GM-15/883 - Intersil Corporation

File Number

2802.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

DECIMATE™ is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2™ are trademarks of IBM Corporation.

HSP43220/883

Decimating Digital Filter

The HSP43220/883 Decimating Digital Filter is a linear

phase low pass decimation ﬁlter which is optimized for

ﬁltering narrow band signals in a broad spectrum of a signal

processing applications. The HSP43220/883 offers a single

chip solution to signal processing application which have

historically required several boards of ICs. This reduction in

component count results in faster development times, as

well as reduction of hardware costs.

The HSP43220/883 is implemented as a two stage ﬁlter

structure. As seen in the Block Diagram, the ﬁrst stage is a

High Order Decimation Filter (HDF) which utilizes an

efﬁcient decimation (sample rate reduction) technique to

obtain decimation up to 1024 through a coarse low-pass

ﬁltering process. The HDF provides up to 96dB aliasing

rejection in the signal pass band. The second stage consists

of a Finite Impulse Response (FIR) decimation ﬁlter

structured as a transversal FIR ﬁlter with up to 512

symmetric taps which can implement ﬁlters with sharp

transition regions. The FIR can perform further decimation

by up to 16 if required, while preserving the 96dB aliasing

attenuation obtained by the HDF. The combined total

decimation capability is 16,384.

The HSP43220/883 accepts 16-bit parallel data in 2’s

complement format at sampling rates up to 30MSPS. It

provides a 16-bit microprocessor compatible interface to

simplify the task of programming and three-state outputs to

allow the connection of several ICs to a common bus. The

HSP43220/883 also provides the capability to bypass either

the HDF or the FIR for additional ﬂexibility.

Features

• This Circuit is Processed in Accordance to MIL-STD-883

and is Fully Conformant Under the Provisions of

Paragraph 1.2.1.

• Single Chip Narrow Band Filter with up to 96dB

Attenuation

• DC to 25.6MHz Clock Rate

• 16-Bit 2’s Complement Input

• 20-Bit Coefﬁcients in FIR

• 24-Bit Extended Precision Output

• Programmable Decimation up to a Maximum of 16,384

• Standard 16-Bit Microprocessor Interface

• Filter Design Software Available DECI•MATE™

Applications

• Very Narrow Band Filters

• Zoom Spectral Analysis

• Channelized Receivers

Block Diagram

Ordering Information

PART NUMBER TEMP.

RANGE (oC) PACKAGE PKG.

NO.

HSP43220GM-15/883 -55 to 125 84 Ld PGA

HSP43220GM-25/883 -55 to 125 84 Ld PGA

INPUT CLOCK

DATA INPUT DATA OUT

FIR CLOCK

DECIMATION UP TO 1024 DECIMATION UP TO 16

DATA READY

CONTROL AND COEFFICIENTS

FIR

DECIMATION

FILTER

HIGH ORDER

DECIMATION

FILTER

Data Sheet March 1999

Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

Input, Output Voltage . . . . . . . . . . . . . . . . . . . GND -5V to VCC 0.5V

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Operating Conditions

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to 5.5V

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PGA Package. . . . . . . . . . . . . . . . . . . . 32.9 7.2

Maximum Package Power Dissipation at 125oC

PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.52

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .175oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

Die Characteristics

Number of Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48,250

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Devices Guaranteed and 100% Tested

PARAMETER SYMBOL TEST

CONDITIONS

GROUP A

SUB-

GROUPS TEMP (oC)

LIMITS

UNITSMIN TYP

Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤TA≤ 125 2.2 - V

Logical Zero Input Voltage VIL VCC - 4.5V 1, 2, 3 -55 ≤TA≤ 125 - 0.8 V

Output HIGH Voltage VOH IOH = 400µA,

VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤TA≤ 125 2.6 - V

Output LOW Voltage VOL IOL = 2.0mA

VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤TA≤ 125 - 0.4 V

Input Leakage Current IIVIN = VCC or GND,

VCC = 5.5V 1, 2, 3 -55 ≤TA≤ 125 -10 +10 µA

Output Leakage Current IOVOUT = VCC or GND,

VCC = 5.5V 1, 2, 3 -55 ≤TA≤ 125 -10 +10 µA

Clock Input High VIHC VCC = 5.5V 1, 2, 3 -55 ≤TA≤ 125 3.0 - V

Clock Input Low VILC VCC = 4.5V 1, 2, 3 -55 ≤TA≤ 125 - 0.8 V

Standby Power Supply Current ICCSB VIN = VCC or GND,

VCC = 5.5V,

Outputs Open

1, 2, 3 -55 ≤TA≤ 125 - 500 µA

Operating Power Supply Current ICCOP f = 15.0MHz,

VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤TA≤ 125 - 120 mA

Functional Test FT (Note 4) 7, 8 -55 ≤TA≤ 125 - -

NOTES:

2. Interchanging of force and sense conditions is permitted.

3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz.

4. Tested as follows: f = 1MHz, VIH = 2.6, VIL = 0.4, VOH ≥1.5V, VOL ≤ 1.5V, VIHC = 3.4V and VILC = 0.4V.

HSP43220/883

TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS

Devices Guaranteed and 100% Tested

PARAMETER SYMBOL (NOTES)

(NOTE 5)

GROUP A

SUB-

GROUPS TEMP (oC)

-15 (15MHz) -25 (25.6MHz)

UNITSMIN MAX MIN MAX

Input Clock Period tCK 9, 10, 11 -55 ≤ TA≤ 125 66 - 39 - ns

FIR Clock Period tFIR 9, 10, 11 -55 ≤ TA≤ 125 66 - 39 - ns

Clock Pulse Width Low tSPWL 9, 10, 11 -55 ≤ TA≤ 125 26 - 16 - ns

Clock Pulse Width High tSPWH 9, 10, 11 -55 ≤ TA≤ 125 26 - 16 - ns

Clock Skew Between

FIR_CLK and CK_IN tSK 9, 10, 11 -55 ≤ TA≤ 125 0 TFIR -25 0 TFIR -19 ns

RESET Pulse Width Low tRSPW 9, 10, 11 -55 ≤ TA≤ 125 4 TCK -4 T

CK -ns

Recovery Time On

RESET tRTRS 9, 10, 11 -55 ≤ TA≤ 125 8 TCK -8 T

CK -ns

ASTARTIN Pulse Width

Low tAST 9, 10, 11 -55 ≤ TA≤ 125 TCK +10 - TCK +10 - ns

STARTOUT Delay From

CK_IN tSTOD 9, 10, 11 -55 ≤ TA≤ 125 - 35 - 20 ns

STARTIN Setup to

CK _IN tSTIC 9, 10, 11 -55 ≤ TA≤ 125 25 - 15 - ns

Setup Time on DATA_IN tSET 9, 10, 11 -55 ≤ TA≤ 125 20 - 16 - ns

Hold Time on All Inputs tHOLD 9, 10, 11 -55 ≤ TA≤ 125 0 - 0 - ns

Write Pulse Width Low tWL 9, 10, 11 -55 ≤ TA≤ 125 26 - 15 - ns

Write pulse Width High tWH 9, 10, 11 -55 ≤ TA≤ 125 26 - 20 - ns

Setup Time on Address

Bus Before the Rising

Edge of Write

tSTADD 9, 10, 11 -55 ≤ TA≤ 125 28 - 24 - ns

Setup Time on Chip

Select Before the

Rising Edge of Write

tSTCS 9, 10, 11 -55 ≤ TA≤ 125 28 - 24 - ns

Setup Time on Control

Bus Before the Rising

Edge of Write

tSTCB 9, 10, 11 -55 ≤ TA≤ 125 28 - 24 - ns

DATA_RDY Pulse Width

Low tDRPWL 9, 10, 11 -55 ≤ TA≤ 125 2TFIR -20 - 2TFIR -10 - ns

DATA_OUT Delay

Relative to FIR_CK tFIRDV 9, 10, 11 -55 ≤ TA≤ 125 - 50 - 35 ns

DATA_RDY Valid Delay

Relative to FIR_CK tFIRDR 9, 10, 11 -55 ≤ TA≤ 125 - 35 - 25 ns

DATA_OUT Delay

Relative to OUT_SELH tOUT 9, 10, 11 -55 ≤ TA≤ 125 - 30 - 25 ns

Output Enable to

Data Out Valid tOEV Note 6 9, 10, 11 -55 ≤ TA≤ 125 - 20 - 20 ns

NOTES:

5. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are

made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V.

6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF.

HSP43220/883

TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

Devices Guaranteed and 100% Tested

PARAMETER SYMBOL TEST

CONDITIONS NOTES TEMP (oC)

-15 (15MHz) -25 (25.6MHz)

UNITSMIN MAX MIN MAX

CK_IN Pulse Width Low tCH1L 7, 9 -55 ≤TA≤ 125 29 - 19 - ns

CK_IN Pulse Width High tCH1H 7, 9 -55 ≤TA≤ 125 29 - 19 - ns

CK_IN Setup to FIR_CK tCIS 7, 9 -55 ≤TA≤ 125 27 - 17 - ns

CK_IN Hold from FIR_CK tCIH 7, 9 -55 ≤TA≤ 125 2 - 2 - ns

Input Capacitance CIN VCC = Open, f = 1MHz,

All measurements are

referenced to device

GND

A = 25oC - 12 - 12 pF

Output Capacitance COUT VCC = Open, f = 1MHz,

All measurements are

referenced to device

GND

A = 25oC - 10 - 10 pF

Output Disable Delay tOEZ 7, 8 -55 ≤TA≤ 125 - 20 - 20 ns

Output Rise Time tOR 7, 8 -55 ≤TA≤ 125 - 8 - 8 ns

Output Fall Time tOF 7, 8 -55 ≤TA≤ 125 - 8 - 8 ns

NOTES:

7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized

upon initial design and after major process and/or design changes.

8. Loading is as specified in the test load circuit with CL = 40pF.

9. Applies only when H_BYP = 1 or H_DRATE = 0.

TABLE 4. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS METHOD SUBGROUPS

Initial Test 100%/5004 -

Interim Test 100%/5004 -

PDA 100% 1

Final Test 100% 2, 3, 8A, 8B, 10, 11

Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11

Groups C and D Samples/5005 1, 7, 9

HSP43220/883

Burn-In Circuit

HSP43220/883

TOP VIEW

PINS DOWN

DATA_ VCC GND

START CLK_IN VCC

ASTART VCC

A1 RESET

CS WR

VCC

GND

GND GND

VCC GND

VCC

2173456 891011

GND

IN 1 DATA_

IN 2 DATA_

IN 4 DATA_

IN 7 DATA_

IN 8 DATA_

IN 11 DATA_

IN 14

IN START

OUT DATA_

IN 0 DATA_

IN 3 DATA_

IN 6 DATA_

IN 13 DATA_

IN 12 DATA_

IN 15 DATA_

OUT 1

IN DATA_

IN 0 DATA_

IN 9 DATA_

IN 10 DATA_

OUT 0 DATA_

OUT 2

DATA_

OUT 3 DATA_

OUT 4

A0 DATA_

OUT 7

DATA_

OUT 5 DATA_

OUT 3

C_BUS

10 C_BUS

15 C_BUS

14 DATA_

OUT 9 DATA_

OUT 8

C_BUS

12 DATA_

OUT 10 DATA_

OUT 11

C_BUS

9VCC DATA_

OUT 12

DATA_

OUT 13

C_BUS

7OUT_

SELH FIR_

CK DATA_

OUT 16 DATA_

OUT 14

C_BUS

8C_BUS

5C_BUS

4C_BUS

1OUT_

EMP DATA_

OUT 15

DATA_

OUT 17

DATA_

OUT 19

DATA_

OUT 22

C_BUS

6C_BUS

3C_BUS

2C_BUS

0OUT_

ENX DATA_

RDY DATA_

OUT 23 DATA_

OUT 21 DATA_

OUT 20 DATA_

OUT 18

GND

BURN-IN CIRCUIT SIGNALS

PIN LEAD PIN NAME BURN-IN

SIGNAL PIN LEAD PIN NAME BURN-IN

SIGNAL

A1 GND GND C1 ASTARTIN F15 F11 DATA_OUT 3 VCC/2

A2 DATA_IN 1 F2 C2 VCC VCC G1 C_BUS 12 F5

A3 DATA_IN 2 F3 C5 DATA_IN 5 F6 G2 C_BUS 11 F4

A4 DATA_IN 4 F5 C6 DATA_IN 9 F2 G3 C_BUS 13 F6

A5 DATA_IN 7 F8 C7 DATA_IN 10 F3 G9 DATA_OUT 10 VCC/2

A6 DATA_IN 8 F1 C10 DATA_OUT 0 VCC/2 G10 GND GND

A7 DATA_IN 11 F4 C11 DATA_OUT 2 VCC/2 G11 DATA_OUT 11 VCC/2

A8 DATA_IN 14 F7 D1 A1 F14 HI C_BUS 9 F2

A9 VCC VCC D2 RESET F16 H2 VCC VCC

A10 GND GND D10 DATA_OUT 3 VCC/2 H10 DATA_OUT 13 VCC/2

A11 GND GND D11 DATA_OUT 4 VCC/2 H11 DATA_OUT 12 VCC/2

B1 STARTIN F15 E1 CS F11 J1 GND GND

B2 STARTOUT VCC/2 E2 WR F11 J2 C_BUS 7 F8

B3 DATA_IN 0 F1 E3 A0 F13 J5 OUT_SEL F10

B4 DATA_IN 3 F4 E9 DATA_OUT 5 VCC/2 J6 GND GND

B5 DATA_IN 6 F7 E10 DATA_OUT 6 VCC/2 J8 FIR_CK F0

HSP43220/883

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products , see web site http://www.intersil.com

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Metal Topology

DIE DIMENSIONS:

348 x 349.2 x 19 ±1 mils

METALLIZATION:

Type: Si - Al, or Si - Al - Cu

Thickness: 8kÅ

WORST CASE CURRENT DENSITY:

1.18 x 105A/cm2

GLASSIVATION:

Type: Nitrox

Thickness: 10kÅ

B6 DATA_IN 13 F6 E11 DATA_OUT 7 VCC/2 J10 DATA_OUT 16 VCC/2

B7 DATA_IN 12 F5 F1 C_BUS 10 F3 J11 DATA_OUT 14 VCC/2

B8 DATA_IN 15 F8 F2 C_BUS 15 F8 K1 C_BUS 8 F1

B9 CK_IN F0 F3 C_BUS 14 F7 K2 C_BUS 5 F6

B10 VCC VCC F9 DATA_OUT9 VCC/2 K3 C_BUS 4 F5

B11 DAT_OUT 1 VCC/2 F10 VCC VCC K4 C_BUS 1 F2

K5 OUT_ENP F9 K11 DATA_OUT 15 VCC/2 L6 DATA_RDYV

CC/2

K6 VCC VCC L1 C_BUS 6 F7 L7 VCC VCC

K7 GND GND L2 C_BUS 3 F4 L8 DATA_OUT 23 VCC/2

K8 DATA_OUT 22 VCC/2 L3 C_BUS 2 F3 L9 DATA_OUT 21 VCC/2

K9 DATA_OUT 19 VCC/2 L4 C_BUS 0 F1 L10 DATA_OUT 20 VCC/2

K10 DATA_OUT 17 VCC/2 L5 OUT_ENX F9 L11 DATA_OUT 18 VCC/2

NOTES:

10. VCC/2 (2.7 ±10%) used for outputs only.

11. 47kΩ (±20%) resistor connected to all pins except VCC and GND.

12. VCC = 5.5 ±0.5V.

13. 0.1µF (minimum) capacitor between VCC and GND per position.

14. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2....F16 = F15/2, 40% - 60% duty cycle.

15. Input voltage limits: VIL = 0.8 maximum, VIH = 4.5V ±10%.

BURN-IN CIRCUIT SIGNALS (CONTINUED)

PIN LEAD PIN NAME BURN-IN

SIGNAL PIN LEAD PIN NAME BURN-IN

SIGNAL

HSP43220/883