Evaluation Board For AD7682/89/99/7949
PulSAR® ADCs
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator and buffers
EVAL-CONTROL BRD3Z compatibility
PC software for control and data analysis of time and
frequency domain
GENERAL DESCRIPTION
The EVAL-AD76MUXCBZ is an evaluation board for the
PulSAR AD7682, AD7689, AD7699, and AD7949 14-bit and
16-bit PulSAR analog to digital converter (ADC) family. These
low power, successive approximation register (SAR) architect-
ture ADCs (see Ordering Guide for product list) offer very high
performance with up to 500kSPS throughput rate and 4 – 8
channels. The evaluation board is designed to demonstrate the
ADC's performance and to provide an easy to understand
interface for a variety of system applications. A full description
of the AD7682, AD7689, AD7699, and AD7949 is available in at
www.analog.com and should be consulted when utilizing this
evaluation board.
The evaluation board must be used in conjunction with the
Analog Devices EVAL-CONTROL BRD3Z 16-bit parallel DSP
interface board. Since the ADC’s being evaluated are serial
interface only, the EVAL-AD76MUXCBZ contains the
necessary logic to perform serial to parallel conversion for this
interface.
On-board components include a high precision band gap
reference, (ADR435), reference buffers, 8-signal conditioning
circuits with an op amp and an FGPA for digital logic. Also
included are separate low drop out regulators for supplying
special voltages of 1.2V and 7V which are not available from the
EVAL-CONTRL BRD3Z.
The board interfaces to the EVAL-CONTROL-BRD3Z with a
96-pin DIN connector. J1, J2 SMB connectors are provided for
the low noise analog signal source for CH0 and CH1 with the
remaining channels (and CH0/1) available on an IDC
connector, P1. J3 can be used for providing an external common
(COM) or configured for any input channel.
Figure 1.Evaluation Board
Analog
Inputs
Signal conditioning Reference Source, COM Select
ADC
FPGA
External COM
(or Input)
40-Pin IDC Header
96-Pin EVAL-CONTROL BRD3Z
Interface
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Revision History ............................................................................... 2
Overview........................................................................................ 3
Conversion Control...................................................................... 3
Analog Inputs................................................................................ 3
Serial Interface .............................................................................. 3
Reference ....................................................................................... 3
Power Supplies and Grounding.................................................. 3
Schematics/PCB Layout............................................................... 3
Hardware Setup .............................................................................3
Software Installation.....................................................................4
Running the Evaluation Software ..............................................4
Setup Screen...................................................................................4
Configuring the ADC ...................................................................4
DC Testing - Histogram ...............................................................4
AC Testing......................................................................................4
Decimated AC Testing (Averaging)............................................4
Ordering Guide .......................................................................... 24
LIST OF FIGURES
Figure 1.Evaluation Board............................................................... 1
Figure 2. Schematic, ADC + Block Diagram................................. 7
Figure 3. Schematic, Supplies .......................................................... 8
Figure 4. Schematic, Reference, Buffer, VCM, VBIAS......................... 9
Figure 5. Schematic, AnalogCH0-CH3........................................ 10
Figure 6. Schematic, AnalogCH4-CH7........................................ 11
Figure 7. Schematic, FPGA............................................................ 12
Figure 8. Schematic, 96-Pin Interface........................................... 13
Figure 9. Top Side Silk-Screen....................................................... 14
Figure 10. Inner Layer 1................................................................. 14
Figure 11. Ground Plane................................................................ 15
Figure 12. Inner Layer 2................................................................. 15
Figure 13.Inner Layer 3.................................................................. 16
Figure 14. Bottom Layer ................................................................ 16
Figure 15. Bottom Layer ................................................................ 17
Figure 16. Setup Screen.................................................................. 18
Figure 17. Input Configuration..................................................... 19
Figure 18. Reference Selection...................................................... 19
Figure 19.Channel Select............................................................... 19
Figure 20. Temperature Sensor ..................................................... 19
Figure 21. Low Pass Filter.............................................................. 19
Figure 22. Histogram Screen......................................................... 20
Figure 23. FFT Screen .................................................................... 21
Figure 24. Time-Domain Screen .................................................. 22
Figure 25. Decimated (Averaging) Screen................................... 23
LIST OF TABLES
Table 1. Jumper Description............................................................ 5
Table 2.Test Points ............................................................................ 6
Table 3. Bill of Materials for the Connectors .................................6
REVISION HISTORY
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 3 of 24
OVERVIEW
Figure 1 shows the EVAL-AD76MUXCBZ evaluation board.
When used in conjunction with the EVAL-CONTROL BRD3Z,
the FPGA, U6, provides the necessary control signals for
conversion and buffers the ADC serial output data into 16-bit
wide transfers. The evaluation board is a flexible design that
enables the user to choose among many different board
configurations, analog signal conditioning, reference, and
different interfaces for conversion results.
CONVERSION CONTROL
Conversion start (CNV) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
generated internally. CNV is generated by the gate array and the
frequency is selected with the software.
While the ADC is converting, activity is indicated by the green
LED, CR1. Operating the software in Burst mode as opposed to
Continuous mode, will only light the LED when conversion is
taking place.
ANALOG INPUTS
SMB connectors, J1 and J2, are provided for the ADC input
channels IN0 and IN1 (IN0 only on AD7682). These inputs are
also on the IDC connector P1-2 and P1-4. The remaining inputs
are also on P1-6 through P1-16 (even pins only). J3 can be
configured for providing a common point (COM) for all input
signals or for any analog input IN0-IN7. For using J3 as an
external common point, remove the solder pad (bottom of
PCB) from “COMS to COM” and solder “EXT_COM to COM”
as shown below.
To configure J3 to drive any of the analog input channels,
remove R35 from the left pads (bottom of PCB) and solder it to
the rightmost pads.
The analog input amplifier circuitry U13 – U20 (see schematic -
Figure 2) allows flexible configuration changes such as positive
or negative gain, input range scaling, filtering, addition of a DC
component, use of different op-amp and supplies. The analog
input amplifiers are set as unity gain buffers at the factory. The
supplies are selectable with solder pads VDRV- and VDRV+
and are set for the +7V, -5V range.
Note that when using the unipolar configuration, COMS (P8) is
set to (P8, 2-3) and for bipolar input configuration set to (P8, 1-
2) with pin 1 being the leftmost pin.
SERIAL INTERFACE
The 3-wire serial interface DIN, SCK, and SDO along with CNV
are present on test points. FPGA buffered versions are on 40-pin
IDC connector, P3 pins 2, 4, 6 and 8.
REFERENCE
All of the ADCs for this evaluation board can use a precision
trimmed on-chip band gap reference, an on-board precision
ADR435 band gap reference, or an external reference connected
to the EXTREF test point (TP17). The on-chip reference is
enabled or disabled with the software. The on-chip reference
can be set for 2.5V or 4.096V outputs and also includes an
internal buffer, useful for external reference applications. When
using the on-chip reference, remove the jumper on TP7 since
this will overdrive the on-chip reference with the external one.
The default configuration is for on-board ADR435 reference
with a buffered output (P5 2-3), (P6 1-2) and (P7 1-2).
For using an external reference connect to the EXTREF test
point (TP17), select a buffer or not with P6 and select if driving
the ADC REF directly or using the ADC’s internal reference
buffer. When using the internal reference buffer with gain=1,
the maximum output is limited to 4.096V (headroom from 5V
supply).
The default configuration sets the amplifiers output to be at
VREF/2 (mid-scale) from the voltage divider at U1B (VBIAS).
POWER SUPPLIES AND GROUNDING
To attain high resolution performance, the board was designed
to ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CONTROL-BRDXZ
SCHEMATICS/PCB LAYOUT
The EVAL-AD76MUXCBZ is a 6-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the ADC. Figure 2 through Figure 8 shows the
schematics of the evaluation board. The silkscreens for the PCB
are given in Figure 9 and Figure 11.
HARDWARE SETUP
System Requirements
• Evaluation Board
• Evaluation Control Board 3, EVAL-CONTROL BRD3Z
• AC Power Supply (AC 14V/1A source - can be purchased
from ADI)
• IEEE 1284 Compliant Parallel Port Cable (if not supplied)
• DC source (low noise for checking different input ranges)
• AC source (low distortion)
• Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 4 of 24
• PC operating Windows 2000 or XP.
Connect the control board supplied mini plug to the 14V AC
source. Connect the evaluation board to the controller board
and connect the parallel port cable to the evaluation board and
to the PC .Software Installation
Double-Click on setup.exe from the CD-ROM and follow the
installation instructions. If upgrading the software, the previous
version will first be removed. Thus setup.exe will need to be run
again to install the new version. When asked to install the
“GIVEIO” driver, click on yes to install. You must reboot the
computer for the drivers to load properly.
SOFTWARE INSTALLATION
Double-Click on setup.exe from the CD-ROM and follow the
installation instructions. When asked to install the “GIVEIO”
driver, click on yes to install. You must reboot the computer for
the drivers to load properly. If this message is displayed:
Click OK and run GIVEIO from <local drive>:\Program
Files\Analog Devices\Hi-Res Mux ADC's x.x and reboot the
computer.
RUNNING THE EVALUATION SOFTWARE
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-
CONTROL-BRDX is required when using the software. The
software is used to perform the following tests:
• Histogram for determining code transition noise (DC)
• Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
• Decimation (digital filtering)
The default configuration loads the software into <local
drive>:\Program Files\Analog Devices\Hi-Res ADC's Mux
x.x\ADC Eval SW MUX.exe. This can also be accessed from the
Start button and selecting: All Programs -> Analog Devices Hi-
Res MUX ADC’s Evaluation Software x.x -> ADC Eval SW
MUX.
The software has four screens as shown in Figure 22 through
Figure 25.
SETUP SCREEN
Figure 16 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
CONFIGURING THE ADC
These ADCs need to be configured through a dedicated SPI
compatible serial port. The included SW configures the part to a
default configuration. Each of the different configurable
parameters are shown in Figure 17.to Figure 21.
DC TESTING - HISTOGRAM
Figure 22 is the histogram screen, which tests the code
distribution for DC input and computes the mean and standard
deviation or transition noise. To perform a histogram test, select
“Histogram” from the test selection window and click on the
“Start” radio button. Note: a histogram test can be performed
without an external source since the evaluation board has a
buffered VREF/2 source at the ADC input. To test other DC
values, apply a source to the J1/J2/P1-x inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC.
AC TESTING
Figure 23 is the FFT screen, which performs an FFT on the
captured data and computes the SNR, SINAD, THD and SFDR.
Figure 24 is the time domain representation of the output. To
perform an AC test, apply a sinusoidal signal to the evaluation
board at the SMB inputs J1 for CH0 and J2 for CH1. Low
distortion, better than 100dB, is required to allow true
evaluation of the part. One possibility is to filter the input signal
from the AC source. There is no suggested bandpass filter but
consideration should be taken in the choice. Furthermore, if
using a low frequency bandpass filter when the full-scale input
range is more than a few Vpp, it is recommended to use the on
board amplifiers to amplify the signal, thus preventing the filter
from distorting the input signal.
DECIMATED AC TESTING (AVERAGING)
The AC performances can be evaluated after digital filtering
with enhanced resolution of up to 32 bits. Figure 25 is the FFT
screen when decimation is used. Additional bits of resolution
are attained when over sampling by:
SAMPLE
N
OVERSAMPLE f*f 4
=
where , N = number of bits and 4N.= the DRATIO. Set the
DRATIO to the amount of over sampling desired. When using
decimation, the test duration increases with the larger number
of samples taken. The decimated test requires the EVAL-
CONTROL-BRD3Z
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 5 of 24
Table 1. Jumper Description
Jumper Name Default
Position
Function
P5 - REFS Reference source selection.
REFS to middle pin: uses ADR435 (A1) 5V, 4.096V or 2.5V output.
VDD to middle pin: VDD supply is used as a reference.
Open: optional source can be connected to TP17/VREF.
P6 - BUF Reference buffer selection.
BUF to middle pin: buffer selection from P5 with the AD8032-A (U2).
NOBUFF to middle pin: use P5 direct (no buffer).
P7 REF/REFIN REF ADC REF/REFIN input selection.
REF to middle pin: external source drives ADC REF pin.
REFIN to middle pin: external source drives REFIN, reference buffer input pin
Open: When using the on-chip reference.
P8 COMS VCM Common channel select.
VCM to middle pin: for bipolar mode, selects VREF/2.
GND to middle pin: for unipolar operation, selects GND.
JP9 5V 5V External reference selection of 5V.
JP10 4.096V Open External reference selection of 4.096V.
JP11 2.5V Open External reference selection of 2.5V.
SB0-7 BUF Select BUF Use on-board analog amplifiers (U13 – U20)
BUF: use amplifier
NO BUF: bypass amplifier
- VDRV- -5V Amplifiers (U13-U20) (-) supply.
- VDRV+ 7V Amplifiers (U13-U20) (+) supply.
- VCCREF 12V ADR435(A1) (+) supply.
- VDDR 5V ADC (U7) VDD supply. Must always be the same as VDD.
- VDD 5V ADC (U7) VDD supply.
- VIO 3.3V ADC (U7) VIO interface supply.
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 6 of 24
Table 2.Test Points
Test
Point
Available
Signal
Type Description
TP13 VDD P ADC (U7) VDD supply.
TP14 VDDR P ADC (U7) VDD supply. Must always be = AVDD above.
TP15 VIO P ADC (U7) VIO interface supply.
TP17 VREF AI External reference input.
TP18 REF AI/O ADC on-chip reference output or external reference input.
TP19 REFIN AI/O ADC on-chip band-gap output or external reference input when using on-chip reference
buffer.
TP20 IN0 AI Analog input for ADC IN0 on both 4 and 8-cahhel ADCs.
TP21 IN1 AI Analog input for channel 1 on 8-channel ADCs only.
TP22 COM AI Sets the level on ADC COM; GND or VREF/2.
TP24 SDO DO Serial data output from ADC.
TP25 SCK DI Serial clock data input to ADC.
TP26 DIN DI Serial data input for part configuration.
TP27 CNV DI Conversion input to ADC
Table 3. Bill of Materials for the Connectors
Ref Des Connector Type Manf. Part No.
J1, J2, J3 RT Angle SMB Male Pasternack PE4177
P1 0.100 X 0.100 straight IDC header 2X10 3M 2540-6002UB
P2 0.100 X 0.100 straight IDC header 2X20 3M 2540-6002UB
P4 32X3 RT PC MOUNT CONNECTOR ERNI 533402
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 7 of 24
BOTTOM
BOTTOM
TOP
BOTTOM
BOTTOM
BOTTOM
1
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
ad7689_csp_t opl evel
PAD
9
8
7
6
5
4
3
20
2
19
18
17
16
15
14
13
12
11
10
1
U7
1
TP7 4
1
TP71
C2
1
TP2
1
TP3
1
TP4
1
TP5
1
TP6
1
TP7
1
TP8
1
TP1
2
1
C1
2
1
C3
2
1
C4
2
1
C6
2
1
C5
0. 1UF
0. 1UF
10UF
BLKBLK
GND
0. 1UF
0. 1UF
BLK
BLKBLKBLK
BL K BL K
BLKBLK
TBD0805
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THEEQUIPMENTSHOWNHEREONMAY BE PROTECTED BY PATENTS
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
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PTDE ENGI NEER
DRAWING NO.
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BCS_ N
DSPCL K
CONTRO L
RESE T
BWR_ N
BRD_ N
BBUSY
+5VA
-12VA
+12VA
-5VA
GND
VDI G
GND
GND
GND
FPGA
VI O_ F PGA
EN_3. 3V_N
VFPGA
VPLLA2
VPLLA1
RESE T
CONTRO L
DSPCL K
BBUSY
BWR_ N
BRD_ N
BCS_ N
EN_7V_N
EN_5V_N
SCK
DI N
CNV
SDO
BD<0. . 15 >
VI O
AD<0. . 4 >
GND
ANALO G
REFI N
IN0/IN0
IN1
IN2/IN1
IN3
IN4
IN5/IN2
IN6
IN7/IN3
VDD
VDRV +
REF
COM
VCCRE F
VDRV -
POWER
VFPGA
VPLLA 2
VPLLA 1
VI O_FPG A
+12V A
+5VA
EN_3. 3V_ N
EN_5V_ N
EN_7V_ N
VCCRE F
VDD
VI O
VDDR
VDRV-
VDRV+
-5VA
VDI G
Figure 2. Schematic, ADC + Block Diagram
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 8 of 24
VI O
+12VA+5VAGND-5VA
EXT
VDD
VDDR
LDO ADJUSTED TO 1. 2V
L DO ADJ UST E D T O 1 . 2 V
LDO ADJUSTED TO 1. 2V
REGULATES FPGA VI O SUPPLI ES TO 3. 3V ( MAX ALLOWED)
ANALOG SUPPLI ES
FPGA SUPPLI ES
SUPPLY OPTI ONS
2
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
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powe r
2
1
P9
C7
6
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2
1
8
7
5
3
U8
R56
C8
R5 5
C9
1
TP39
1
TP38
1
TP40
1
TP42
1
TP41
1
TP43
1
TP46
1
TP45
1
TP44
1
TP47
1
TP36
1
TP35
1
TP37
1
TP33
1
TP34
1
TP32
1
TP31
1
TP30
1
TP29
1
TP28
1
TP7 6
1
TP1 6
1
TP11
1
TP1 2
1
TP9
1
TP1 0
1
TP1 5
1
TP1 4
1
TP1 3
C1 4
C1 5
C1 6
C1 3
C1 2
C11
6
PAD
2
1
8
7
5
3
U1 2
C34
C28 C27
C33 C32
C26
2
1
C17
2
1
R2
3
2
8
7
65
1
4
U9
2
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R1
2
1
C20
2
1
C23
2
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R7
2
1
R8
2
1
R9
2
1
R1 9
2
1
R21
2
1
R2 0
2
1
R1 2
2
1
R11
2
1
R1 0
2
1
C21
2
1
C18
2
1
C19
2
1
C22
2
1
R18
2
1
R17
2
1
R14
2
1
R16
2
1
R6
3
2
8
7
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1
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2
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R5
2
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R4
3
2
8
7
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U1 0
2
1
R3
2
1
C25
2
1
C24
2
1
C29
2
1
R1 3
6
PAD
2
1
8
7
5
3
U4
2
1
C31
2
1
R15
6
PAD
2
1
8
7
5
3
U3
2
1
C30
RED
BLU
+5V
+12VA
VCCREF
GND
VDRV-
+5V
+7V
VDRV+
+12VA
10UF
REDRED
RED
RED
RED
RED
10UF
REDREDRED
10UF
2. 2UF
0. 1UF
2. 2UF
78. 7K
1000PF
140K
VDI G
VDI G
VDI G
VDI G
RED
2. 2UF
ADP3334ACPZ
VI O_ F PGA
VPLLA2
VPLLA1
VFPGA
VCCREF
VDDR
VDD
VI O
VDRV-
VDRV+
EN_7V_N
EN_5V_N
EN_3. 3V_N
VDI G
-5VA
+5VA
+12VA
AV21+AV5+AV5-TXE
VI O
VDDR
VDD
YEL WHT
BL K
RED
RED
REDREDRED
DERDER
RED RED
RED
RED
10UF
10UF
10UF
BLU
2K
2. 2UF
1K
0
0. 1UF
2. 2UF
1K
2K
1K
ADP1715ARMZ- R7
0
2. 2UF
0. 1UF
0
VI O_ F PGA
+7V
+5V
VI O_ F PGA
+3. 3V
EN_7V_N
EN_5V_N
+12VA
+12VA
EN_3. 3V_N
+5VA
10K
10K
2. 2UF
ADP3334ACPZ
60. 4K
1000PF
300K
2. 2UF
ADP3334ACPZ
64. 9K
1000PF
210K
2. 2UF
0
0
10K
2. 2UF
ADP3334ACPZ
78. 7K
1000PF
140K
2. 2UF
0
VI O_FPGA
VI O_ F PGA
VPLLA2
ADP1715ARMZ- R7
ADP1715ARMZ- R7
2. 2UF
2. 2UF
2K
VPLLA1
VFPGA
2. 2UF
BLU
+7V
-5VA
+5V
+5V
EXT
EXT
EXT
+3. 3V
RED
DESI GNVIEW
ORFORANYOTHERPURPOSE DE TRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
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B
CC
D
5
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RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROTECTED BY PATENTS
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
GND
GND
OUT
GND
IN1
IN2
OUT2
OUT1
PAD FB
GND
SD*
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN1
IN2
OUT2
OUT1
PAD FB
GND
SD*
OUT
IN1
IN2
OUT2
OUT1
PAD FB
GND
SD*
GND
GND
GND
IN1
IN2
OUT2
OUT1
PAD FB
GND
SD*
GND
GND
GND
OUT
ADJ GND
EN
IN
OUT
GND
GND
GND
GND
OUT
OUT GND
GND
OUT
ADJ GND
EN
IN
OUT
ADJ GND
EN
IN
OUT
Figure 3. Schematic, Supplies
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 9 of 24
4. 096V
REFS
VREF
VDD
VREF
2. 5V
REF
REF
5V
BI ASI NG USI NG ADC REF
REFI N
REFI N
BUF
NOBUF
EXTERNAL REFERENCE OPTI ONS
3
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
2
1
JP9
C37
C4 0
C4 2
1
3
2
U1
2
1
JP11
2
1
JP10
C35
C3 8
C4 5
C4 3
C4 1
1
TP1 9
1
TP1 7
1
TP1 8
R2 2
4
8
U2
1
3
2
U2
R3 0
R32
R2 9
R2 8
R2 6
2
1
R2 7
2
1
C36
6
2
5
8
1
7
3
4
A1
2
1
R2 3
2
1
R24
2
1
R25
3
2
1
P5
2
1
C3 9
3
2
1
P6
3
2
1
P7
7
5
6
U2
4
8
U1
2
1
C4 4
2
1
R31
2
1
R33
7
5
6
U1
VCCREF
TBD0805
1K
AD8032ARZ
0. 1UF
10K
REFI N
VDD
2. 2UF
REFI N
REF
VCCREF
10K
TBD0805
0
10UF
0. 1UF
ADR435BRZ
45. 3K
1K
AD8032ARZ
1K
YEL
BLU
AD8032ARZ
AD8032ARZ
AD8032ARZ
AD8032ARZ
VCCREF
VBI AS
VCM
REF
VDD
10K
10K
10K
10K
0. 1UF
10UF
10UF
10UF 10UF
10UF
BLU
VCCREF
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
REV
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDORCONTROLLEDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWN HEREONMAY BE PROTECT EDBYPATENTS
IN PART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
V-
V+
GND
GND
GND
OUT
OUT
GND
TRI M
VI N
GND
NC1
TP
NC2
TP1
VOUT
GND
GND
V-
V+
GND GND GND
GND GND
Figure 4. Schematic, Reference, Buffer, VCM, VBIAS
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 10 of 24
IN0/IN0
IN1
ADC BUFFERS
4
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
54
3
2
1
J3
R4 9R3 5
1
TP52
1
TP53
1
TP51
1
TP49
1
TP50
1
TP48
1
TP58
1
TP59
1
TP57
1
TP56
1
TP55
1
TP54
R157 R156
9
8
7
6
5
4
3
2
16
15
14
13
12
11
10
1
P1
C4 7
R4 3
R45
C4 9
1
TP21
1
TP20
2
1
C6 2
2
1
R6 4
2
1
R66
2
1
C6 4
2
1
C61
2
1
R6 0
2
1
R65
2
1
C6 3
C69
C68
C67
C72
C71
C70
C5 7
C5 6
C5 5
C5 2
C5 4
C5 3
54
3
2
1
J2
54
3
2
1
J1
2
1
R4 2
2
1
R41
2
1
R47
4
7
8
6
3
5
1
2
U1 4
2
1
R5 2
2
1
R5 4
2
1
R4 0
2
1
C51
2
1
R5 0
2
1
C4 6
2
1
R3 9
2
1
R44
2
1
R3 8
2
1
R3 7
2
1
C4 8
4
7
8
6
3
5
1
2
U1 3
2
1
R46
2
1
R5 1
2
1
R5 3
2
1
R3 6
2
1
R4 8
2
1
C5 0
2
1
C5 9
2
1
R6 3
2
1
R6 2
2
1
C5 8
2
1
R61
2
1
R5 9
2
1
R5 8
2
1
R6 8
4
7
8
6
3
5
1
2
U1 6
2
1
R7 3
2
1
R7 5
2
1
R71
2
1
C6 6
4
7
8
6
3
5
1
2
U1 5
2
1
R6 7
2
1
R7 2
2
1
R7 4
2
1
R5 7
2
1
R6 9
2
1
C6 5
2
1
C7 4
2
1
C7 3
IN5/IN2
CH7/ CH3
CH5/ CH2
CH2/ CH1
CH0/ CH0
IN2/IN1
IN3
CH0/ CH0 CH2/ CH1
CH3
IN7/IN3
IN6
IN4
IN3
IN2/IN1
IN1
IN0/IN0
CH6
CH4
CH3
CH1
CH1
IN1
IN0/IN0
BLU
10K
0. 1UF
TBD0805TBD0805
TBD0805TBD0805
TBD0805TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
RED
ADA4841- 1YRZ
TBD0805
0
TBD0805
0. 1UF
49. 9
TBD0805
0. 1UF
0
VDRV+
VDRV-
VDRV-
EXT_COM
0
TBD0805
TBD0805
TBD0805 TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
22
RED
RED
RED
ADA4841- 1YRZ
ADA4841- 1YRZ
RED
RED
RED
22
2700PF
RED
RED
RED
22
2700PF
10K
2700PF
BLU
RED
RED
22
2700PF
49. 9 49. 9
49. 9
0
0
0
0
0
00
0
0
VBI AS
VDRV-
VDRV+
COM
VDRV-
VDRV-
VDRV+
ADA4841- 1YRZ
VDRV+
VDRV+
590 590
590
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
VBI AS
0. 1UF
VBI AS
0. 1UF
590
VBI AS
0
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROT ECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
PD_N
N2
N1
V-
V+
GND
PD_N
N2
N1
V-
V+
GND
GND
GND
GND
GND
GND
PD_N
N2
N1
V-
V+
GND
GND
GND
GND GND
GNDGND
GND
PD_N
N2
N1
V-
V+
GNDGND GND
GND GND GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GND
GND
GND
Figure 5. Schematic, AnalogCH0-CH3
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 11 of 24
ADC BUFFERS CONTI NUED
COM
5
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
1
TP78
1
TP77
1
TP79
1
TP70
1
TP69
1
TP72
1
TP61
1
TP60
1
TP62
1
TP67
1
TP66
1
TP68
1
TP64
1
TP63
1
TP65
C91
R9 9
1
TP2 2
2
1
C9 2
2
1
R10 5
2
1
R110
2
1
C9 4
C10 0
C9 9
C9 8
2
1
C9 3
2
1
R10 9
2
1
R111
2
1
C9 5
C10 3
C10 2
C10 1
2
1
C7 7
2
1
R8 5
2
1
R87
2
1
C7 9
C8 7
C8 6
C8 5
2
1
C7 6
2
1
R81
2
1
R86
2
1
C7 8
C8 4
C8 3
C8 2
2
1
R8 3
2
1
R8 4
2
1
R89
4
7
8
6
3
5
1
2
U1 8
2
1
R8 2
2
1
R9 2
2
1
C81
2
1
R9 4
2
1
R9 8
2
1
C8 9
2
1
R10 8
2
1
R10 7
2
1
R10 6
2
1
R7 9
2
1
R8 0
2
1
R7 8
2
1
R8 8
4
7
8
6
3
5
1
2
U1 7
2
1
R9 0
2
1
C8 0
2
1
R9 3
2
1
R9 7
2
1
C8 8
2
1
R10 4
2
1
R10 3
2
1
R10 2
2
1
R11 3
4
7
8
6
3
5
1
2
U2 0
2
1
R11 8
2
1
R11 6
2
1
C9 7
2
1
R12 0
2
1
C10 5
2
1
R11 2
4
7
8
6
3
5
1
2
U1 9
2
1
R11 7
2
1
R11 4
2
1
C9 6
2
1
R11 9
2
1
C10 4
3
2
1
P8
0
TBD0805
0. 1UF
TBD0805
CH6
IN6
IN7/IN3
CH5/ CH2 IN5/IN2 CH7/ CH3
IN4
CH4
TBD0805
TBD0805
TBD0805 TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
RED
ADA4841- 1YRZ
0. 1UF
0
ADA4841- 1YRZ
0. 1UF
22
RED
VBI AS
0. 1UF
ADA4841- 1YRZ
RED
RED
RED
VCM
22
VDRV-
0. 1UF
VDRV+
0. 1UF
49. 9
VBI AS
0. 1UF
0. 1UF
0. 1UF
VBI AS
0. 1UF
0. 1UF
VBI AS
0. 1UF
49. 9 49. 9
VDRV- VDRV-
VDRV-
VDRV+VDRV+
VDRV+
0
0
0
0
0
0
0
0
0
0
590
590 590
590
2700PF
49. 9
2700PF
22
RED
22
RED
RED
RED
2700PF
22
RED
RED
RED
2700PF
ADA4841- 1YRZ
2700PF
BLU
RED
RED
RED
EXT_COM
COM
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805TBD0805
TBD0805
TBD0805
TBD0805
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROT ECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
GND
GND
GND
GND GND
GND
GND GND
GND
GND GND
GND
GND GND
GNDGND
PD_N
N2
N1
V-
V+
GND
GND
PD_N
N2
N1
V-
V+
GND
GND
PD_N
N2
N1
V-
V+
GND
PD_N
N2
N1
V-
V+
GND
Figure 6. Schematic, AnalogCH4-CH7
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 12 of 24
BANK_2
ADCOK
MCL K
DUT_I / O
96_PI N_I / O
BANK_3
BANK_4
BANK_1
SUPPLI ES
POWER_FPGA
6
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
fpga
2
1
P10
2
1
P11
R125
1
TP7 3
9
8
7
6
5
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
P3
1
TP2 7
1
TP2 6
1
TP2 5
1
TP2 4
C128
C130
C131
C127
C129
C109 C110
R126
C125
C126
C122
C124
C118
C120
C115
C116
C113
C111
C108
R12 3
R132
R130 R128
C10 7
R12 4
C11 2 C11 4 C11 7 C11 9
C12 1
C12 3
2
1
R13 6
2
1
R15 0
2
1
R13 7
2
1
R15 1
2
1
R14 4
2
1
R14 3
2
1
R14 2
2
1
R1 4 1
2
1
R14 0
2
1
R13 9
2
1
R13 8
2
1
R13 4
2
1
R12 2
2
1
R12 1
2
1
R13 5
2
1
R14 5
AC
CR1
9
8
7
6
5
4
3
2
10
1
P2
8
7
3
1
4
62
5
U5
4
3
2
1
Y3
T15
T2
P10
P7
M1 0
M7
R16
K14
G1 4
B16
E10
E7
C10
C7
A15
A2
R1
K3
G3
B1
J7
H10
H7
G9
C8
B15
B2
A16
A1
J8
H9
K9
J9
T16
T1
R15
R2
P9
H8
P8
M9
M8
J14
J3
H14
H3
E9
E8
C9
G8
U6
L6
G1
G2
H5
F2
J5
G5
D3
E4
E3
E5
D5
C2
M4
L4
C1
P3
P2
P1
L3
N2
N1
M3
M2
J4
L2
F4
L1
M1
K5
K4
K1
K2
E2
E1
F3
D4
C3
N5 L5
H4
F1
J1
J2
H1
H2
U6
E12
F6
E6
B3
A3
A4
B4
A5
B5
C4
C5
C6
D6
G7
G6
A6
B6
D8
F8
F7
B7
A7
A8
B9
A9
D10
D11
F9
F10
A10
B10
G1 1
G1 0
C11
A11
A12
B12
B11
A13
B13
C12
C13
A14
B14
E11
U6
F11
M1 3
K12
J13
G1 3
G1 2
H11
J11
F16
F15
G1 5
G1 6
J12
H1 2
K15
K16
L16
L15
L14
M1 4
M1 6
M1 5
N1 6
N1 5
P16
P15
P14
N1 4
N1 3
M1 2
N1 2
D1 4
E14
D1 3
C1 4
E16
D1 6
D1 5
H1 3
D1 2
F12
L13
J16
J15
H1 5
H1 6
U6
M5
L11
M1 1
R14
T14
R13
T13
L12
R12
T12
P13
P12
N11
K10
K11
T10
R10
L10
L9
P11
R11
T11
N10
N9
R9
T9
R8
T8
L8
L7
R7
T7
N8
T6
R5
T5
R4
T4
P4
P5
T3
R3
M6
U6
VFPGA
VCCI O1
VI O_ F PGA
VI O
VI O_ F PGA
EP2C5F256C7N
VFPGA
VI O_FPGA
EP2C5F256C7N
EN_5V_N
EN_3. 3V_N
BCS_N
AD<2>
SCK
EN_7V_N
18
5
60. 4
ADCOK
DSPCLK
RESET
BBUSY
10K
10K
BD<7>
VCCI O1
.1UF
ASDO
PS_STATUS_N
PS_CONFI G_N
ASDO
EPCS4SI 8N
ASDO
1000PF
VI O_ F PGA
VI O_ F PGA
VI O_ F PGA
VI O_ F PGA
VI O_ F PGA
VI O_FPGA
VI O_FPGA
VI O_ F PGA
VI O_ F PGA
PS_CONFI G_N
PS_STATUS_N
100MHZ
DATA
10K
DATA
N_CSO
DI N
1000PF
VPLLA2
LA_D<0. . 31>
BD<0. . 15>
MCL K
BLU
15K
10K
CNV
BCS_N
CONTROL
BBUSY
BBUSY
10K
VI O
PS_CDONE_N
BD<6>
BD<5>
BD<3>
BD<14>
AD<3>
AD<4>
BWR_N
BD<11>
BD<9>
VFPGA
MSEL1
MSEL0
DSPCLK
ADCOK
BRD_ N
RESET
AD<1>
AD<0>
BD<15>
BD<13>
BD<12>
BD<10>
BD<8>
BD<4>
BD<2>
BD<1>
BD<0>
PS_CDONE_ N
EP2C5F256C7N
EN_7V_N
LA_D<0. . 31>
VPLLA1
7
SDO
10K
VPLLA1
10K
PS_DCLK
0
PS_DCLK
N_CSO
N_CSO
MCL K
PS_DCLK
CONTROL
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF .1UF .1UF .1UF .1UF
0
0
10K
10K
BWR_N
10K
BRD_ N
10K
10K
10K
10K
BLU
EP2C5F2 56C7 N
EP2C5F2 56C7 N
LA_CLK2LA_CLK1
LA_CLK2
16
12
25
BWR_N
CONTROL
DSPCLK
20
21
MSEL0
30
29
28
27
26
25
24
23
22
19
18
17
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
MSE L 1
VI O
GND
31
30
29
28
24
23
22
21
20
19
17
15
14
13
11
10
9
8
7
6
4
3
2
1
0
EN_5V_N
SDO
BCS_N
BRD_ N
RESET
DI N
CNV
3M2510- 5002UB
GND
GND
AD<0..4>
26
27
31
LA_CLK1
.1UF
VFPGA
SCK
BLU
BLU
VFPGA
TBD0603
EN_3. 3V_N
10K
15K
VPLLA2
VI O_ F PGA
DATA
YEL
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROT ECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
VCCI O4VCCI O3VCCI O2VCCI O1VCCI NT
GND
VCCD_ PL L1
TDO
TMS
TDI
TCK
NCONFI G
NCE
DCLK
DATA0
CLK3
CLK2
CLK1
CLK0
GND_PL L1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
GND
GND
GND
GND
IN
GND
GND
GND
GND
VCCA_PLL2
GNDA_PLL2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
ASDI
DCLK
VCC
DATA
nCS
GND
GND
GND
GND
V+
GNDOUT
EN
GND
GND
GND
GND
VCCD_ PL L2
MSEL1
MSEL 0
CLK7
CLK6
CLK5
CLK4
GND_PL L2
NSTATUS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CONF_ DONE
VCCA_PLL1
GNDA_PLL1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Figure 7. Schematic, FPGA
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 13 of 24
BD<15>
AD<0>
AD<3>
AD<4>
VDI G
-5VA
+5VA
- 12VA
+12VA
DSPCLK
CONTROL
RESET
BWR_N
BRD_ N
BBUSY
BCS_N
AD<1>
BD<13>
BD<11>
BD<12>
BD<10>
BD<9>
BD<8>
BD<0. . 15>
BD<3>
BD<2>
4
3
1
0
15
14
13
11
12
9
8
7
6
5
4
3
2
1
0
GND
GND
BD<14>
BD<0>
BD<1>
BD<4>
BD<6>
10
ERNI 533402
VDI G
BWR_N
BCS_N
AD<4>
BBUSY
BD<14>
BD<15>
+12VA
-5VA
+5VA
CONTROL
BD<0>
BD<1>
BD<2>
BD<3>
BD<4>
VDI G
BD<7>
BD<8>
BD<13>
-5VA
+5VA
VDI G
AD<3>
RESET
BD<12>
DSPCLK
- 12VA
-5VA
+5VA
AD<0..4>
BD<5>
GND
BD<5>
BD<6>
BD<11>
BRD_N
BD<10>
AD<2>
AD<0>
BD<9>AD<1>
ERNI 533402ERNI 533402
BD<7>
GND
AD<2>
2
96_pin
A
Topl evel
AD7689/ 82/ 99/ 92
<PRODUCT_1>
<PTDE_ENGI NEER>
77
P4
C1
C1 0
C11
C1 2
C1 3
C1 4
C1 5
C1 6
C1 7
C1 8
C1 9
C2
C2 0
C21
C2 2
C2 3
C2 4
C2 5
C2 6
C2 7
C2 8
C2 9
C3
C3 0
C31
C3 2
C4
C5
C6
C7
C8
C9
P4
B1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B2
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B3
B30
B31
B32
B4
B5
B6
B7
B8
B9
P4
A1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A3
A30
A31
A32
A4
A5
A6
A7
A8
A9
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ONS
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROT ECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
Figure 8. Schematic, 96-Pin Interface
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 14 of 24
Figure 9. Top Side Silk-Screen
(Viewed from top side)
Figure 10. Inner Layer 1
(Viewed from top side)
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 15 of 24
Figure 11. Ground Plane
(Viewed from top side)
Figure 12. Inner Layer 2
(Viewed from top side)
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 16 of 24
Figure 13.Inner Layer 3
(Viewed from top side)
Figure 14. Bottom Layer
(Viewed from top side)
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 17 of 24
Figure 15. Bottom Layer
(Viewed from Bottom Side)
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 18 of 24
Figure 16. Setup Screen
2) The part under evaluation is chosen from this
menu. The device must be selected second.
3) Interface modes are chosen here.
4) This window is used to select the
test type, number of Ksamples, and
conversion mode (continuous or
burst). For the test type choose
from either:
Histogram test
AC Test
Decimated AC Test
5) This window allow the samples to be taken once (F3) or continuous (F4).
Also selects: Help screen, Save data (F5), Print (F8) and Quit (F10). The Help
menu shows a description of the functionality of the chosen command.
This is the
p
erformance window.
These controls are for locking and resetting the display
axis to the data minimum and maximum values.
1) The Run button starts the software. This button
must be pressed first.
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 19 of 24
The ADC needs to be configured for input configuration,
reference, channel to be converted, temperature sensor, and on-
chip low pass (LP) filter (optional) for full bandwidth (BW) or
¼ BW. These next figures show the pull down configurations
available. Note the default value when the program is started is
indicated by the √; or unipolar to GND, ext reference, CH0,
temperature sensor enabled and LP filter set to full BW.
Note that after updating the very first conversion (when using
burst mode) will be of the last configuration since the ADC
must complete one conversion for the configuration register to
update.
Figure 17 details the inputs (IN0-IN7) configuration. Refer to
the datasheet for more information about the input configure-
ations. Note that in the bipolar ranges, the input must not go
below GND as this is intended for single supply systems where
the amplfiers output swings midscale of the amplifier’s supplies
(V+ and GND). In bipolar range, the COM or paired channel
must be set to this midscale voltage as well.
Figure 17. Input Configuration
Figure 18 details the reference selection. The choices are straight
forward.
Figure 18. Reference Selection
Figure 19 details the choices for the channel to be converted.
Figure 19.Channel Select
The Temp sensor can be used to monitor the temperature of the
ADC. The displayed results should be in Volts format as
opposed to Hex.
Figure 20. Temperature Sensor
Figure 21 details the bandwidth selection of the 1-pole low pass
filter, which can reduce the noise from the amplifier circuit, if
desired.
Figure 21. Low Pass Filter
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 20 of 24
Figure 22. Histogram Screen
The results are displayed in this chart. Also, the cursor
(yellow) can be dragged it to a desired location where the
X-axis values and the Y-axis value will be displayed.
Different measurements are displayed here. The DC
value, Transition Noise and other values
These control the choice of chart type and X-units.
Chart type selection of Histogram or Time and X-units
of hexadecimal or Volts.
This window shows the ADC range and LSB
value in Volts.
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 21 of 24
Figure 23. FFT Screen
AC test results are displayed here. Also the
choice of viewing the amplitude of a certain
FFT component can be selected from the
FFT component menu.
These control the chart type choice of Frequency
domain or Time domain and X axis units.
Choice of either a Kaiser window or a Blackmann-
Harris window from the is menu.
The results are displayed in this chart. Also, the cursor
(yellow) can be dragged it to a desired location where the
X-axis values and the Y-axis value will be displayed.
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 22 of 24
Figure 24. Time-Domain Screen
To view the Time domain output, select Time in this menu.
The AC test can also be displayed in the Time Domain as shown below.
Preliminary Technical Data EVAL-AD76MUXCBZ
Rev. PrB | Page 23 of 24
Figure 25. Decimated (Averaging) Screen
AC test results with decimated averaging are shown
here. The SNR indicator also represents the
dynamic range when no signal is present.
The decimation ratio (Dratio) and number of
Ksamples are entered here.
The Nyquist frequency is displayed here as:
RATIO
SAMPLE
NYQUIST D*
F
F2
=
The results are displayed in this chart. Also, the cursor
(yellow) can be dragged it to a desired location where the
X-axis values and the Y-axis value will be displayed.
EVAL-AD76MUXCBZ Preliminary Technical Data
Rev. PrB | Page 24 of 24
ORDERING GUIDE
Evaluation Board Model Product
EVAL-AD7682CBZ AD7682BRMZ
EVAL-AD7689CBZ AD7689BRMZ
EVAL-AD7699CBZ AD7699BRMZ
EVAL-AD7949CBZ AD7949BRMZ
EVAL-CONTROL BRD3Z Controller Board
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07084-0-11/07(PrB)
