Preliminary Technical Data Evaluation Board For AD7682/89/99/7949 PulSAR(R) ADCs EVAL-AD76MUXCBZ The evaluation board must be used in conjunction with the Analog Devices EVAL-CONTROL BRD3Z 16-bit parallel DSP interface board. Since the ADC's being evaluated are serial interface only, the EVAL-AD76MUXCBZ contains the necessary logic to perform serial to parallel conversion for this interface. FEATURES Versatile analog signal conditioning circuitry On-board reference, clock oscillator and buffers EVAL-CONTROL BRD3Z compatibility PC software for control and data analysis of time and frequency domain GENERAL DESCRIPTION The EVAL-AD76MUXCBZ is an evaluation board for the PulSAR AD7682, AD7689, AD7699, and AD7949 14-bit and 16-bit PulSAR analog to digital converter (ADC) family. These low power, successive approximation register (SAR) architectture ADCs (see Ordering Guide for product list) offer very high performance with up to 500kSPS throughput rate and 4 - 8 channels. The evaluation board is designed to demonstrate the ADC's performance and to provide an easy to understand interface for a variety of system applications. A full description of the AD7682, AD7689, AD7699, and AD7949 is available in at www.analog.com and should be consulted when utilizing this evaluation board. Signal conditioning On-board components include a high precision band gap reference, (ADR435), reference buffers, 8-signal conditioning circuits with an op amp and an FGPA for digital logic. Also included are separate low drop out regulators for supplying special voltages of 1.2V and 7V which are not available from the EVAL-CONTRL BRD3Z. The board interfaces to the EVAL-CONTROL-BRD3Z with a 96-pin DIN connector. J1, J2 SMB connectors are provided for the low noise analog signal source for CH0 and CH1 with the remaining channels (and CH0/1) available on an IDC connector, P1. J3 can be used for providing an external common (COM) or configured for any input channel. Reference Source, COM Select FPGA 96-Pin EVAL-CONTROL BRD3Z Interface Analog Inputs External COM (or Input) ADC Figure 1.Evaluation Board 40-Pin IDC Header Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. EVAL-AD76MUXCBZ Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Hardware Setup .............................................................................3 Revision History ............................................................................... 2 Software Installation .....................................................................4 Overview........................................................................................ 3 Running the Evaluation Software ..............................................4 Conversion Control...................................................................... 3 Setup Screen...................................................................................4 Analog Inputs................................................................................ 3 Configuring the ADC ...................................................................4 Serial Interface .............................................................................. 3 DC Testing - Histogram ...............................................................4 Reference ....................................................................................... 3 AC Testing ......................................................................................4 Power Supplies and Grounding .................................................. 3 Decimated AC Testing (Averaging) ............................................4 Schematics/PCB Layout............................................................... 3 Ordering Guide .......................................................................... 24 LIST OF FIGURES Figure 1.Evaluation Board ............................................................... 1 Figure 14. Bottom Layer ................................................................ 16 Figure 2. Schematic, ADC + Block Diagram................................. 7 Figure 15. Bottom Layer ................................................................ 17 Figure 3. Schematic, Supplies .......................................................... 8 Figure 16. Setup Screen.................................................................. 18 Figure 4. Schematic, Reference, Buffer, VCM, VBIAS ......................... 9 Figure 17. Input Configuration..................................................... 19 Figure 5. Schematic, AnalogCH0-CH3 ........................................ 10 Figure 18. Reference Selection ...................................................... 19 Figure 6. Schematic, AnalogCH4-CH7 ........................................ 11 Figure 19.Channel Select ............................................................... 19 Figure 7. Schematic, FPGA ............................................................ 12 Figure 20. Temperature Sensor ..................................................... 19 Figure 8. Schematic, 96-Pin Interface........................................... 13 Figure 21. Low Pass Filter .............................................................. 19 Figure 9. Top Side Silk-Screen....................................................... 14 Figure 22. Histogram Screen......................................................... 20 Figure 10. Inner Layer 1 ................................................................. 14 Figure 23. FFT Screen .................................................................... 21 Figure 11. Ground Plane ................................................................ 15 Figure 24. Time-Domain Screen .................................................. 22 Figure 12. Inner Layer 2 ................................................................. 15 Figure 25. Decimated (Averaging) Screen................................... 23 Figure 13.Inner Layer 3.................................................................. 16 LIST OF TABLES Table 1. Jumper Description............................................................ 5 Table 3. Bill of Materials for the Connectors .................................6 Table 2.Test Points ............................................................................ 6 REVISION HISTORY Rev. PrB | Page 2 of 24 Preliminary Technical Data EVAL-AD76MUXCBZ OVERVIEW Figure 1 shows the EVAL-AD76MUXCBZ evaluation board. When used in conjunction with the EVAL-CONTROL BRD3Z, the FPGA, U6, provides the necessary control signals for conversion and buffers the ADC serial output data into 16-bit wide transfers. The evaluation board is a flexible design that enables the user to choose among many different board configurations, analog signal conditioning, reference, and different interfaces for conversion results. CONVERSION CONTROL Conversion start (CNV) controls the sample rate of the ADC and is the only input needed for conversion; all SAR timing is generated internally. CNV is generated by the gate array and the frequency is selected with the software. While the ADC is converting, activity is indicated by the green LED, CR1. Operating the software in Burst mode as opposed to Continuous mode, will only light the LED when conversion is taking place. ANALOG INPUTS SMB connectors, J1 and J2, are provided for the ADC input channels IN0 and IN1 (IN0 only on AD7682). These inputs are also on the IDC connector P1-2 and P1-4. The remaining inputs are also on P1-6 through P1-16 (even pins only). J3 can be configured for providing a common point (COM) for all input signals or for any analog input IN0-IN7. For using J3 as an external common point, remove the solder pad (bottom of PCB) from "COMS to COM" and solder "EXT_COM to COM" as shown below. To configure J3 to drive any of the analog input channels, remove R35 from the left pads (bottom of PCB) and solder it to the rightmost pads. Note that when using the unipolar configuration, COMS (P8) is set to (P8, 2-3) and for bipolar input configuration set to (P8, 12) with pin 1 being the leftmost pin. SERIAL INTERFACE The 3-wire serial interface DIN, SCK, and SDO along with CNV are present on test points. FPGA buffered versions are on 40-pin IDC connector, P3 pins 2, 4, 6 and 8. REFERENCE All of the ADCs for this evaluation board can use a precision trimmed on-chip band gap reference, an on-board precision ADR435 band gap reference, or an external reference connected to the EXTREF test point (TP17). The on-chip reference is enabled or disabled with the software. The on-chip reference can be set for 2.5V or 4.096V outputs and also includes an internal buffer, useful for external reference applications. When using the on-chip reference, remove the jumper on TP7 since this will overdrive the on-chip reference with the external one. The default configuration is for on-board ADR435 reference with a buffered output (P5 2-3), (P6 1-2) and (P7 1-2). For using an external reference connect to the EXTREF test point (TP17), select a buffer or not with P6 and select if driving the ADC REF directly or using the ADC's internal reference buffer. When using the internal reference buffer with gain=1, the maximum output is limited to 4.096V (headroom from 5V supply). The default configuration sets the amplifiers output to be at VREF/2 (mid-scale) from the voltage divider at U1B (VBIAS). POWER SUPPLIES AND GROUNDING To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths by connecting the planes together directly under the converter. Power is supplied to the board through P3 when using with the EVAL-CONTROL-BRDXZ SCHEMATICS/PCB LAYOUT The EVAL-AD76MUXCBZ is a 6-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the ADC. Figure 2 through Figure 8 shows the schematics of the evaluation board. The silkscreens for the PCB are given in Figure 9 and Figure 11. HARDWARE SETUP System Requirements The analog input amplifier circuitry U13 - U20 (see schematic Figure 2) allows flexible configuration changes such as positive or negative gain, input range scaling, filtering, addition of a DC component, use of different op-amp and supplies. The analog input amplifiers are set as unity gain buffers at the factory. The supplies are selectable with solder pads VDRV- and VDRV+ and are set for the +7V, -5V range. * Evaluation Board * Evaluation Control Board 3, EVAL-CONTROL BRD3Z * AC Power Supply (AC 14V/1A source - can be purchased from ADI) * IEEE 1284 Compliant Parallel Port Cable (if not supplied) * DC source (low noise for checking different input ranges) * AC source (low distortion) * Band pass filter suitable for 16 or 18 bit testing (value based on signal frequency) Rev. PrB | Page 3 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data * PC operating Windows 2000 or XP. SETUP SCREEN Connect the control board supplied mini plug to the 14V AC source. Connect the evaluation board to the controller board and connect the parallel port cable to the evaluation board and to the PC .Software Installation Figure 16 is the setup screen where ADC device selection, test type, input voltage range, sample rate and number of samples are selected. Double-Click on setup.exe from the CD-ROM and follow the installation instructions. If upgrading the software, the previous version will first be removed. Thus setup.exe will need to be run again to install the new version. When asked to install the "GIVEIO" driver, click on yes to install. You must reboot the computer for the drivers to load properly. These ADCs need to be configured through a dedicated SPI compatible serial port. The included SW configures the part to a default configuration. Each of the different configurable parameters are shown in Figure 17.to Figure 21. SOFTWARE INSTALLATION Figure 22 is the histogram screen, which tests the code distribution for DC input and computes the mean and standard deviation or transition noise. To perform a histogram test, select "Histogram" from the test selection window and click on the "Start" radio button. Note: a histogram test can be performed without an external source since the evaluation board has a buffered VREF/2 source at the ADC input. To test other DC values, apply a source to the J1/J2/P1-x inputs. It is advised to filter the signal to make the DC source noise compatible with that of the ADC. Double-Click on setup.exe from the CD-ROM and follow the installation instructions. When asked to install the "GIVEIO" driver, click on yes to install. You must reboot the computer for the drivers to load properly. If this message is displayed: CONFIGURING THE ADC DC TESTING - HISTOGRAM AC TESTING Click OK and run GIVEIO from <local drive>:\Program Files\Analog Devices\Hi-Res Mux ADC's x.x and reboot the computer. * Fast Fourier transforms (FFT) for signal to noise ratio (SNR), SNR and distortion (SINAD), total harmonic distortion (THD) and spurious free dynamic range (SFDR) Figure 23 is the FFT screen, which performs an FFT on the captured data and computes the SNR, SINAD, THD and SFDR. Figure 24 is the time domain representation of the output. To perform an AC test, apply a sinusoidal signal to the evaluation board at the SMB inputs J1 for CH0 and J2 for CH1. Low distortion, better than 100dB, is required to allow true evaluation of the part. One possibility is to filter the input signal from the AC source. There is no suggested bandpass filter but consideration should be taken in the choice. Furthermore, if using a low frequency bandpass filter when the full-scale input range is more than a few Vpp, it is recommended to use the on board amplifiers to amplify the signal, thus preventing the filter from distorting the input signal. * Decimation (digital filtering) DECIMATED AC TESTING (AVERAGING) RUNNING THE EVALUATION SOFTWARE The evaluation board includes software for analyzing the AD7682, AD7689, AD7699 and AD7949. The EVALCONTROL-BRDX is required when using the software. The software is used to perform the following tests: * Histogram for determining code transition noise (DC) The default configuration loads the software into <local drive>:\Program Files\Analog Devices\Hi-Res ADC's Mux x.x\ADC Eval SW MUX.exe. This can also be accessed from the Start button and selecting: All Programs -> Analog Devices HiRes MUX ADC's Evaluation Software x.x -> ADC Eval SW MUX. The AC performances can be evaluated after digital filtering with enhanced resolution of up to 32 bits. Figure 25 is the FFT screen when decimation is used. Additional bits of resolution are attained when over sampling by: The software has four screens as shown in Figure 22 through Figure 25. where , N = number of bits and 4N.= the DRATIO. Set the DRATIO to the amount of over sampling desired. When using decimation, the test duration increases with the larger number of samples taken. The decimated test requires the EVALCONTROL-BRD3Z f OVERSAMPLE Rev. PrB | Page 4 of 24 = 4 N * f SAMPLE Preliminary Technical Data EVAL-AD76MUXCBZ Table 1. Jumper Description Jumper Name P5 - Default Position REFS P6 - BUF P7 REF/REFIN REF P8 COMS VCM JP9 JP10 JP11 SB0-7 5V 4.096V 2.5V BUF Select 5V Open Open BUF VDRVVDRV+ VCCREF VDDR VDD VIO -5V 7V 12V 5V 5V 3.3V - Function Reference source selection. REFS to middle pin: uses ADR435 (A1) 5V, 4.096V or 2.5V output. VDD to middle pin: VDD supply is used as a reference. Open: optional source can be connected to TP17/VREF. Reference buffer selection. BUF to middle pin: buffer selection from P5 with the AD8032-A (U2). NOBUFF to middle pin: use P5 direct (no buffer). ADC REF/REFIN input selection. REF to middle pin: external source drives ADC REF pin. REFIN to middle pin: external source drives REFIN, reference buffer input pin Open: When using the on-chip reference. Common channel select. VCM to middle pin: for bipolar mode, selects VREF/2. GND to middle pin: for unipolar operation, selects GND. External reference selection of 5V. External reference selection of 4.096V. External reference selection of 2.5V. Use on-board analog amplifiers (U13 - U20) BUF: use amplifier NO BUF: bypass amplifier Amplifiers (U13-U20) (-) supply. Amplifiers (U13-U20) (+) supply. ADR435(A1) (+) supply. ADC (U7) VDD supply. Must always be the same as VDD. ADC (U7) VDD supply. ADC (U7) VIO interface supply. Rev. PrB | Page 5 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data Table 2.Test Points Test Point TP13 TP14 TP15 TP17 TP18 TP19 Available Signal VDD VDDR VIO VREF REF REFIN Type Description P P P AI AI/O AI/O TP20 TP21 TP22 TP24 TP25 TP26 TP27 IN0 IN1 COM SDO SCK DIN CNV AI AI AI DO DI DI DI ADC (U7) VDD supply. ADC (U7) VDD supply. Must always be = AVDD above. ADC (U7) VIO interface supply. External reference input. ADC on-chip reference output or external reference input. ADC on-chip band-gap output or external reference input when using on-chip reference buffer. Analog input for ADC IN0 on both 4 and 8-cahhel ADCs. Analog input for channel 1 on 8-channel ADCs only. Sets the level on ADC COM; GND or VREF/2. Serial data output from ADC. Serial clock data input to ADC. Serial data input for part configuration. Conversion input to ADC Table 3. Bill of Materials for the Connectors Ref Des J1, J2, J3 P1 P2 P4 Connector Type RT Angle SMB Male 0.100 X 0.100 straight IDC header 2X10 0.100 X 0.100 straight IDC header 2X20 32X3 RT PC MOUNT CONNECTOR Manf. Pasternack 3M 3M ERNI Part No. PE4177 2540-6002UB 2540-6002UB 533402 Rev. PrB | Page 6 of 24 Figure 2. Schematic, ADC + Block Diagram A B C 8 7 7 VDRV - VDRV + VDD VCCRE F ANALO G REF 6 COM I N7 / I N 3 I N6 I N5 / I N 2 I N4 I N3 I N2 / I N 1 I N1 I N0 / I N 0 REFI N 6 1 TP1 BL K GND - 5VA VDI G TP2 BL K EN_ 7V_ N VI O 1 EN_ 5V_ N 1 5 GND 2 3 4 5 1 TP3 BL K BOTTOM VDDR VDD EN_ 3. 3V_ N +5VA C1 1 TOP VCCRE F +1 2V A VPL LA 2 POWE R VPL LA 1 VDRV - 2 VDRV + VFPGA VI O_FPG A 5 C2 7 TBD0805 PAD 20 6 1 TP4 BL K 0. 1UF BOTTOM 0. 1UF BOTTOM BOTTOM TP6 BL K 1 TP7 BL K 4 TP8 BL K 1 AD<0. . 4 > TP7 4 BL K 3 DSPCL K THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . A N A L OG DE V CE S CONTRO L RESE T RESE T DSPCL K BWR_ N CONTRO L BRD_ N BCS_ N BBUS Y TP7 1 BL K 9 6_ pi n AD<0. . 4 > BD<0. . 15 > GND VDI G - 5VA +5VA BWR_ N GND GND - 12 V A +12 V A BRD_ N 1 3 BBUS Y BCS_ N BD<0 . . 15 > SCK 1 VI O FPGA VFPGA VI O_FPGA VPLLA1 VPLLA2 SDO CNV 1 BOTTOM DI N TP5 BL K 0. 1UF 11 1 0. 1UF GND 4 EN_3. 3V_N EN_5V_N EN_7V_N 15 14 13 12 U7 10UF C3 1 2 19 18 17 16 8 9 Rev. PrB | Page 7 of 24 10 2 C4 1 2 C5 1 2 C6 1 D 8 2 2 <PTDE_ENGI NEER> PTDE ENGI NEER ad7689_c s p_t opl evl e DESI GN VI EW Topl evel AD7689/ 82/ 99/ 92 <PRODUCT_1 > REV REVI SI ON S DD SI ZE SCALE 1 1 SHEET DATE DRAWI NG NO. SCHEMATI C DESCRI PTI O N 1 OF 7 A REV APPROVED A B C D Preliminary Technical Data EVAL-AD76MUXCBZ VDI G 8 EN_7V_N EN_5V_N EN_3. 3V_N OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN VI O_FPGA VPLLA2 VPLLA1 VFPGA VCCREF VDDR VDD VI O VDRV- VDRV+ 7 EXT EXT 1 TP1 2 YEL - 5VA - 5VA TP9 1 WHT +3. 3V EXT +5V EXT +5V EXT +5V +7V +12VA GND GND TP44 TP45 TP46 1 RED 1 RED 1 RED A B C - 5VA +5VA +12VA - 5VA +5V +7V TP31 RED TP37 GND GND TP1 6 BL K 1 GND C1 2 10UF GND C11 10UF 1 1 1 +5VA +5VA TP1 0 1 RED VI O VDDR VDD GND C1 3 10UF VCCREF VDRV- VDRV+ 6 +12VA +12VA TP1 1 1 RED GND C1 6 10UF TP1 5 BL U VI O GND C1 5 10UF VDDR TP1 4 BL U GND C1 4 10UF TP1 3 BL U VDD 1 GND 1K R5 GND R2 2K GND ADP1715ARMZ-7R R1 1K 1 EN 2 I N U9 OUT 3 4 ADJ GND 5 6 7 8 LDO ADJ USTE D TO 1 . 2 V R6 2K ADP1715ARMZ-7R EN 2 I N U11 OUT 3 4 ADJ GND 5 6 7 8 1 LDO ADJ USTED TO 1. 2V R4 2K ADP1715ARMZ-7R EN 2 I N U1 0 OUT 3 4 ADJ GND 5 6 7 8 1 LDO ADJ USTED TO 1. 2V 1K R3 0 1 R7 2 0 1 R9 2 0 1 R8 2 5 VDI G U8 GND 8 I N2 OUT2 2 6 SD* FB 3 PAD GND PAD 5 ADP3334ACP Z 7 I N1 OUT1 1 R5 5 140 K 4 VFPGA VPLLA2 VPLLA1 VI O_FPGA REGUL ATE S FPGA VI O SUPPLI E S TO 3 . 3 V ( MAX AL LOWED) VDI G VDI G TP7 6 RED VDI G FPGA SUPPLI ES 2 2 4 C24 2 C25 2 1 TP34 1 RED RED 1 3 3 A N A L OG DE V CE S 10K 1 R1 2 2 10K 1 R11 2 10K 1 R1 0 2 THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . VI O_FPGA EN_7V_N +12VA VI O_FPGA EN_5V_N +12VA VI O_FPGA EN_3. 3V_N +5VA 2 U3 GND DESI GN VI EW <PRODUCT_1 > 2 <PTDE_ENGI NEER> PTDE ENGI NEER GND 8 I N2 OUT2 2 6 SD* FB 3 PAD GND PAD 5 ADP3334ACP Z 7 I N1 OUT1 1 U4 GND 8 I N2 OUT2 2 6 SD* FB 3 PAD GND PAD 5 ADP3334ACP Z 7 I N1 OUT1 1 Topl evel AD7689/ 82/ 99/ 92 powe r U1 2 7 I N1 OUT1 1 8 I N2 OUT2 2 6 SD* FB 3 PAD GND PAD 5 ADP3334ACP Z R1 3 140 K DD SI ZE SCALE 1 1 OF 7 A REV APPROVED SHEET 2 +7V +5V +3. 3V DATE DRAWI NG NO. SCHEMATI C 0 1 R21 2 0 1 R2 0 2 0 1 R1 9 2 REVI SI ON S DESCRI PTI O N ANALOG SUPPLI ES REV 1000PF SUPPLY OPTI ONS C7 TP43 1 RED TP40 C22 2 +12VA 2. 2UF RED 1 C18 2 C19 2 C17 2 1 1 5 P9 6 1 C30 2 D 7 2 Rev. PrB | Page 8 of 24 C8 Figure 3. Schematic, Supplies 1000PF C32 C33 8 TP38 TP39 1 RED 1 RED C9 TP41 TP42 1 RED 1 RED TP47 1 RED 1 1 1 2. 2UF 2. 2UF 2. 2UF C21 1 2 1 C20 1 2 0. 1UF 0. 1UF 2. 2UF 2. 2UF 2. 2UF C23 1 2 2 2 2 2 1 R56 TP35 TP36 1 RED 1 RED 0. 1UF 1 2. 2UF C26 C27 C28 2. 2UF 2. 2UF 2. 2UF 78. 7K 210K 2 1 R16 2 C29 1 2 1 C31 1 2 1 R14 2 1000PF 1 R15 2 1000PF 2. 2UF 2. 2UF TP32 TP33 1 RED 1 RED 64. 9K TP28 TP29 TP30 1 RED 1 RED 1 RED 1 1 R17 2 300K 1 C34 1 1 R182 60. 4K 1 2. 2UF 1 78. 7K A B C D EVAL-AD76MUXCBZ Preliminary Technical Data Figure 4. Schematic, Reference, Buffer, VCM, VBIAS Rev. PrB | Page 9 of 24 A B C 8 VCCREF 0 R2 2 OUT REFI N REF C35 OUT 10UF GND 1 TP 8 NC2 7 6 TP1 VOUT 5 TRI M ADR435BR Z 2 VI N 3 NC1 4 GND A1 C37 7 10K 1 R2 3 2 5V 1 JP9 2 VDD 4. 096V 1 R242 1 JP10 2 45. 3K VCCREF 2. 5V 1 R252 1 JP11 2 P5 VREF REFS VDD 5 1 6 2 3 VDD VREF TP1 7 1 YEL 1K R2 6 1 R2 7 2 TBD0 805 GND C3 8 10UF 3 2 C3 9 2 5 U2 1K R2 8 1 P6 BUF NOBUF AD8032AR Z TBD0805 1 8 VCCREF 4 V- V+ GND U2 4 0. 1UF C4 0 1 1K R2 9 REFI N TP1 9 1 BL U REFI N TP1 8 BL U REF REF P7 4 REFI N 1 2 3 1 REF 2 3 AD8032AR Z EXTERNAL REFERENCE OPTI ONS 6 GND C4 1 10UF 5 6 U2 7 AD8032AR Z 3 3 THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S I N PART , OR USE D I N FURNI SHIGN I NFORMATI N O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . A N A L OG DE V CE S 10K 1 R31 2 10K R3 0 REV 2 GND 5 6 U1 AD8032AR Z GND C4 3 10UF 7 0. 1UF C4 4 VBI AS VCM 2 D SCALE DRAWI NG NO. <PTDE_ENGI NEER> anal og SI ZE GND PTDE ENGI NEER SCHEMATI C 1 2 GND VCCREF AD8032AR Z V- 4 1 AD8032AR Z V+ 8 U1 U1 1 1 OF 7 A REV APPROVED SHEET 3 DATE DESI GN VI EW Topl evel AD7689/ 82/ 99/ 92 <PRODUCT_1 > GND C4 2 10UF GND 3 2 C4 5 10UF REVI SI ON S DESCRI PTI O N BI ASI NG USI NG ADC REF 10K D 7 R32 1 R33 2 10K 8 A B C D Preliminary Technical Data EVAL-AD76MUXCBZ GND 10K 2. 2UF 1 0. 1UF C36 2 1 1 8 GND 2 3 4 5 EXT_COM R4 9 TBD0805 0 CH7/ CH3 CH6 CH5/ CH2 CH4 CH3 CH2/ CH1 CH1 CH0/ CH0 COM I N7/ I N3 I N6 I N5/ I N2 I N4 I N3 I N2/ I N1 I N1 I N0/ I N0 R3 5 12 13 14 15 16 11 10 8 9 7 2 3 4 5 6 J3 GND P1 OUT OUT OUT OUT OUT OUT OUT OUT OUT 1 CH1 GND 2 3 4 5 J2 GND 2 3 4 5 J1 1 CH0/ CH0 7 VBI AS VBI AS 2 1 GND C4 7 0. 1U F 59 0 R4 3 0 1 R41 2 TBD0805 1 R4 2 2 1 R4 0 2 TBD0805 GND 59 0 C4 6 0. 1U F 1 R3 9 2 0 1 R3 7 2 TBD0805 1 R3 8 2 1 R3 6 2 TBD0805 TBD0805 2 6 TBD0805 C4 9 49. 9 1 R4 7 2 C4 8 1 49. 9 1 R4 6 2 V+ 4 C5 6 C5 7 0. 1U F 0 ADA4841- 1YR Z 1 U1 4 1 R5 2 2 6 N1 PD_N 8 5 N2 TBD0805 V- 0. 1U F C5 5 0 1 R5 0 2 V+ 7 VDRV- 3 2 C51 1 C5 4 0. 1U F TBD0805 VDRV+ 2 C5 3 TBD0805 0 ADA4841- 1YR Z 1 U1 3 1 R5 1 2 6 N1 0. 1U F C5 2 0 1 R4 8 2 PD_N N2 V8 5 4 VDRV- 3 7 VDRV+ 2 C5 0 2 1 TBD0805 5 1 I N1 1 5 BL U TP2 0 I N0/ I N0 TP2 1 BL U 22 1 R5 3 2 22 1 R5 4 2 2700PF 2 GND C5 9 1 I N1 2700PF 2 GND C5 8 1 I N0/ I N0 ADC BUFFERS 4 4 CH3 CH2/ CH1 VBI AS VBI AS 2 1 2 1 GND A B C D R45 6 RED R156 VDRV- 1 R442 TBD0805 TBD0805 RED TP58 1 RED TP57 GND GND GND GND TP54 TP55 1 RED 1 10K 10K 1 RED R157 Rev. PrB | Page 10 of 24 1 Figure 5. Schematic, AnalogCH0-CH3 RED 1 TP56 TP59 VDRV+ 7 59 0 GND C6 2 0. 1U F 59 0 1 R6 4 2 0 1 R6 2 2 TBD0805 1 R6 3 2 1 R61 2 TBD0805 GND 0. 1U F C61 1 R6 0 2 0 1 R5 8 2 TBD0805 1 R5 9 2 1 R5 7 2 TBD0805 3 3 1 R652 TBD0805 2 1 2 1 3 2 4 I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S 0 C7 0 N2 2 0 C71 C7 2 2 <PTDE_ENGI NEER> PTDE ENGI NEER anal og DESI GN VI EW <PRODUCT_1 > Topl evel AD7689/ 82/ 99/ 92 0. 1U F 0 ADA4841- 1YR Z 1 U1 6 6 1 R7 3 2 N1 PD_N 8 5 0. 1U F TBD0805 V- V+ THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. C6 6 2 1 R71 2 7 VDRV- 3 C6 9 0. 1U F TBD0805 VDRV+ 2 C6 8 TBD0805 1 REV ADA4841- 1YR Z 1 U1 5 1 R7 2 2 6 N1 0. 1U F PD_N N2 V8 5 4 V+ C6 7 0 1 R6 9 2 7 VDRV- A N A L OG DE V CE S TBD0805 C6 4 49. 9 1 R6 8 2 TBD0805 C6 3 49. 9 1 R6 7 2 C6 5 2 1 TBD0805 VDRV+ THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . 1 R66 2 TBD0805 GND GND GND GND GND DD SI ZE SCALE 1 SHEET 4 2700PF 2 GND C7 4 1 I N3 2700PF GND OF 7 A REV APPROVED I N2/ I N1 C7 3 1 DRAWI NG NO. SCHEMATI C 22 1 R7 5 2 22 1 R7 4 2 1 DATE 2 REVI SI ON S DESCRI PTI O N RED TP52 1 RED RED TP51 1 RED 1 TP48 TP49 1 RED 1 GND RED 1 TP50 TP53 8 A B C D EVAL-AD76MUXCBZ Preliminary Technical Data GND 8 CH5/ CH2 VBI AS VBI AS 1 2 1 GND Figure 6. Schematic, AnalogCH4-CH7 2 1 R8 2 2 GND 7 59 0 C7 7 0. 1U F 1 R8 5 2 0 1 R8 3 2 TBD080 5 1 R8 4 2 TBD0805 GND 59 0 C7 6 0. 1U F 1 R81 2 0 2 1 TBD0805 TBD0805 C7 9 49. 9 1 R8 9 2 C7 8 1 2 1 R8 8 2 49. 9 V+ 7 N1 C8 6 0. 1U F C8 7 6 0 ADA4841- 1YR Z 1 U1 8 6 1 R9 4 2 N1 PD_N 8 5 N2 TBD0805 V- V+ 4 VDRV- 3 0. 1U F C8 5 1 R9 2 2 0 7 VDRV+ 2 2 C81 1 C8 4 0. 1U F TBD0805 VDRV- C8 3 TBD0805 0 ADA4841- 1YR Z 1 U1 7 1 R9 3 2 6 0. 1U F C8 2 PD_N 3 N2 V8 5 4 2 VDRV+ 0 1 R9 0 2 TBD0805 C8 0 1 2 6 RED TP67 1 RED A B C CH4 1 R7 9 2 TBD0805 1 R8 0 2 1 R7 8 2 TBD0805 1 R862 TBD0805 1 R87 2 TBD0805 GND GND GND GND TP63 TP64 1 RED 1 RED TP66 1 RED 1 RED 1 TP65 TP68 7 EXT_COM VCM 22 1 R9 8 2 22 1 R9 7 2 22 R9 9 5 1 2 3 2700PF P8 GND C91 2700PF 2 GND C8 9 1 I N5/ I N2 2700PF 2 GND C8 8 1 I N4 GND 4 CH7/ CH3 CH6 ADC BUFFERS CONTI NUED 4 1 COM BL U TP2 2 COM VBI AS VBI AS 1 2 1 2 R10 62 GND 59 0 C9 3 0. 1U F 1 R10 92 0 1 R10 72 TBD080 5 1 R10 82 1 TBD0805 GND 59 0 C9 2 0. 1U F 1 R10 52 0 1 R10 32 TBD0805 1 R10 42 1 R10 22 TBD0805 1 2 3 V+ 7 N1 A N A L OG DE V CE S 0. 1U F C10 3 I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. 0 2 2 <PTDE_ENGI NEER> PTDE ENGI NEER anal og DESI GN VI EW <PRODUCT_1 > Topl evel AD7689/ 82/ 99/ 92 ADA4841- 1YR Z 1 U2 0 6 1 R11 82 N1 C10 2 N2 PD_N 8 5 0. 1U F C10 1 0 R11 62 TBD0805 V- V+ 4 VDRV- 3 1 7 VDRV+ 2 C9 7 2 1 0. 1U F C10 0 TBD0805 VDRV- C9 9 TBD0805 0 ADA4841- 1YR Z 1 U1 9 1 R11 72 6 0. 1U F C9 8 0 1 R11 42 PD_N 3 N2 V8 5 4 2 VDRV+ TBD0805 C9 6 1 2 REV TP70 1 RED THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . TBD0805 C9 5 49. 9 1 R11 32 C9 4 TBD0805 1 49. 9 R11 22 2 1 3 RED 5 1 Rev. PrB | Page 11 of 24 TP79 GND GND D 8 GND RED TP77 1 1 R1102 TBD0805 1 R111 2 TBD0805 GND GND GND GND RED 1 1 1 RED TP69 1 TP62 TP72 TP60 TP61 RED 1 RED RED 2700PF GND C10 5 1 2 I N7/ I N3 2700PF GND C10 4 1 2 DD SI ZE SCALE 1 1 OF 7 A REV APPROVED SHEET 5 DATE DRAWI NG NO. SCHEMATI C 22 1 R12 02 22 1 R11 92 I N6 REVI SI ON S DESCRI PTI O N A B C D Preliminary Technical Data EVAL-AD76MUXCBZ TP78 1 RED A B C SUPPLI ES CNV DI N SCK 1 1 1 1 OUT OUT OUT OUT OUT 8 DSPCLK OUT CONTROL OUT RESET BWR_N BRD_N BBUSY BCS_N BD<0. . 15> OUT AD<0. . 4> OUT 96_PI N_I / O IN IN IN IN SDO OUT OUT OUT GND DUT_I / O GND EN_7V_N EN_5V_N EN_3. 3V_N VI O_FPGA VPLLA2 VPLLA1 VFPGA VI O BL U TP2 7 BL U TP2 6 BL U TP2 5 BL U TP2 4 CNV DI N SDO SCK R128 VI O GND GND 7 TBD0603 0 R12 4 C10 7 C108 10K R12 3 GND 10K . 1UF GND 1 GND GND MCLK MCLK TP7 3 YEL 1 6 U6 VFPGA L6 GND L4 M4 C2 D5 E5 E3 E4 D3 G2 C1 P2 P3 P1 L3 N2 N1 J4 M2 M3 L2 N_CSO F4 M1 L1 K4 K5 K1 K2 E2 E1 F3 GND_PLL1 VPLLA1 GND N5 NCE DCLK DATA0 CLK2 CLK3 L5 TMS TDI TCK NCONFI G BANK_1 GND LA_D<0. . 31> LA_D<0. . 31> TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO J2 EP2C5F256C7 N G1 H5 F2 G5 PS_STATUS_N J 5 PS_CONFI G_N H4 PS_DCLK J1 F1 DATA ASDO C3 I O VCCD_PLL1CLK0 H2 MCLK D4 H1 CLK1 IO EN_5V_N EN_7V_N Y3 OUT 3 EN GND 2 GND 1 1 15K VCCA_PLL2 P3 V+ 5 7 4 3 100MH Z 4 4 VI O_FPGA 3 3 0 0 1 5 5 4 5 6 2 2 2 6 7 6 7 8 15K VI O P10 VCCI NT H7 L7 U6 R3 T3 P5 P4 T4 R4 T5 R5 T6 N8 T7 R7 10 R125 1 H10 13 10 11 9 8 9 GND 8 10 10K 2 14 11 GND 15 R130 VFPGA G9 P11 VCCI O1 VCCI O1 J7 B1 12 10K 1 G3 16 13 C110 2 2 D10 2 K3 R1 17 14 M5 VI O_FPGA BANK_2 VI O_FPGA VCCI O2 VCCI O3 GND POWER_FPGA A2 BANK_4 19 R126 R132 A15 LA_CLK1 20 16 20 12 9 11 23 10K 24 C109 GND T1 26 1000PF E12 U6 B14 A14 C13 C12 B13 A13 B11 B12 A12 A11 C11 G10 G11 B10 A10 F10 F9 D11 VCCA_PLL1 C7 21 17 21 18 15 12 13 14 15 16 17 18 19 22 18 R12 2 19 8 9 20 GND 10 3M2510- 5002U B R15 25 21 VPLLA2 VCCI O4 EP2C5F256C7 N J8 8N J9 4 28 7 K9 H9 29 1000PF T16 22 22 23 24 25 26 27 30 24 30 27 23 28 29 PS_CDONE_N VI O_FPGA PS_CONFI G_N PS_STATUS_N DATA N_CSO ASDO 25 D A16 U6 LA_CLK2 LA_CLK1 26 1 30 nCS 2 8 DATA PS_DCLK 6 DCLK DATA 5 ASDO ASDI GND 4 EPCS4SI GND B2 27 N_CSO A1 31 31 MSEL0 MSEL1 DSPCLK CLK7 VFPGA IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO LA_CLK2 F1 2 GND 3 GND BWR_N RESET CONTROL BBUSY BRD_N BCS_N ADCOK BD<11> AD<0> AD<1> AD<2> AD<3> AD<4> BD<12> BD<13> BD<14> BD<15> BD<10> BD<0> BD<1> BD<2> BD<3> BD<4> BD<5> BD<6> BD<7> BD<8> BD<9> PS_CDONE_N GND . 1UF C11 2 VFPGA . 1UF C11 4 EP2C5F256C7 N U6 L1 3 H1 3 D1 5 D1 6 E1 6 C1 4 D1 3 E1 4 D1 4 N1 2 M1 2 N1 3 N1 4 P1 4 P1 5 P1 6 N1 5 N1 6 M1 5 M1 6 M1 4 L1 4 L1 5 L1 6 K1 6 K1 5 H1 2 J12 G1 6 G1 5 F1 5 F1 6 J 11 H11 G1 2 G1 3 M1 3 VI O_FPGA D1 2 NSTATUS GND_PLL2 BANK_3 MSEL1 J13 MSEL0 K1 2 F11 VCCD_PLL2 H1 6 CLK4 CONF_DONE H1 5 CLK5 IO J15 CLK6 IO J16 GND R12 1 10K B15 28 GND A9 B9 A8 A7 B7 F7 F8 D8 B6 A6 G6 G7 C10 E7 E10 B16 G14 K14 R16 M7 M10 P7 P10 T2 G8 C9 E8 E9 H3 H14 J3 J14 M8 M9 P8 H8 P9 R2 T15 C8 29 32 33 34 35 36 EP2C5F256C7N M6 VI O_FPGA 31 37 GNDA_PLL2 EP2C5F256C7N E11 D6 C6 C5 C4 B5 A5 B4 A4 A3 B3 E6 F6 GNDA_PLL1 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO L8 T8 R8 T9 R9 N9 N10 T11 R11 P11 L9 L10 R10 T10 K11 K10 N11 P12 P13 T12 R12 L12 T13 R13 T14 R14 M11 L11 38 39 . 1UF GND C111 PS_DCLK A N A L OG DE V CE S VI O_FPGA OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. 10K R13 4 VI O_FPGA I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . . 1UF 1 . 1UF 2 3 4 5 6 C115 2 2 C11 9 . 1UF REV . 1UF . 1UF C11 7 10K R13 5 . 1UF P2 C116 U5 2 <PTDE_ENGI NEER> PTDE ENGI NEER f pga DESI GN VI EW <PRODUCT_1 > ADCOK R13 6 MSEL1 60. 4 1 R14 52 10K 1 R14 42 10K 1 R14 32 10K 1 R14 22 10K 1 R14 12 10K 1 R14 02 10K 1 R13 92 10K 1 R13 82 GND R13 7 0 CR1 . 1UF C12 3 A R15 0 0 CADCOK GND R15 1 VCCI O1 GND DD SI ZE SCALE DRAWI NG NO. SCHEMATI C VI O_FPGA VI O_FPGA APPROVED . 1UF 1 SHEET 6 . 1UF 1 DATE OF 7 A REV . 1UF REVI SI ON S DESCRI PTI O N VI O_FPGA C12 1 . 1UF DSPCLK CONTROL RESET BWR_N BRD_N BBUSY BCS_N MSEL0 2 Topl evel AD7689/ 82/ 99/ 92 C118 3 . 1UF 4 C120 2 2 . 1UF 5 C122 3 7 VCC 6 C131 VI O_FPGA C124 2 2 GND GND GND GND GND 7 . 1UF GND . 1UF IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO 40 C127 8 C125 GND . 1UF . 1UF Rev. PrB | Page 12 of 24 C126 Figure 7. Schematic, FPGA C129 1 C128 1 1 1 . 1UF 1 1 C130 1 1 C113 A B C D EVAL-AD76MUXCBZ Preliminary Technical Data EN_3. 3V_N Figure 8. Schematic, 96-Pin Interface Rev. PrB | Page 13 of 24 A B C D 8 8 7 7 BD<10> BD<11> BD<12> BD<13> BD<14> BD<15> BD<0> BD<1> BD<2> BD<3> BD<4> BD<5> BD<6> BD<7> BD<8> BD<9> 4 3 2 1 0 AD<0> AD<1> AD<2> AD<3> AD<4> OUT 6 OUT VDI G OUT GND OUT +5VA OUT - 5VA OUT +12VA OUT - 12VA OUT CONTROL OUT DSPCLK OUT BWR_N OUT RESET BCS_N OUT BBUSY OUT BRD_N OUT AD<0. . 4> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BD<0. . 15> OUT 6 GND - 12VA - 5VA +5VA RESET BD<12> DSPCLK AD<3> AD<1> VDI G BRD_N A1 0 A11 A1 2 A1 3 A1 4 A1 5 A1 6 A1 7 A1 8 A1 9 A2 0 A21 A2 2 A2 3 A2 4 A2 5 A2 6 A2 7 A2 8 A2 9 A3 0 A31 A3 2 A7 A8 A9 A2 A3 A4 A5 A6 A1 5 ERNI 53340 2 P4 5 GND - 5VA +5VA BD<11> BD<13> BD<10> BD<8> BD<9> BD<5> BD<6> BD<7> VDI G BD<2> BD<3> BD<4> BD<0> BD<1> CONTROL B1 0 B11 B1 2 B1 3 B1 4 B1 5 B1 6 B1 7 B1 8 B1 9 B2 0 B21 B2 2 B2 3 B2 4 B2 5 B2 6 B2 7 B2 8 B2 9 B3 0 B31 B3 2 B7 B8 B9 B2 B3 B4 B5 B6 B1 4 ERNI 53340 2 P4 4 GND +12VA - 5VA +5VA BBUSY BD<14> BD<15> AD<4> AD<2> AD<0> VDI G BWR_N BCS_N C1 0 C11 C1 2 C1 3 C1 4 C1 5 C1 6 C1 7 C1 8 C1 9 C2 0 C21 C2 2 C2 3 C2 4 C2 5 C2 6 C2 7 C2 8 C2 9 C3 0 C31 C3 2 C7 C8 C9 C2 C3 C4 C5 C6 C1 3 ERNI 53340 2 P4 3 THE EQUI PMEN T SHOW N HEREO N MAY BE PROTECTE D BY PATENT S OWNE D OR CONTROLLE D BY OWNE D ANALO G DEVI CES . OF ANALO G DEVI CES. OR FOR ANY OTHE R PURPOS E DETRI MENTA L TO THE I NTEREST S I N PART , OR USE D I N FURNI SHIGN I NFORMATIN O TO OTHERS , I T I S NOT TO BE REPRODUCE D OR COPI ED , I N WHOL E OR THIS DRAWI G N I S THE PROPERT Y OF ANALO G DEVI CE S I NC . A N A L OG DE V CE S 2 <PTDE_ENGI NEER> PTDE ENGI NEER 96_pin DESI GN VI EW <PRODUCT_1 > 2 Topl evel AD7689/ 82/ 99/ 92 REV REVI SI ON S DD SI ZE SCALE 1 1 SHEET DATE DRAWI NG NO. SCHEMATI C DESCRI PTI O N 7 OF 7 A REV APPROVED A B C D Preliminary Technical Data EVAL-AD76MUXCBZ EVAL-AD76MUXCBZ Preliminary Technical Data Figure 9. Top Side Silk-Screen (Viewed from top side) Figure 10. Inner Layer 1 (Viewed from top side) Rev. PrB | Page 14 of 24 Preliminary Technical Data EVAL-AD76MUXCBZ Figure 11. Ground Plane (Viewed from top side) Figure 12. Inner Layer 2 (Viewed from top side) Rev. PrB | Page 15 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data Figure 13.Inner Layer 3 (Viewed from top side) Figure 14. Bottom Layer (Viewed from top side) Rev. PrB | Page 16 of 24 Preliminary Technical Data EVAL-AD76MUXCBZ Figure 15. Bottom Layer (Viewed from Bottom Side) Rev. PrB | Page 17 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data 2) The part under evaluation is chosen from this menu. The device must be selected second. 1) The Run button starts the software. This button must be pressed first. 3) Interface modes are chosen here. This is the performance window. These controls are for locking and resetting the display axis to the data minimum and maximum values. 5) This window allow the samples to be taken once (F3) or continuous (F4). Also selects: Help screen, Save data (F5), Print (F8) and Quit (F10). The Help menu shows a description of the functionality of the chosen command. Figure 16. Setup Screen Rev. PrB | Page 18 of 24 4) This window is used to select the test type, number of Ksamples, and conversion mode (continuous or burst). For the test type choose from either: Histogram test AC Test Decimated AC Test Preliminary Technical Data EVAL-AD76MUXCBZ The ADC needs to be configured for input configuration, reference, channel to be converted, temperature sensor, and onchip low pass (LP) filter (optional) for full bandwidth (BW) or 1/4 BW. These next figures show the pull down configurations available. Note the default value when the program is started is indicated by the ; or unipolar to GND, ext reference, CH0, temperature sensor enabled and LP filter set to full BW. Figure 19 details the choices for the channel to be converted. Note that after updating the very first conversion (when using burst mode) will be of the last configuration since the ADC must complete one conversion for the configuration register to update. Figure 17 details the inputs (IN0-IN7) configuration. Refer to the datasheet for more information about the input configureations. Note that in the bipolar ranges, the input must not go below GND as this is intended for single supply systems where the amplfiers output swings midscale of the amplifier's supplies (V+ and GND). In bipolar range, the COM or paired channel must be set to this midscale voltage as well. Figure 19.Channel Select The Temp sensor can be used to monitor the temperature of the ADC. The displayed results should be in Volts format as opposed to Hex. Figure 20. Temperature Sensor Figure 21 details the bandwidth selection of the 1-pole low pass filter, which can reduce the noise from the amplifier circuit, if desired. Figure 17. Input Configuration Figure 18 details the reference selection. The choices are straight forward. Figure 21. Low Pass Filter Figure 18. Reference Selection Rev. PrB | Page 19 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data The results are displayed in this chart. Also, the cursor (yellow) can be dragged it to a desired location where the X-axis values and the Y-axis value will be displayed. These control the choice of chart type and X-units. Chart type selection of Histogram or Time and X-units of hexadecimal or Volts. This window shows the ADC range and LSB value in Volts. Different measurements are displayed here. The DC value, Transition Noise and other values Figure 22. Histogram Screen Rev. PrB | Page 20 of 24 Preliminary Technical Data EVAL-AD76MUXCBZ The results are displayed in this chart. Also, the cursor (yellow) can be dragged it to a desired location where the X-axis values and the Y-axis value will be displayed. These control the chart type choice of Frequency domain or Time domain and X axis units. AC test results are displayed here. Also the choice of viewing the amplitude of a certain FFT component can be selected from the FFT component menu. Choice of either a Kaiser window or a BlackmannHarris window from the is menu. Figure 23. FFT Screen Rev. PrB | Page 21 of 24 EVAL-AD76MUXCBZ Preliminary Technical Data The AC test can also be displayed in the Time Domain as shown below. To view the Time domain output, select Time in this menu. Figure 24. Time-Domain Screen Rev. PrB | Page 22 of 24 Preliminary Technical Data EVAL-AD76MUXCBZ The results are displayed in this chart. Also, the cursor (yellow) can be dragged it to a desired location where the X-axis values and the Y-axis value will be displayed. AC test results with decimated averaging are shown here. The SNR indicator also represents the dynamic range when no signal is present. The decimation ratio (Dratio) and number of Ksamples are entered here. The Nyquist frequency is displayed here as: FNYQUIST = Figure 25. Decimated (Averaging) Screen Rev. PrB | Page 23 of 24 FSAMPLE 2 * D RATIO EVAL-AD76MUXCBZ Preliminary Technical Data ORDERING GUIDE Evaluation Board Model EVAL-AD7682CBZ EVAL-AD7689CBZ EVAL-AD7699CBZ EVAL-AD7949CBZ EVAL-CONTROL BRD3Z Product AD7682BRMZ AD7689BRMZ AD7699BRMZ AD7949BRMZ Controller Board (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07084-0-11/07(PrB) Rev. PrB | Page 24 of 24