Pre-Production
This is a product in the pre-production phase of development. Device Ramtron International Corporation
characterization is complete and Ramtron does not expect to change the 1850 Ramtron Drive, Colorado Springs, CO 80921
specifications. Ramtron will issue a Product Change Notice if any (800) 545-FRAM, (719) 481-7000
specification changes are made. http://www.ramtron.com
Rev. 2.0
May 2010 Page 1 of 16
FM25V10
1Mb Serial 3V F-RAM Memory
Features
1M bit Ferroelectric Nonvolatile RAM
• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (10
14
) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 40 MHz Frequency
• Direct Hardware Replacement for Serial Flash
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Write Protection Scheme
• Hardware Protection
• Software Protection
Device ID and Serial Number
• Device ID reads out Manufacturer ID & Part ID
• Unique Serial Number (FM25VN10)
Low Voltage, Low Power
• Low Voltage Operation 2.0V – 3.6V
• 90 µA Standby Current (typ.)
• 5 µA Sleep Mode Current (typ.)
Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS SOIC Package
Description
The FM25V10 is a 1-megabit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by Serial
Flash and other nonvolatile memories.
Unlike Serial Flash, the FM25V10 performs write
operations at bus speed. No write delays are incurred.
Data is written to the memory array immediately
after it has been transferred to the device. The next
bus cycle may commence without the need for data
polling. The product offers very high write
endurance, orders of magnitude more endurance than
Serial Flash. Also, F-RAM exhibits lower power
consumption than Serial Flash.
These capabilities make the FM25V10 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of Serial Flash can
cause data loss.
The FM25V10 provides substantial benefits to users
of Serial Flash as a hardware drop-in replacement.
The devices use the high-speed SPI bus, which
enhances the high-speed write capability of F-RAM
technology. The FM25VN10 is offered with a unique
serial number that is read-only and can be used to
identify a board or system. Both devices incorporate
a read-only Device ID that allows the host to
determine the manufacturer, product density, and
product revision. The devices are guaranteed over an
industrial temperature range of -40°C to +85°C.
Pin Configuration
S
Q
W
VSS
VDD
HOLD
C
D
1
2
3
4
8
7
6
5
Pin Name Function
/S Chip Select
/W Write Protect
/HOLD Hold
C Serial Clock
D Serial Data Input
Q Serial Data Output
VDD Supply Voltage
VSS Ground
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 2 of 16
Instruction Decode
Clock Generator
Control Logic
Write Protect
Instruction Register
Address Register
Counter
16384 x 64
FRAM Array
17
Data I/O Register
8
Nonvolatile Status
Register
3
W
S
C
Q
D
HOLD
Figure 1. Block Diagram
Pin Descriptions
Pin Name I/O Description
/S Input Chip Select: This active-low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the C signal. A falling edge on /S must occur prior
to every op-code.
C Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 40 MHz and may be interrupted at
any time.
/HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on C or /S. All transitions on /HOLD must occur while C is low.
This pin has a weak internal pull-up (see R
IN
spec, pg 11). However, if it is not used,
the /HOLD pin should be tied to V
DD
.
/W Input Write Protect: This active-low pin prevents write operations to the Status Register
only. A complete explanation of write protection is provided on pages 6 and 7. If it is
not used, the /W pin should be tied to V
DD
.
D Input Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of C and is ignored at other times. It should always be driven to a valid
logic level to meet I
DD
specifications.
* D may be connected to Q for a single pin data interface.
Q Output Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* Q may be connected to D for a single pin data interface.
VDD Supply Power Supply
VSS Supply Ground
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 3 of 16
Overview
The FM25V10 is a serial F-RAM memory. The
memory array is logically organized as 131,072 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to Serial Flash. The major
differences between the FM25V10 and a Serial Flash
with the same pinout are the F-RAM’s superior write
performance, very high endurance, and lower power
consumption.
Memory Architecture
When accessing the FM25V10, the user addresses
128K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a three-
byte address. The complete address of 17-bits
specifies each byte address uniquely.
Most functions of the FM25V10 either are controlled
by the SPI interface or are handled automatically by
on-board circuitry. The access time for memory
operation is essentially zero, beyond the time needed
for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike Serial
Flash, it is not necessary to poll the device for a ready
condition since writes occur at bus speed. So, by the
time a new bus transaction can be shifted into the
device, a write operation will be complete. This is
explained in more detail in the interface section.
Users expect several obvious system benefits from
the FM25V10 due to its fast write cycle and high
endurance as compared to Serial Flash. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than Serial Flash
since it is completed quickly. By contrast, Serial
Flash requiring milliseconds to write is vulnerable to
noise during much of the cycle.
Serial Peripheral Interface – SPI Bus
The FM25V10 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to
40MHz. This high-speed serial bus provides high
performance serial communication to a host
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25V10 operates in SPI Mode 0 and 3.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25V10 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /S, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25V10 supports only modes 0 and 3. Figure 2
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25V10 on the rising edge of C and data is
expected on the first rising edge after /S goes active.
If the clock starts from a high state, it will fall prior to
the first data transfer in order to create the first rising
edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/S is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /S must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
SPI Mode 0: CPOL=0, CPHA=0
SPI Mode 3: CPOL=1, CPHA=1
Figure 2. SPI Modes 0 & 3
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 4 of 16
System Hookup
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25V10 devices
with a microcontroller that has a dedicated SPI port,
as Figure 3 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25V10 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 4 shows a configuration that uses
only three pins.
Figure 3. 2Mbit (256KB) System Configuration with SPI port
Figure 4. System Configuration without SPI port
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 5 of 16
Power Up to First Access
The FM25V10 is not accessible for a period of time
(t
PU
) after power up. Users must comply with the
timing parameter t
PU
, which is the minimum time
from V
DD
(min) to the first /S low.
Data Transfer
All data transfers to and from the FM25V10 occur in
8-bit groups. They are synchronized to the clock
signal (C), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of C. Outputs are driven from the falling edge of
clock C.
Command Structure
There are ten commands called op-codes that can be
issued by the bus master to the FM25V10. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function, such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name Description Op-code
WREN
Set Write Enable Latch 0000
0110b
WRDI
Write Disable 0000
0100b
RDSR
Read Status Register 0000
0101b
WRSR
Write Status Register 0000
0001b
READ
Read Memory Data 0000
0011b
FSTRD
Fast Read Memory Data 0000
1011b
WRITE
Write Memory Data 0000
0010b
SLEEP
Enter Sleep Mode 1011
1001b
RDID
Read Device ID 1001
1111b
SNR
Read S/N 1100
0011b
WREN – Set Write Enable Latch
The FM25V10 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for write
operations. These include writing the Status Register
(WRSR) and writing the memory (WRITE).
Sending the WREN op-code causes the internal Write
Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below illustrates the WREN command bus
configuration.
0 0 0 0 0 1 1 0
S
C
D
Q
Hi-Z
0 1 2 3 4 5 6 7
Figure 5. WREN Bus Configuration
WRDI – Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 6 illustrates the WRDI command bus
configuration.
0 0 0 0 0 1 0 0
S
C
D
Q
Hi-Z
0 1 2 3 4 5 6 7
Figure 6. WRDI Bus Configuration
RDSR – Read Status Register
The RDSR command allows the bus master to
verify the contents of the Status Register. Reading
Status provides information about the current state
of the write protection features. Following the
RDSR op-code, the FM25V10 will return one byte
with the contents of the Status Register. The Status
Register is described in detail in the section below.
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 6 of 16
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status Register. Prior to issuing a WRSR
command, the /W pin must be high or inactive. Prior
to sending the WRSR command, the user must send
a WREN command to enable writes. Note that
executing a WRSR command is a write operation
and therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR are shown
below.
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
Status Register & Write Protection
The write protection features of the FM25V10 are
multi-tiered. Taking the /W pin to a logic low state is
the hardware write-protect function. Status Register
write operations are blocked when /W is low. To
write the memory with /W high, a WREN op-code
must first be issued. Assuming that writes are enabled
using WREN and by /W, writes to memory are
controlled by the Status Register. As described
above, writes to the Status Register are performed
using the WRSR command and subject to the /W pin.
The Status Register is organized as follows.
Table 2. Status Register
Bit
7 6 5 4 3 2 1 0
Name
WPEN 1 0 0 BP1 BP0 WEL 0
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and
none of these bits can be modified. Note that bit 0
(“Ready” in Serial Flash) is unnecessary as the F-
RAM writes in real-time and is never busy, so it
reads out as a ‘0’. There is an exception to this when
the device is waking up from Sleep Mode, which is
described on the following page. The BP1 and BP0
control software write protection features. They are
nonvolatile (shaded yellow). The WEL flag indicates
the state of the Write Enable Latch. Attempting to
directly write the WEL bit in the Status Register has
no effect on its state. This bit is internally set and
cleared via the WREN and WRDI commands,
respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1 BP0 Protected Address Range
0 0 None
0 1 18000h to 1FFFFh (upper ¼)
1 0 10000h to 1FFFFh (upper ½)
1 1 00000h to 1FFFFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware /W
pin. When WPEN is low, the /W pin is ignored.
When WPEN is high, the /W pin controls write
access to the Status Register. Thus the Status Register
is write protected if WPEN=1 and /W=0.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
S
C
D
Q
S
C
D
Q
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 7 of 16
under any circumstances. This occurs if the BP1 and
BP0 bits are set to 1, the WPEN bit is set to 1, and
the /W pin is low. This occurs because the block
protect bits prevent writing memory and the /W
signal in hardware prevents altering the block protect
bits (if WPEN is high). Therefore in this condition,
hardware must be involved in allowing a write
operation. The following table summarizes the write
protection conditions.
Table 4. Write Protection
WEL WPEN /W Protected Blocks Unprotected Blocks Status Register
0 X X Protected Protected Protected
1 0 X Protected Unprotected Unprotected
1 1 0 Protected Unprotected Protected
1 1 1 Protected Unprotected Unprotected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the F-RAM technology. Unlike Serial
Flash, the FM25V10 can perform sequential writes at
bus speed. No page buffer is needed and any number
of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a three-byte address
value, which specifies the 17-bit address of the first
data byte of the write operation. Subsequent bytes are
data and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of
1FFFFh is reached, the counter will roll over to
00000h. Data is written MSB first. A write operation
is shown in Figure 9.
Unlike Serial Flash, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8
th
clock). The rising edge of /S terminates a WRITE
op-code operation. Asserting /W active in the middle
of a write operation will have no effect until the next
falling edge of /S.
Read Operation
After the falling edge of /S, the bus master can issue
a READ op-code. Following this instruction is a
three-byte address value (A16-A0), specifying the
address of the first data byte of the read operation.
After the op-code and address are complete, the D
pin is ignored. The bus master issues 8 clocks, with
one bit read out for each. Addresses are incremented
internally as long as the bus master continues to issue
clocks. If the last address of 1FFFFh is reached, the
counter will roll over to 00000h. Data is read MSB
first. The rising edge of /S terminates a READ op-
code operation and tri-states the Q pin. A read
operation is shown in Figure 10.
Fast Read Operation
The FM25V10 supports the FAST READ op-code
(0Bh) that is found on Serial Flash devices. It is
implemented for code compatibility with Serial Flash
devices. Following this instruction is a three-byte
address (A16-A0), specifying the address of the first
data byte of the read operation. A dummy byte
follows the address. It inserts one byte of read
latency. The D pin is ignored after the op-code, 3-
byte address, and dummy byte are complete. The bus
master issues 8 clocks, with one bit read out for each.
The Fast Read operation is otherwise the same as an
ordinary READ. If the last address of 1FFFFh is
reached, the counter will roll over to 00000h. Data is
read MSB first. The rising edge of /S terminates a
FAST READ op-code operation and tri-states the Q
pin. A Fast Read operation is shown in Figure 11.
Hold
The FM25V10 and FM25VN10 devices have a
/HOLD pin that can be used to interrupt a serial
operation without aborting it. If the bus master pulls
the /HOLD pin low while C is low, the current
operation will pause. Taking the /HOLD pin high
while C is low will resume an operation. The
transitions of /HOLD must occur while C is low, but
the C and /S pins can toggle during a hold state.
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 8 of 16
Figure 9. Memory Write with 3-Byte Address
Figure 10. Memory Read with 3-Byte Address
Figure 11. Fast Read with 3-Byte Address and Dummy Byte
76
012345670 1 2 3 5456701234567
op-code
0000101
MSB
17-bit Address
0 0 0 0 A1
X
X
X
X
76543210
LSB MSB LSB
Dat
a
1
A2
S
C
D
Q
A0
Dummy byte
76
012345670 1 2 345456701234567
op-code
0000001
MSB
17-bit
A
dd
r
ess
0
0 0 0 0 0
76543210
LSB MSB LSB
Dat
a
10
S
C
D
Q
A
16 A3 A1A2 A0
0 1 2 345670 1 2 345
op-c
ode
00000010
M
SB
17-bit Add
r
ess
00
6
0
00 0 0
S
C
D
Q
7
A
16 A1A2A3
45670
1 2 34567
A0
76543210
LSB MSB LSB
D
ata
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 9 of 16
Sleep Mode
A low power mode called Sleep Mode is
implemented on both FM25V10 and FM25VN10
devices. The device will enter this low power state
when the SLEEP op-code B9h is clocked-in and a
rising edge of /S is applied. Once in sleep mode, the
C and D pins are ignored and Q will be high-Z, but
the device continues to monitor the /S pin. On the
next falling edge of /S, the device will return to
normal operation within t
REC
(400 µs max.). The Q
pin remains in a hi-Z state during the wakeup period.
The device will not necessarily respond to an opcode
within the wakeup period. To start the wakeup
procedure, the controller may send a “dummy” read,
for example, and wait the remaining t
REC
time.
Figure 12. Sleep Mode Entry
Device ID
The FM25V10 and FM25VN10 devices can be interrogated for its manufacturer, product identification, and die
revision. The RDID op-code 9Fh allows the user to read the manufacturer ID and product ID, both of which are
read-only bytes. The JEDEC-assigned manufacturer ID places the Ramtron identifier in bank 7, therefore there are
six bytes of the continuation code 7Fh followed by the single byte C2h. There are two bytes of product ID, which
includes a Family code, a Density code, a Sub code, and Product Revision code.
Table 6. Manufacturer and Product ID
Bit
7 6 5 4 3 2 1 0 Hex
Manufacturer ID 0 1 1 1 1 1 1 1 7F Continuation code
0 1 1 1 1 1 1 1 7F Continuation code
0 1 1 1 1 1 1 1 7F Continuation code
0 1 1 1 1 1 1 1 7F Continuation code
0 1 1 1 1 1 1 1 7F Continuation code
0 1 1 1 1 1 1 1 7F Continuation code
1 1 0 0 0 0 1 0 C2 JEDEC assigned Ramtron C2h in bank 7
Family Density Hex
Device ID (1
st
Byte) 0 0 1 0 0 1 0 0 24h Density: 01h=128K, 02h=256K, 03h=512K, 04=1M
Sub Rev. Rsvd
Device ID (2
n
d
Byte) 0 0 0 0 0 0 0 0 00h 00h=FM25V10, 01h=FM25VN10
Figure 13. Read Device ID
S
C
D
Q
Enter Sleep
Mode
S
C
D
Q
7Fh … 7Fh C2
h
00
h
Six bytes of continuation code 7Fh
9Fh
24
h
1 6
. . . . . . .
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 10 of 16
Unique Serial Number (FM25VN10 only)
The FM25VN10 device incorporates a read-only 8-
byte serial number. It can be used to uniquely
identify a pc board or system. The serial number
includes a 40-bit unique number, an 8-bit CRC, and a
16-bit number that can be defined upon request by
the customer. If a customer-specific number is not
requested, the 16-bit Customer Identifier is 0x0000.
The serial number is read by issuing the SNR op-
code (C3h).
The 8-bit CRC value can be used to compare to the
value calculated by the controller. If the two values
match, then the communication between slave and
master was performed without errors. The function
(shown below) is used to calculate the CRC value.
To perform the calculation, 7 bytes of data are filled
into a memory buffer in the same order as they are
read from the part – i.e. byte7, byte6, byte5, byte4,
byte3, byte2, byte1 of the serial number. The
calculation is performed on the 7 bytes, and the result
should match the final byte out from the part which is
byte0, the 8-bit CRC value.
CUSTOMER IDENTIFIER * 40-bit UNIQUE NUMBER 8-bit CRC
SN(63:56) SN(55:48) SN(47:40) SN(39:32) SN(31:24) SN(23:16) SN(15:8) SN(7:0)
* Contact factory for requesting a customer identifier number.
Figure 14. 8-Byte Serial Number (read-only)
Function to Calculate CRC
BYTE calcCRC8( BYTE* pData, int nBytes )
{
static BYTE crctable[256] = {
0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
};
BYTE crc = 0;
while( nBytes-- ) crc = crctable[crc ^ *pData++];
return crc;
}
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 11 of 16
Figure 15. Read Serial Number
Endurance
The FM25V10 and FM25VN10 devices are capable
of being accessed at least 10
14
times, reads or writes.
An F-RAM memory operates with a read and restore
mechanism. Therefore, an endurance cycle is applied
on a row basis for each access (read or write) to the
memory array. The F-RAM architecture is based on
an array of rows and columns. Rows are defined by
A16-A3 and column addresses by A2-A0. See Block
Diagram (pg 2) which shows the array as 16K rows
of 64-bits each. The entire row is internally accessed
once whether a single byte or all eight bytes are read
or written. Each byte in the row is counted only once
in an endurance calculation. The table below shows
endurance calculations for 64-byte repeating loop,
which includes an op-code, a starting address, and a
sequential 64-byte data stream. This causes each byte
to experience one endurance cycle through the loop.
F-RAM read and write endurance is virtually
unlimited even at 40MHz clock rate.
Table 7. Time to Reach 100 Trillion Cycles for Repeating 64-byte Loop
SCK Freq
(MHz)
Endurance
Cycles/sec.
Endurance
Cycles/year
Years to Reach
10
14
Cycles
40 73,520 2.32 x 10
12
43.2
20 36,760 1.16 x 10
12
86.4
10 18,380 5.79 x 10
11
172.7
5 9,190 2.90 x 10
11
345.4
S
C
D
Q
Byte 7 Byte 6 . . .
C3
h
. . . . . . .
Byte 1 Byte 0
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 12 of 16
Electrical Specifications
Absolute Maximum Ratings
Symbol Description Ratings
V
DD
Power Supply Voltage with respect to V
SS
-1.0V to +4.5V
V
IN
Voltage on any pin with respect to V
SS
-1.0V to +4.5V
and V
IN
< V
DD
+1.0V
T
STG
Storage Temperature -55°C to + 125°C
T
LEAD
Lead Temperature (Soldering, 10 seconds) 260° C
V
ESD
Electrostatic Discharge Voltage
- Human Body Model
(AEC-Q100-002 Rev. E)
- Charged Device Model
(AEC-Q100-011 Rev. B)
- Machine Model
(AEC-Q100-003 Rev. E)
4kV
1.25kV
200V
Package Moisture Sensitivity Level MSL-1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (T
A
= -40°C to + 85°C, V
DD
= 2.0V to 3.6V unless otherwise specified)
Symbol Parameter Min Typ Max Units Notes
V
DD
Power Supply Voltage 2.0 3.3 3.6 V
I
DD
Power Supply Operating Current
@
C = 1 MHz
@
C = 40 MHz
-
1.5
0.3
3.0
mA
mA
1
I
SB
Standby Current 90 150
µ
A
2
I
ZZ
Sleep Mode Current 5 8
µ
A 3
I
LI
Input Leakage Current - ±1
µ
A 4
I
LO
Output Leakage Current - ±1
µ
A 4
V
IH
Input High Voltage 0.7 V
DD
V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.3 V
DD
V
V
OH1
Output High Voltage (
I
OH
= -1 mA, V
DD
=2.7V)
2.4 - V
V
OH2
Output High Voltage (
I
OH
= -100 µA)
V
DD
-0.2 - V
V
OL1
Output Low Voltage (
I
OL
= 2 mA, V
DD
=2.7V)
- 0.4 V
V
OL2
Output Low Voltage (
I
OL
= 150 µA)
- 0.2 V
R
IN
Input Resistance (/HOLD pin)
For V
IN
= V
IH
(min)
For V
IN
= V
IL
(max)
40
1
KΩ
MΩ
5
Notes
1.
C toggling between V
DD
-0.2V and V
SS
, other inputs V
SS
or V
DD
-0.2V.
2.
/S=V
DD
. All inputs V
SS
or V
DD
.
3.
In Sleep mode and /S=V
DD
. All inputs V
SS
or V
DD
.
4.
V
SS
≤ V
IN
≤ V
DD
and V
SS
≤ V
OUT
≤ V
DD
.
5.
The input pull-up circuit is stronger (> 40KΩ) when the input voltage is above V
IH
and weak (> 1MΩ) when the input
voltage is below V
IL
.
Data Retention (T
A
= -40°C to + 85°C)
Parameter Min Max Units Notes
Data Retention 10 - Years
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 13 of 16
AC Parameters (T
A
= -40°C to + 85°C, C
L
= 30pF, unless otherwise specified)
V
DD
2.0 to 2.7V V
DD
2.7 to 3.6V
Symbol Parameter Min Max Min Max Units Notes
f
C
C Clock Frequency 0 25 0 40 MHz
t
CH
Clock High Time 20 11 ns 1
t
CL
Clock Low Time 20 11 ns 1
t
CSU
Chip Select Setup 12 10 ns
t
CSH
Chip Select Hold 12 10 ns
t
OD
Output Disable Time 20 12 ns 2
t
ODV
Output Data Valid Time 18 9 ns
t
OH
Output Hold Time 0 0 ns
t
D
Deselect Time 60 40 ns
t
R
Data In Rise Time 50 50 ns 2,3
t
F
Data In Fall Time 50 50 ns 2,3
t
SU
Data Setup Time 8 5 ns
t
H
Data Hold Time 8 5 ns
t
HS
/HOLD Setup Time 12 10 ns
t
HH
/HOLD Hold Time 12 10 ns
t
HZ
/HOLD Low to Hi-Z 25 20 ns 2
t
LZ
/HOLD High to Data Active 25 20 ns 2
Notes
1. t
CH
+ t
CL
= 1/f
C
.
2.
This parameter is characterized but not 100% tested.
3. Rise and fall times measured between 10% and 90% of waveform.
Capacitance (T
A
= 25° C, f=1.0 MHz, V
DD
= 3.3V)
Symbol Parameter Min Max Units Notes
C
O
Output Capacitance (Q) - 8 pF 1
C
I
Input Capacitance - 6 pF 1
Notes
1.
This parameter is characterized and not 100% tested.
AC Test Conditions
Input Pulse Levels 10% and 90% of V
DD
Input rise and fall times 3 ns
Input and output timing levels 0.5 V
DD
Output Load Capacitance 30 pF
Serial Data Bus Timing
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 14 of 16
/HOLD Timing
S
C
Q
HOLD
t
HS
t
HH
t
HZ
t
LZ
t
HS
t
HH
Power Cycle Timing
VDD min.
VDD
S
tVR
tPD
tPU
tVF
Power Cycle & Sleep Timing (T
A
= -40° C to + 85° C, V
DD
= 2.0V to 3.6V, unless otherwise specified)
Symbol Parameter Min Max Units Notes
t
VR
V
DD
Rise Time 50 -
µ
s/V 1,2
t
VF
V
DD
Fall Time 100 -
µ
s/V 1,2
t
PU
Power Up (V
DD
min) to First Access (/S low) 250 -
µ
s
t
PD
Last Access (/S high) to Power Down (V
DD
min) 0 -
µ
s
t
REC
Recovery Time from Sleep Mode - 400
µ
s
Notes
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on V
DD
waveform.
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 15 of 16
Mechanical Drawing
8-pin SOIC (JEDEC MS-012 variation AA)
Pin 1
3.90
±
0.10 6.00
±
0.20
4.90
±
0.10
0.10
0.25
1.35
1.75
0.33
0.51
1.27 0.10 mm
0.25
0.50
45
°
0.40
1.27
0.19
0.25
0°- 8°
Recommended PCB Footprint
7.70
0.65
1.27
2.00
3.70
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXX= part number, P=package type
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int’l Corp, YY=year, WW=work week
Example: FM25V10, “Green”/RoHS SOIC package,
Rev. A, Lot 9646447, Year 2010, Work Week 11
Without S/N feature With S/N feature
FM25V10-G FM25VN10-G
A9646447 A9646447
RIC1011 RIC1011
XXXXXX-P
RLLLLLLL
RICYYWW
FM25V10 - 1Mb SPI FRAM
Rev. 2.0
May 2010 Page 16 of 16
Revision History
Revision
Date
Summary
1.0 8/29/2008 Initial release.
1.1 10/6/2009 Updated ESD ratings. Added tape and reel ordering information. Updated
lead temperature rating in Abs Max table. Expanded CRC check description.
2.0 5/25/2010 Changed to Pre-Production status. Changed part marking scheme.
Ordering Information
Part Number Features Operating
Voltage
Package
FM25V10-G Device ID 2.0-3.6V 8-pin “Green”/RoHS SOIC
FM25VN10-G Device ID, S/N 2.0-3.6V 8-pin “Green”/RoHS SOIC
FM25V10-GTR Device ID 2.0-3.6V 8-pin “Green”/RoHS SOIC
in Tape & Reel
FM25VN10-GTR Device ID, S/N 2.0-3.6V 8-pin “Green”/RoHS SOIC
in Tape & Reel
